Re: [U-Boot] omap3: Is lowlevel_init() ever called?

2009-12-03 Thread Premi, Sanjeev
 -Original Message-
 From: u-boot-boun...@lists.denx.de 
 [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Premi, Sanjeev
 Sent: Monday, November 30, 2009 11:41 PM
 To: u-boot@lists.denx.de
 Subject: [U-Boot] omap3: Is lowlevel_init() ever called?
 
 Hi all,
 
 I have been trying to debug 'strange' clock settings in the 
 omap3evm; that would
 surface quite infrequently. However, today I was able to get 
 them regularly.
 
 Symptom: the MPU clock is set at 381MHz instead of expected 500MHz.
 
 Tracing back from prcm_init() to s_init() to lowlevel_init() 
 and cpu_init_crit()
 I feel that lowlevel_init() is being skipped at together.
 
 In the patch below, I am updating a flag on very beginning of 
 s_init() and later
 printing in print_cpuinfo(). To exclude any other (possible) 
 foul-play by stray
 pointer, I initialized this flag to 11 and expect it to be 55 
 after s_init() is
 called. But the value remains 11 - when printed in print_cpuinfo().
 
 Also, CONFIG_SKIP_LOWLEVEL_INIT is not defined in omap3_evm_config.
 
 Though I am at 2009.08, I did not see any differences in 
 start.S that could have
 an apparent effect.
 
 Am I missing something completely?

Ok. I was misled by a portion of code+comment that states:
[quote]Copy DPLL code into SRAM[/quote] but goes on to copy
384*32 bytes.

I don't understand the startup bit of this code well, so
have few doubts:

1) What does the magic number #384 correspond to?
   384 * 32 = 12288 (0x3000)

2) Going by the comment, we possibly need to copy only the
   function _go_to_speed and constants used in it.

   Currently, we seem to be copying and relocating 0x3000 bytes.
   Isn't it an overhead?

3) While we are executing from SRAM, the variables are (possibly)
   being updated in relocated offsets, not 'in place' expected
   by the code.

   This goes with the behavior I described earlier.

I have made changes to u-boot to optimize the re-execution of the
code detecting silicon version for OMAP3. I have been able to make
it work by calling it twice - once when execution happens from
SRAM and then again in arch_cpu_init().

However, I feel we can optimize this - not just detecting si revision;
but amount of code copied and relocated.

Answers to 3 questions above will help me a lot.

Best regards,
Sanjeev

 
 Best regards,
 Sanjeev
 
 
 
 diff --git a/cpu/arm_cortexa8/omap3/board.c 
 b/cpu/arm_cortexa8/omap3/board.c
 index 939ed6c..5dfd8f3 100644
 --- a/cpu/arm_cortexa8/omap3/board.c
 +++ b/cpu/arm_cortexa8/omap3/board.c
 @@ -42,6 +42,8 @@ extern omap3_sysinfo sysinfo;
  
  extern u32 is_mem_sdr(void);
  
 +int s_init_flag=11;
 +
  
 /*
 *
   * Routine: delay
   * Description: spinning delay to use before udelay works
 @@ -193,6 +195,8 @@ void s_init(void)
  {
   int in_sdram = is_running_in_sdram();
  
 + s_init_flag=55;
 +
   watchdog_init();
  
   try_unlock_memory();
 diff --git a/cpu/arm_cortexa8/omap3/lowlevel_init.S 
 b/cpu/arm_cortexa8/omap3/lowlevel_init.S
 index 73063ec..d83dd53 100644
 --- a/cpu/arm_cortexa8/omap3/lowlevel_init.S
 +++ b/cpu/arm_cortexa8/omap3/lowlevel_init.S
 @@ -174,7 +174,11 @@ lowlevel_init:
   ldr sp, SRAM_STACK
   str ip, [sp]/* stash old link register */
   mov ip, lr  /* save link reg across call */
 + nop
 + nop
   bl  s_init  /* go setup pll, mux, memory */
 + nop
 + nop
   ldr ip, [sp]/* restore save ip */
   mov lr, ip  /* restore link reg */
  
 diff --git a/cpu/arm_cortexa8/omap3/sys_info.c 
 b/cpu/arm_cortexa8/omap3/sys_info.c
 index 2fb6c10..2f29032 100644
 --- a/cpu/arm_cortexa8/omap3/sys_info.c
 +++ b/cpu/arm_cortexa8/omap3/sys_info.c
 @@ -31,6 +31,8 @@
  #include asm/arch/sys_proto.h
  #include i2c.h
  
 +extern int s_init_flag;
 +
  extern omap3_sysinfo sysinfo;
  static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
  static struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
 @@ -414,6 +416,8 @@ int print_cpuinfo (void)
   cpu_s, sec_s, rev_s[get_cpu_rev()],
   (cpu_family == CPU_AM35XX) ?  :  CPU-OPP2);
  
 + printf (s_init_flag = %d\n, s_init_flag);
 + 
   return 0;
  }
  #endif   /* CONFIG_DISPLAY_CPUINFO */
 
 ==
 
 U-Boot 2009.08-00047-gd5ef5fe-dirty (Nov 30 2009 - 23:15:59)
 
 OMAP3430/3530-GP ES3.1, CPU-OPP2 L3-165MHz
 s_init_flag = 11
 OMAP3 EVM board + LPDDR/NAND
 DRAM:  128 MB
 NAND:  256 MiB
 In:serial
 Out:   serial
 Err:   serial
 Die ID #6092000404032d460c01201a
 Net:   smc911x-0
 Hit any key to stop autoboot:  0
 OMAP3_EVM #
 OMAP3_EVM #
 OMAP3_EVM #
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 U-Boot@lists.denx.de
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[U-Boot] omap3: Is lowlevel_init() ever called?

2009-11-30 Thread Premi, Sanjeev
Hi all,

I have been trying to debug 'strange' clock settings in the omap3evm; that would
surface quite infrequently. However, today I was able to get them regularly.

Symptom: the MPU clock is set at 381MHz instead of expected 500MHz.

Tracing back from prcm_init() to s_init() to lowlevel_init() and cpu_init_crit()
I feel that lowlevel_init() is being skipped at together.

In the patch below, I am updating a flag on very beginning of s_init() and later
printing in print_cpuinfo(). To exclude any other (possible) foul-play by stray
pointer, I initialized this flag to 11 and expect it to be 55 after s_init() is
called. But the value remains 11 - when printed in print_cpuinfo().

Also, CONFIG_SKIP_LOWLEVEL_INIT is not defined in omap3_evm_config.

Though I am at 2009.08, I did not see any differences in start.S that could have
an apparent effect.

Am I missing something completely?

Best regards,
Sanjeev



diff --git a/cpu/arm_cortexa8/omap3/board.c b/cpu/arm_cortexa8/omap3/board.c
index 939ed6c..5dfd8f3 100644
--- a/cpu/arm_cortexa8/omap3/board.c
+++ b/cpu/arm_cortexa8/omap3/board.c
@@ -42,6 +42,8 @@ extern omap3_sysinfo sysinfo;
 
 extern u32 is_mem_sdr(void);
 
+int s_init_flag=11;
+
 /**
  * Routine: delay
  * Description: spinning delay to use before udelay works
@@ -193,6 +195,8 @@ void s_init(void)
 {
int in_sdram = is_running_in_sdram();
 
+   s_init_flag=55;
+
watchdog_init();
 
try_unlock_memory();
diff --git a/cpu/arm_cortexa8/omap3/lowlevel_init.S 
b/cpu/arm_cortexa8/omap3/lowlevel_init.S
index 73063ec..d83dd53 100644
--- a/cpu/arm_cortexa8/omap3/lowlevel_init.S
+++ b/cpu/arm_cortexa8/omap3/lowlevel_init.S
@@ -174,7 +174,11 @@ lowlevel_init:
ldr sp, SRAM_STACK
str ip, [sp]/* stash old link register */
mov ip, lr  /* save link reg across call */
+   nop
+   nop
bl  s_init  /* go setup pll, mux, memory */
+   nop
+   nop
ldr ip, [sp]/* restore save ip */
mov lr, ip  /* restore link reg */
 
diff --git a/cpu/arm_cortexa8/omap3/sys_info.c 
b/cpu/arm_cortexa8/omap3/sys_info.c
index 2fb6c10..2f29032 100644
--- a/cpu/arm_cortexa8/omap3/sys_info.c
+++ b/cpu/arm_cortexa8/omap3/sys_info.c
@@ -31,6 +31,8 @@
 #include asm/arch/sys_proto.h
 #include i2c.h
 
+extern int s_init_flag;
+
 extern omap3_sysinfo sysinfo;
 static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
 static struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
@@ -414,6 +416,8 @@ int print_cpuinfo (void)
cpu_s, sec_s, rev_s[get_cpu_rev()],
(cpu_family == CPU_AM35XX) ?  :  CPU-OPP2);
 
+   printf (s_init_flag = %d\n, s_init_flag);
+   
return 0;
 }
 #endif /* CONFIG_DISPLAY_CPUINFO */

==

U-Boot 2009.08-00047-gd5ef5fe-dirty (Nov 30 2009 - 23:15:59)

OMAP3430/3530-GP ES3.1, CPU-OPP2 L3-165MHz
s_init_flag = 11
OMAP3 EVM board + LPDDR/NAND
DRAM:  128 MB
NAND:  256 MiB
In:serial
Out:   serial
Err:   serial
Die ID #6092000404032d460c01201a
Net:   smc911x-0
Hit any key to stop autoboot:  0
OMAP3_EVM #
OMAP3_EVM #
OMAP3_EVM #
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