> -Original Message-
> From: ChiaWei Wang
> Sent: Monday, December 14, 2020 1:54 PM
> To: tr...@konsulko.com; u-boot@lists.denx.de; Ryan Chen
>
> Cc: BMC-SW ; Dylan Hung
>
> Subject: [PATCH 2/7] ram: aspeed: Add AST2600 DRAM control support
>
> From: Dylan Hung
>
> AST2600 supports DDR4 SDRAM with maximum speed DDR4-1600.
> The DDR4 DRAM types including 128MbX16 (2Gb), 256MbX16 (4Gb),
> 512MbX16 (8Gb), 1GbX16 (16Gb), and 1GbX8 TwinDie (16Gb) are supported.
>
> Signed-off-by: Dylan Hung
> Signed-off-by: Chia-Wei, Wang
Reviewed-by: Ryan Chen
> ---
> .../include/asm/arch-aspeed/sdram_ast2600.h | 163 +++
> drivers/ram/aspeed/Kconfig| 61 +-
> drivers/ram/aspeed/Makefile |3 +-
> drivers/ram/aspeed/sdram_ast2600.c| 1061
> +
> 4 files changed, 1286 insertions(+), 2 deletions(-) create mode 100644
> arch/arm/include/asm/arch-aspeed/sdram_ast2600.h
> create mode 100644 drivers/ram/aspeed/sdram_ast2600.c
>
> diff --git a/arch/arm/include/asm/arch-aspeed/sdram_ast2600.h
> b/arch/arm/include/asm/arch-aspeed/sdram_ast2600.h
> new file mode 100644
> index 00..d2408c0020
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-aspeed/sdram_ast2600.h
> @@ -0,0 +1,163 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (c) Aspeed Technology Inc.
> + */
> +#ifndef _ASM_ARCH_SDRAM_AST2600_H
> +#define _ASM_ARCH_SDRAM_AST2600_H
> +
> +/* keys for unlocking HW */
> +#define SDRAM_UNLOCK_KEY 0xFC600309
> +#define SDRAM_VIDEO_UNLOCK_KEY 0x00440003
> +
> +/* Fixed priority DRAM Requests mask */
> +#define REQ_PRI_VGA_HW_CURSOR_R 0
> +#define REQ_PRI_VGA_CRT_R 1
> +#define REQ_PRI_SOC_DISPLAY_CTRL_R 2
> +#define REQ_PRI_PCIE_BUS1_RW3
> +#define REQ_PRI_VIDEO_HIGH_PRI_W4
> +#define REQ_PRI_CPU_RW 5
> +#define REQ_PRI_SLI_RW 6
> +#define REQ_PRI_PCIE_BUS2_RW7
> +#define REQ_PRI_USB2_0_HUB_EHCI1_DMA_RW 8 #define
> +REQ_PRI_USB2_0_DEV_EHCI2_DMA_RW 9
> +#define REQ_PRI_USB1_1_UHCI_HOST_RW 10
> +#define REQ_PRI_AHB_BUS_RW 11
> +#define REQ_PRI_CM3_DATA_RW 12
> +#define REQ_PRI_CM3_INST_R 13
> +#define REQ_PRI_MAC0_DMA_RW 14
> +#define REQ_PRI_MAC1_DMA_RW 15
> +#define REQ_PRI_SDIO_DMA_RW 16
> +#define REQ_PRI_PILOT_ENGINE_RW 17
> +#define REQ_PRI_XDMA1_RW18
> +#define REQ_PRI_MCTP1_RW19
> +#define REQ_PRI_VIDEO_FLAG_RW 20
> +#define REQ_PRI_VIDEO_LOW_PRI_W 21
> +#define REQ_PRI_2D_ENGINE_DATA_RW 22
> +#define REQ_PRI_ENC_ENGINE_RW 23
> +#define REQ_PRI_MCTP2_RW24
> +#define REQ_PRI_XDMA2_RW25
> +#define REQ_PRI_ECC_RSA_RW 26
> +
> +#define MCR30_RESET_DLL_DELAY_EN BIT(4)
> +#define MCR30_MODE_REG_SEL_SHIFT 1
> +#define MCR30_MODE_REG_SEL_MASK GENMASK(3, 1)
> +#define MCR30_SET_MODE_REG BIT(0)
> +
> +#define MCR30_SET_MR(mr) ((mr << MCR30_MODE_REG_SEL_SHIFT) |
> +MCR30_SET_MODE_REG)
> +
> +#define MCR34_SELF_REFRESH_STATUS_MASK GENMASK(30, 28)
> +
> +#define MCR34_ODT_DELAY_SHIFT12
> +#define MCR34_ODT_DELAY_MASK GENMASK(15, 12)
> +#define MCR34_ODT_EXT_SHIFT 10
> +#define MCR34_ODT_EXT_MASK GENMASK(11, 10)
> +#define MCR34_ODT_AUTO_ONBIT(9)
> +#define MCR34_ODT_EN BIT(8)
> +#define MCR34_RESETN_DIS BIT(7)
> +#define MCR34_MREQI_DIS BIT(6)
> +#define MCR34_MREQ_BYPASS_DISBIT(5)
> +#define MCR34_RGAP_CTRL_EN BIT(4)
> +#define MCR34_CKE_OUT_IN_SELF_REF_DISBIT(3)
> +#define MCR34_FOURCE_SELF_REF_EN BIT(2)
> +#define MCR34_AUTOPWRDN_EN BIT(1)
> +#define MCR34_CKE_EN BIT(0)
> +
> +#define MCR38_RW_MAX_GRANT_CNT_RQ_SHIFT 16
> +#define MCR38_RW_MAX_GRANT_CNT_RQ_MASK GENMASK(20, 16)
> +
> +/* default request queued limitation mask (0xFFBBFFF4) */
> +#define MCR3C_DEFAULT_MASK
> \
> + ~(REQ_PRI_VGA_HW_CURSOR_R | REQ_PRI_VGA_CRT_R |
> REQ_PRI_PCIE_BUS1_RW | \
> + REQ_PRI_XDMA1_RW | REQ_PRI_2D_ENGINE_DATA_RW)
> +
> +#define MCR50_RESET_ALL_INTR BIT(31)
> +#define SDRAM_CONF_ECC_AUTO_SCRUBBINGBIT(9)
> +#define SDRAM_CONF_SCRAMBLE BIT(8)
> +#define SDRAM_CONF_ECC_ENBIT(7)
> +#define SDRAM_CONF_DUALX8BIT(5)
> +#define SDRAM_CONF_DDR4 BIT(4)
> +#define SDRAM_CONF_VGA_SIZE_SHIFT2
> +#define SDRAM_CONF_VGA_SIZE_MASK GENMASK(3, 2)
> +#define SDRAM_CONF_CAP_SHIFT 0
> +#define SDRAM_CONF_CAP_MASK GENMASK(1, 0)
> +
> +#define SDRAM_CONF_CAP_256M 0
> +#define SDRAM_CONF_CAP_512M 1
> +#define SDRAM_CONF_CAP_1024M 2
> +#define SDRAM_CONF_CAP_2048M 3
> +#define SDRAM_CONF_ECC_SETUP
>
