RE: [PATCH v2 6/6] cmd: nand: Add new optional sub-command 'onfi'
Hi Alex, -- Override the ONFI timing mode at runtime. Signed-off-by: Alexander Dahl --- Tested-by: Mihai Sain I tested your new command on a new board/soc sam9x75-curiosity 😊 I find it very very useful ! I also rounded the master clock to 270 MHz 😊 Thanks. => nand info Device 0: nand0, sector size 256 KiB Manufacturer MACRONIX Model MX30LF4G28AD Device size512 MiB Page size 4096 b OOB size 256 b Erase size 262144 b ecc strength 8 bits ecc step size 512 b subpagesize 4096 b options 0x40004200 bbt options 0x00028000 => hsmc decode MCK rate: 270 MHz SMC_SETUP2: 0x0004 SMC_PULSE2: 0x0c070d05 SMC_CYCLE2: 0x000c000d SMC_MODE2: 0x001f0003 NCS_RD: setup: 0 (0 ns), pulse: 12 (36 ns), hold: 0 (0 ns), cycle: 12 (36 ns) NRD: setup: 0 (0 ns), pulse: 7 (21 ns), hold: 5 (15 ns), cycle: 12 (36 ns) NCS_WR: setup: 0 (0 ns), pulse: 13 (39 ns), hold: 0 (0 ns), cycle: 13 (39 ns) NWE: setup: 4 (12 ns), pulse: 5 (15 ns), hold: 4 (12 ns), cycle: 13 (39 ns) Standard read applied TDF optimization enabled TDF cycles: 15 (45 ns) Data Bus Width: 8-bit bus NWAIT Mode: 0 Write operation controlled by NWE signal Read operation controlled by NRD signal => nand onfi 2 => hsmc decode MCK rate: 270 MHz SMC_SETUP2: 0x0003 SMC_PULSE2: 0x0e090e06 SMC_CYCLE2: 0x000e000e SMC_MODE2: 0x001f0003 NCS_RD: setup: 0 (0 ns), pulse: 14 (42 ns), hold: 0 (0 ns), cycle: 14 (42 ns) NRD: setup: 0 (0 ns), pulse: 9 (27 ns), hold: 5 (15 ns), cycle: 14 (42 ns) NCS_WR: setup: 0 (0 ns), pulse: 14 (42 ns), hold: 0 (0 ns), cycle: 14 (42 ns) NWE: setup: 3 (9 ns), pulse: 6 (18 ns), hold: 5 (15 ns), cycle: 14 (42 ns) Standard read applied TDF optimization enabled TDF cycles: 15 (45 ns) Data Bus Width: 8-bit bus NWAIT Mode: 0 Write operation controlled by NWE signal Read operation controlled by NRD signal => nand onfi 1 => hsmc decode MCK rate: 270 MHz SMC_SETUP2: 0x0003 SMC_PULSE2: 0x110a1109 SMC_CYCLE2: 0x00110011 SMC_MODE2: 0x001f0003 NCS_RD: setup: 0 (0 ns), pulse: 17 (51 ns), hold: 0 (0 ns), cycle: 17 (51 ns) NRD: setup: 0 (0 ns), pulse: 10 (30 ns), hold: 7 (21 ns), cycle: 17 (51 ns) NCS_WR: setup: 0 (0 ns), pulse: 17 (51 ns), hold: 0 (0 ns), cycle: 17 (51 ns) NWE: setup: 3 (9 ns), pulse: 9 (27 ns), hold: 5 (15 ns), cycle: 17 (51 ns) Standard read applied TDF optimization enabled TDF cycles: 15 (45 ns) Data Bus Width: 8-bit bus NWAIT Mode: 0 Write operation controlled by NWE signal Read operation controlled by NRD signal => nand onfi 3 => hsmc decode MCK rate: 270 MHz SMC_SETUP2: 0x0004 SMC_PULSE2: 0x0c070d05 SMC_CYCLE2: 0x000c000d SMC_MODE2: 0x001f0003 NCS_RD: setup: 0 (0 ns), pulse: 12 (36 ns), hold: 0 (0 ns), cycle: 12 (36 ns) NRD: setup: 0 (0 ns), pulse: 7 (21 ns), hold: 5 (15 ns), cycle: 12 (36 ns) NCS_WR: setup: 0 (0 ns), pulse: 13 (39 ns), hold: 0 (0 ns), cycle: 13 (39 ns) NWE: setup: 4 (12 ns), pulse: 5 (15 ns), hold: 4 (12 ns), cycle: 13 (39 ns) Standard read applied TDF optimization enabled TDF cycles: 15 (45 ns) Data Bus Width: 8-bit bus NWAIT Mode: 0 Write operation controlled by NWE signal Read operation controlled by NRD signal => nand torture 0x80 0x80 NAND torture: device 0 offset 0x80 size 0x80 (block size 0x4) Passed: 32, failed: 0 => clk dump 2400 1| |-- mainck 108000 1| | |-- plla_fracck 108000 1| | | |-- plla_divpmcck 108000 1| | | | `-- mck_pres 270008| | | | `-- mck_div Best regards, Mihai Sain
RE: [PATCH v2 6/6] cmd: nand: Add new optional sub-command 'onfi'
Hi Alex, Override the ONFI timing mode at runtime. Signed-off-by: Alexander Dahl --- I used the same board sam9x75-curiosity to test mode 5 😊 I forced in nfc driver the mode 5: + if (conf->timings.sdr.tRC_min < 2) And I ran the nand torture on 16 MiB: => nand onfi 0 => hsmc decode MCK rate: 270 MHz SMC_SETUP2: 0x0007 SMC_PULSE2: 0x22112211 SMC_CYCLE2: 0x00220022 SMC_MODE2: 0x001f0003 NCS_RD: setup: 0 (0 ns), pulse: 34 (102 ns), hold: 0 (0 ns), cycle: 34 (102 ns) NRD: setup: 0 (0 ns), pulse: 17 (51 ns), hold: 17 (51 ns), cycle: 34 (102 ns) NCS_WR: setup: 0 (0 ns), pulse: 34 (102 ns), hold: 0 (0 ns), cycle: 34 (102 ns) NWE: setup: 7 (21 ns), pulse: 17 (51 ns), hold: 10 (30 ns), cycle: 34 (102 ns) Standard read applied TDF optimization enabled TDF cycles: 15 (45 ns) Data Bus Width: 8-bit bus NWAIT Mode: 0 Write operation controlled by NWE signal Read operation controlled by NRD signal => time nand torture 0x80 0x100 NAND torture: device 0 offset 0x80 size 0x100 (block size 0x4) Passed: 64, failed: 0 time: 30.152 seconds => nand onfi 5 => hsmc decode MCK rate: 270 MHz SMC_SETUP2: 0x0001 SMC_PULSE2: 0x0b060804 SMC_CYCLE2: 0x000b0008 SMC_MODE2: 0x001f0003 NCS_RD: setup: 0 (0 ns), pulse: 11 (33 ns), hold: 0 (0 ns), cycle: 11 (33 ns) NRD: setup: 0 (0 ns), pulse: 6 (18 ns), hold: 5 (15 ns), cycle: 11 (33 ns) NCS_WR: setup: 0 (0 ns), pulse: 8 (24 ns), hold: 0 (0 ns), cycle: 8 (24 ns) NWE: setup: 1 (3 ns), pulse: 4 (12 ns), hold: 3 (9 ns), cycle: 8 (24 ns) Standard read applied TDF optimization enabled TDF cycles: 15 (45 ns) Data Bus Width: 8-bit bus NWAIT Mode: 0 Write operation controlled by NWE signal Read operation controlled by NRD signal => time nand torture 0x80 0x100 NAND torture: device 0 offset 0x80 size 0x100 (block size 0x4) Passed: 64, failed: 0 time: 15.891 seconds Best regards, Mihai Sain
Re: [PATCH v2 6/6] cmd: nand: Add new optional sub-command 'onfi'
Hi I think this command can be really useful. On Wed, Mar 20, 2024 at 3:09 PM wrote: > > Hi Alex, > > > > Override the ONFI timing mode at runtime. > > Signed-off-by: Alexander Dahl > --- > > I used the same board sam9x75-curiosity to test mode 5 😊 > > I forced in nfc driver the mode 5: > + if (conf->timings.sdr.tRC_min < 2) > > And I ran the nand torture on 16 MiB: > > => nand onfi 0 > => hsmc decode > > MCK rate: 270 MHz > > SMC_SETUP2: 0x0007 > SMC_PULSE2: 0x22112211 > SMC_CYCLE2: 0x00220022 > SMC_MODE2: 0x001f0003 > NCS_RD: setup: 0 (0 ns), pulse: 34 (102 ns), hold: 0 (0 ns), cycle: 34 (102 > ns) >NRD: setup: 0 (0 ns), pulse: 17 (51 ns), hold: 17 (51 ns), cycle: 34 (102 > ns) > NCS_WR: setup: 0 (0 ns), pulse: 34 (102 ns), hold: 0 (0 ns), cycle: 34 (102 > ns) >NWE: setup: 7 (21 ns), pulse: 17 (51 ns), hold: 10 (30 ns), cycle: 34 (102 > ns) > Standard read applied > TDF optimization enabled > TDF cycles: 15 (45 ns) > Data Bus Width: 8-bit bus > NWAIT Mode: 0 > Write operation controlled by NWE signal > Read operation controlled by NRD signal > > => time nand torture 0x80 0x100 > > NAND torture: device 0 offset 0x80 size 0x100 (block size 0x4) > Passed: 64, failed: 0 > > time: 30.152 seconds > > => nand onfi 5 > => hsmc decode > > MCK rate: 270 MHz > > SMC_SETUP2: 0x0001 > SMC_PULSE2: 0x0b060804 > SMC_CYCLE2: 0x000b0008 > SMC_MODE2: 0x001f0003 > NCS_RD: setup: 0 (0 ns), pulse: 11 (33 ns), hold: 0 (0 ns), cycle: 11 (33 ns) >NRD: setup: 0 (0 ns), pulse: 6 (18 ns), hold: 5 (15 ns), cycle: 11 (33 ns) > NCS_WR: setup: 0 (0 ns), pulse: 8 (24 ns), hold: 0 (0 ns), cycle: 8 (24 ns) >NWE: setup: 1 (3 ns), pulse: 4 (12 ns), hold: 3 (9 ns), cycle: 8 (24 ns) > Standard read applied > TDF optimization enabled > TDF cycles: 15 (45 ns) > Data Bus Width: 8-bit bus > NWAIT Mode: 0 > Write operation controlled by NWE signal > Read operation controlled by NRD signal > > => time nand torture 0x80 0x100 > > NAND torture: device 0 offset 0x80 size 0x100 (block size 0x4) > Passed: 64, failed: 0 > > time: 15.891 seconds > Let try to have more testing on more boards Michael > Best regards, > Mihai Sain -- Michael Nazzareno Trimarchi Co-Founder & Chief Executive Officer M. +39 347 913 2170 mich...@amarulasolutions.com __ Amarula Solutions BV Joop Geesinkweg 125, 1114 AB, Amsterdam, NL T. +31 (0)85 111 9172 i...@amarulasolutions.com www.amarulasolutions.com
RE: [PATCH v2 6/6] cmd: nand: Add new optional sub-command 'onfi'
Hi Michael, --- I think this command can be really useful. Let try to have more testing on more boards - I managed to test the command on sama7g54-curiosity board. I also forced timing mode 5 from controller driver (conf->timings.sdr.tRC_min < 2). => nand onfi 0 => hsmc decode MCK rate: 200 MHz HSMC_SETUP3:0x0004 HSMC_PULSE3:0x140a140a HSMC_CYCLE3:0x00140014 HSMC_TIMINGS3: 0x880805f4 HSMC_MODE3: 0x001f0003 NCS_RD: setup: 0 (0 ns), pulse: 20 (100 ns), hold: 0 (0 ns), cycle: 20 (100 ns) NRD: setup: 0 (0 ns), pulse: 10 (50 ns), hold: 10 (50 ns), cycle: 20 (100 ns) NCS_WR: setup: 0 (0 ns), pulse: 20 (100 ns), hold: 0 (0 ns), cycle: 20 (100 ns) NWE: setup: 4 (20 ns), pulse: 10 (50 ns), hold: 6 (30 ns), cycle: 20 (100 ns) TDF optimization enabled TDF cycles: 15 (75 ns) Data Bus Width: 8-bit bus NWAIT Mode: 0 Write operation controlled by NWE signal Read operation controlled by NRD signal NFSEL (NAND Flash Selection) is set OCMS (Off Chip Memory Scrambling) is disabled TWB (WEN High to REN to Busy): 64 (320 ns) TRR (Ready to REN Low Delay): 64 (320 ns) TAR (ALE to REN Low Delay):5 (25 ns) TADL (ALE to Data Start): 71 (355 ns) TCLR (CLE to REN Low Delay): 4 (20 ns) => time nand torture 0x100 0x100 NAND torture: device 0 offset 0x100 size 0x100 (block size 0x4) Passed: 64, failed: 0 time: 22.638 seconds => nand onfi 5 => hsmc decode MCK rate: 200 MHz HSMC_SETUP3:0x0001 HSMC_PULSE3:0x07040502 HSMC_CYCLE3:0x00070005 HSMC_TIMINGS3: 0x880402f2 HSMC_MODE3: 0x001f0003 NCS_RD: setup: 0 (0 ns), pulse: 7 (35 ns), hold: 0 (0 ns), cycle: 7 (35 ns) NRD: setup: 0 (0 ns), pulse: 4 (20 ns), hold: 3 (15 ns), cycle: 7 (35 ns) NCS_WR: setup: 0 (0 ns), pulse: 5 (25 ns), hold: 0 (0 ns), cycle: 5 (25 ns) NWE: setup: 1 (5 ns), pulse: 2 (10 ns), hold: 2 (10 ns), cycle: 5 (25 ns) TDF optimization enabled TDF cycles: 15 (75 ns) Data Bus Width: 8-bit bus NWAIT Mode: 0 Write operation controlled by NWE signal Read operation controlled by NRD signal NFSEL (NAND Flash Selection) is set OCMS (Off Chip Memory Scrambling) is disabled TWB (WEN High to REN to Busy): 64 (320 ns) TRR (Ready to REN Low Delay): 4 (20 ns) TAR (ALE to REN Low Delay):2 (10 ns) TADL (ALE to Data Start): 71 (355 ns) TCLR (CLE to REN Low Delay): 2 (10 ns) => time nand torture 0x100 0x100 NAND torture: device 0 offset 0x100 size 0x100 (block size 0x4) Passed: 64, failed: 0 time: 11.661 seconds => nand info Device 0: nand0, sector size 256 KiB Manufacturer MACRONIX Model MX30LF4G28AD Device size512 MiB Page size 4096 b OOB size 256 b Erase size 262144 b ecc strength 8 bits ecc step size 512 b subpagesize 4096 b options 0x40004200 bbt options 0x00028000 Best regards, Mihai Sain
Re: [PATCH v2 6/6] cmd: nand: Add new optional sub-command 'onfi'
Hello Mihai, Am Fri, Mar 22, 2024 at 10:02:29AM + schrieb mihai.s...@microchip.com: > Hi Michael, > > --- > > I think this command can be really useful. > Let try to have more testing on more boards > > - > > I managed to test the command on sama7g54-curiosity board. Thanks for that. Nice to see it works on other variants of the SoC family. > I also forced timing mode 5 from controller driver (conf->timings.sdr.tRC_min > < 2). You did a similar thing for the sam9x75. These boards/socs seem to have a newer SMC / HSMC controller than sama5d2 or sam9x60? The driver claims all the (H)SMC incarnations do _not_ support these EDO modes 4 and 5. Maybe someone could have a deeper look at the datasheets of the newer SoCs and propose a patch to support those newer controllers in the atmel nand-controller driver? I guess the problem is the same in Linux, right? Greets Alex > > => nand onfi 0 > => hsmc decode > > MCK rate: 200 MHz > > HSMC_SETUP3:0x0004 > HSMC_PULSE3:0x140a140a > HSMC_CYCLE3:0x00140014 > HSMC_TIMINGS3: 0x880805f4 > HSMC_MODE3: 0x001f0003 > NCS_RD: setup: 0 (0 ns), pulse: 20 (100 ns), hold: 0 (0 ns), cycle: 20 (100 > ns) >NRD: setup: 0 (0 ns), pulse: 10 (50 ns), hold: 10 (50 ns), cycle: 20 (100 > ns) > NCS_WR: setup: 0 (0 ns), pulse: 20 (100 ns), hold: 0 (0 ns), cycle: 20 (100 > ns) >NWE: setup: 4 (20 ns), pulse: 10 (50 ns), hold: 6 (30 ns), cycle: 20 (100 > ns) > TDF optimization enabled > TDF cycles: 15 (75 ns) > Data Bus Width: 8-bit bus > NWAIT Mode: 0 > Write operation controlled by NWE signal > Read operation controlled by NRD signal > NFSEL (NAND Flash Selection) is set > OCMS (Off Chip Memory Scrambling) is disabled > TWB (WEN High to REN to Busy): 64 (320 ns) > TRR (Ready to REN Low Delay): 64 (320 ns) > TAR (ALE to REN Low Delay):5 (25 ns) > TADL (ALE to Data Start): 71 (355 ns) > TCLR (CLE to REN Low Delay): 4 (20 ns) > > => time nand torture 0x100 0x100 > > NAND torture: device 0 offset 0x100 size 0x100 (block size 0x4) > Passed: 64, failed: 0 > > time: 22.638 seconds > > => nand onfi 5 > => hsmc decode > > MCK rate: 200 MHz > > HSMC_SETUP3:0x0001 > HSMC_PULSE3:0x07040502 > HSMC_CYCLE3:0x00070005 > HSMC_TIMINGS3: 0x880402f2 > HSMC_MODE3: 0x001f0003 > NCS_RD: setup: 0 (0 ns), pulse: 7 (35 ns), hold: 0 (0 ns), cycle: 7 (35 ns) >NRD: setup: 0 (0 ns), pulse: 4 (20 ns), hold: 3 (15 ns), cycle: 7 (35 ns) > NCS_WR: setup: 0 (0 ns), pulse: 5 (25 ns), hold: 0 (0 ns), cycle: 5 (25 ns) >NWE: setup: 1 (5 ns), pulse: 2 (10 ns), hold: 2 (10 ns), cycle: 5 (25 ns) > TDF optimization enabled > TDF cycles: 15 (75 ns) > Data Bus Width: 8-bit bus > NWAIT Mode: 0 > Write operation controlled by NWE signal > Read operation controlled by NRD signal > NFSEL (NAND Flash Selection) is set > OCMS (Off Chip Memory Scrambling) is disabled > TWB (WEN High to REN to Busy): 64 (320 ns) > TRR (Ready to REN Low Delay): 4 (20 ns) > TAR (ALE to REN Low Delay):2 (10 ns) > TADL (ALE to Data Start): 71 (355 ns) > TCLR (CLE to REN Low Delay): 2 (10 ns) > > => time nand torture 0x100 0x100 > > NAND torture: device 0 offset 0x100 size 0x100 (block size 0x4) > Passed: 64, failed: 0 > > time: 11.661 seconds > > => nand info > > Device 0: nand0, sector size 256 KiB > Manufacturer MACRONIX > Model MX30LF4G28AD > Device size512 MiB > Page size 4096 b > OOB size 256 b > Erase size 262144 b > ecc strength 8 bits > ecc step size 512 b > subpagesize 4096 b > options 0x40004200 > bbt options 0x00028000 > > Best regards, > Mihai Sain
Re: [PATCH v2 6/6] cmd: nand: Add new optional sub-command 'onfi'
HI On Fri, Mar 22, 2024 at 12:46 PM Alexander Dahl wrote: > > Hello Mihai, > > Am Fri, Mar 22, 2024 at 10:02:29AM + schrieb mihai.s...@microchip.com: > > Hi Michael, > > > > --- > > > > I think this command can be really useful. > > Let try to have more testing on more boards > > > > - > > > > I managed to test the command on sama7g54-curiosity board. > > Thanks for that. Nice to see it works on other variants of the SoC > family. > > > I also forced timing mode 5 from controller driver > > (conf->timings.sdr.tRC_min < 2). > > You did a similar thing for the sam9x75. These boards/socs seem to > have a newer SMC / HSMC controller than sama5d2 or sam9x60? The > driver claims all the (H)SMC incarnations do _not_ support these EDO > modes 4 and 5. Maybe someone could have a deeper look at the > datasheets of the newer SoCs and propose a patch to support those > newer controllers in the atmel nand-controller driver? I guess the > problem is the same in Linux, right? > > Greets > Alex > > > > > => nand onfi 0 > > => hsmc decode > > > > MCK rate: 200 MHz > > > > HSMC_SETUP3:0x0004 > > HSMC_PULSE3:0x140a140a > > HSMC_CYCLE3:0x00140014 > > HSMC_TIMINGS3: 0x880805f4 > > HSMC_MODE3: 0x001f0003 > > NCS_RD: setup: 0 (0 ns), pulse: 20 (100 ns), hold: 0 (0 ns), cycle: 20 (100 > > ns) > >NRD: setup: 0 (0 ns), pulse: 10 (50 ns), hold: 10 (50 ns), cycle: 20 > > (100 ns) > > NCS_WR: setup: 0 (0 ns), pulse: 20 (100 ns), hold: 0 (0 ns), cycle: 20 (100 > > ns) > >NWE: setup: 4 (20 ns), pulse: 10 (50 ns), hold: 6 (30 ns), cycle: 20 > > (100 ns) > > TDF optimization enabled > > TDF cycles: 15 (75 ns) > > Data Bus Width: 8-bit bus > > NWAIT Mode: 0 > > Write operation controlled by NWE signal > > Read operation controlled by NRD signal > > NFSEL (NAND Flash Selection) is set > > OCMS (Off Chip Memory Scrambling) is disabled > > TWB (WEN High to REN to Busy): 64 (320 ns) > > TRR (Ready to REN Low Delay): 64 (320 ns) > > TAR (ALE to REN Low Delay):5 (25 ns) > > TADL (ALE to Data Start): 71 (355 ns) > > TCLR (CLE to REN Low Delay): 4 (20 ns) > > > > => time nand torture 0x100 0x100 > > > > NAND torture: device 0 offset 0x100 size 0x100 (block size 0x4) > > Passed: 64, failed: 0 > > > > time: 22.638 seconds > > > > => nand onfi 5 > > => hsmc decode > > > > MCK rate: 200 MHz > > > > HSMC_SETUP3:0x0001 > > HSMC_PULSE3:0x07040502 > > HSMC_CYCLE3:0x00070005 > > HSMC_TIMINGS3: 0x880402f2 > > HSMC_MODE3: 0x001f0003 > > NCS_RD: setup: 0 (0 ns), pulse: 7 (35 ns), hold: 0 (0 ns), cycle: 7 (35 ns) > >NRD: setup: 0 (0 ns), pulse: 4 (20 ns), hold: 3 (15 ns), cycle: 7 (35 ns) > > NCS_WR: setup: 0 (0 ns), pulse: 5 (25 ns), hold: 0 (0 ns), cycle: 5 (25 ns) > >NWE: setup: 1 (5 ns), pulse: 2 (10 ns), hold: 2 (10 ns), cycle: 5 (25 ns) > > TDF optimization enabled > > TDF cycles: 15 (75 ns) > > Data Bus Width: 8-bit bus > > NWAIT Mode: 0 > > Write operation controlled by NWE signal > > Read operation controlled by NRD signal > > NFSEL (NAND Flash Selection) is set > > OCMS (Off Chip Memory Scrambling) is disabled > > TWB (WEN High to REN to Busy): 64 (320 ns) > > TRR (Ready to REN Low Delay): 4 (20 ns) > > TAR (ALE to REN Low Delay):2 (10 ns) > > TADL (ALE to Data Start): 71 (355 ns) > > TCLR (CLE to REN Low Delay): 2 (10 ns) > > > > => time nand torture 0x100 0x100 > > > > NAND torture: device 0 offset 0x100 size 0x100 (block size 0x4) > > Passed: 64, failed: 0 > > > > time: 11.661 seconds > > > > => nand info > > > > Device 0: nand0, sector size 256 KiB > > Manufacturer MACRONIX > > Model MX30LF4G28AD > > Device size512 MiB > > Page size 4096 b > > OOB size 256 b > > Erase size 262144 b > > ecc strength 8 bits > > ecc step size 512 b > > subpagesize 4096 b > > options 0x40004200 > > bbt options 0x00028000 > > > > Best regards, > > Mihai Sain I'm in favor to have it even cover by one soc family. I would like to confirm on imx6 and imx8. If you are not in a rush. Let's us test too Michael -- Michael Nazzareno Trimarchi Co-Founder & Chief Executive Officer M. +39 347 913 2170 mich...@amarulasolutions.com __ Amarula Solutions BV Joop Geesinkweg 125, 1114 AB, Amsterdam, NL T. +31 (0)85 111 9172 i...@amarulasolutions.com www.amarulasolutions.com
Re: [PATCH v2 6/6] cmd: nand: Add new optional sub-command 'onfi'
Hello Michael, Am Fri, Mar 22, 2024 at 12:54:27PM +0100 schrieb Michael Nazzareno Trimarchi: > HI > > On Fri, Mar 22, 2024 at 12:46 PM Alexander Dahl wrote: > > > > Hello Mihai, > > > > Am Fri, Mar 22, 2024 at 10:02:29AM + schrieb mihai.s...@microchip.com: > > > Hi Michael, > > > > > > --- > > > > > > I think this command can be really useful. > > > Let try to have more testing on more boards > > > > > > - > > > > > > I managed to test the command on sama7g54-curiosity board. > > > > Thanks for that. Nice to see it works on other variants of the SoC > > family. > > > > > I also forced timing mode 5 from controller driver > > > (conf->timings.sdr.tRC_min < 2). > > > > You did a similar thing for the sam9x75. These boards/socs seem to > > have a newer SMC / HSMC controller than sama5d2 or sam9x60? The > > driver claims all the (H)SMC incarnations do _not_ support these EDO > > modes 4 and 5. Maybe someone could have a deeper look at the > > datasheets of the newer SoCs and propose a patch to support those > > newer controllers in the atmel nand-controller driver? I guess the > > problem is the same in Linux, right? > > > > Greets > > Alex > > > > > > > > => nand onfi 0 > > > => hsmc decode > > > > > > MCK rate: 200 MHz > > > > > > HSMC_SETUP3:0x0004 > > > HSMC_PULSE3:0x140a140a > > > HSMC_CYCLE3:0x00140014 > > > HSMC_TIMINGS3: 0x880805f4 > > > HSMC_MODE3: 0x001f0003 > > > NCS_RD: setup: 0 (0 ns), pulse: 20 (100 ns), hold: 0 (0 ns), cycle: 20 > > > (100 ns) > > >NRD: setup: 0 (0 ns), pulse: 10 (50 ns), hold: 10 (50 ns), cycle: 20 > > > (100 ns) > > > NCS_WR: setup: 0 (0 ns), pulse: 20 (100 ns), hold: 0 (0 ns), cycle: 20 > > > (100 ns) > > >NWE: setup: 4 (20 ns), pulse: 10 (50 ns), hold: 6 (30 ns), cycle: 20 > > > (100 ns) > > > TDF optimization enabled > > > TDF cycles: 15 (75 ns) > > > Data Bus Width: 8-bit bus > > > NWAIT Mode: 0 > > > Write operation controlled by NWE signal > > > Read operation controlled by NRD signal > > > NFSEL (NAND Flash Selection) is set > > > OCMS (Off Chip Memory Scrambling) is disabled > > > TWB (WEN High to REN to Busy): 64 (320 ns) > > > TRR (Ready to REN Low Delay): 64 (320 ns) > > > TAR (ALE to REN Low Delay):5 (25 ns) > > > TADL (ALE to Data Start): 71 (355 ns) > > > TCLR (CLE to REN Low Delay): 4 (20 ns) > > > > > > => time nand torture 0x100 0x100 > > > > > > NAND torture: device 0 offset 0x100 size 0x100 (block size > > > 0x4) > > > Passed: 64, failed: 0 > > > > > > time: 22.638 seconds > > > > > > => nand onfi 5 > > > => hsmc decode > > > > > > MCK rate: 200 MHz > > > > > > HSMC_SETUP3:0x0001 > > > HSMC_PULSE3:0x07040502 > > > HSMC_CYCLE3:0x00070005 > > > HSMC_TIMINGS3: 0x880402f2 > > > HSMC_MODE3: 0x001f0003 > > > NCS_RD: setup: 0 (0 ns), pulse: 7 (35 ns), hold: 0 (0 ns), cycle: 7 (35 > > > ns) > > >NRD: setup: 0 (0 ns), pulse: 4 (20 ns), hold: 3 (15 ns), cycle: 7 (35 > > > ns) > > > NCS_WR: setup: 0 (0 ns), pulse: 5 (25 ns), hold: 0 (0 ns), cycle: 5 (25 > > > ns) > > >NWE: setup: 1 (5 ns), pulse: 2 (10 ns), hold: 2 (10 ns), cycle: 5 (25 > > > ns) > > > TDF optimization enabled > > > TDF cycles: 15 (75 ns) > > > Data Bus Width: 8-bit bus > > > NWAIT Mode: 0 > > > Write operation controlled by NWE signal > > > Read operation controlled by NRD signal > > > NFSEL (NAND Flash Selection) is set > > > OCMS (Off Chip Memory Scrambling) is disabled > > > TWB (WEN High to REN to Busy): 64 (320 ns) > > > TRR (Ready to REN Low Delay): 4 (20 ns) > > > TAR (ALE to REN Low Delay):2 (10 ns) > > > TADL (ALE to Data Start): 71 (355 ns) > > > TCLR (CLE to REN Low Delay): 2 (10 ns) > > > > > > => time nand torture 0x100 0x100 > > > > > > NAND torture: device 0 offset 0x100 size 0x100 (block size > > > 0x4) > > > Passed: 64, failed: 0 > > > > > > time: 11.661 seconds > > > > > > => nand info > > > > > > Device 0: nand0, sector size 256 KiB > > > Manufacturer MACRONIX > > > Model MX30LF4G28AD > > > Device size512 MiB > > > Page size 4096 b > > > OOB size 256 b > > > Erase size 262144 b > > > ecc strength 8 bits > > > ecc step size 512 b > > > subpagesize 4096 b > > > options 0x40004200 > > > bbt options 0x00028000 > > > > > > Best regards, > > > Mihai Sain > > I'm in favor to have it even cover by one soc family. I would like to > confirm on imx6 and imx8. If you are not in a rush. > Let's us test too Agreed. This is a generic nand command, so it would of course be reasonable to test it on multiple nand controllers. I'm afraid I currently have only at91 boards on my desk for which I have a recent U-Boot _and_ a NAND chip soldered. So take your time for this patch. If you don't mind I would be happy if you could merge the four trivial patches w
Re: [PATCH v2 6/6] cmd: nand: Add new optional sub-command 'onfi'
HI On Fri, Mar 22, 2024 at 1:02 PM Alexander Dahl wrote: > > Hello Michael, > > Am Fri, Mar 22, 2024 at 12:54:27PM +0100 schrieb Michael Nazzareno Trimarchi: > > HI > > > > On Fri, Mar 22, 2024 at 12:46 PM Alexander Dahl wrote: > > > > > > Hello Mihai, > > > > > > Am Fri, Mar 22, 2024 at 10:02:29AM + schrieb mihai.s...@microchip.com: > > > > Hi Michael, > > > > > > > > --- > > > > > > > > I think this command can be really useful. > > > > Let try to have more testing on more boards > > > > > > > > - > > > > > > > > I managed to test the command on sama7g54-curiosity board. > > > > > > Thanks for that. Nice to see it works on other variants of the SoC > > > family. > > > > > > > I also forced timing mode 5 from controller driver > > > > (conf->timings.sdr.tRC_min < 2). > > > > > > You did a similar thing for the sam9x75. These boards/socs seem to > > > have a newer SMC / HSMC controller than sama5d2 or sam9x60? The > > > driver claims all the (H)SMC incarnations do _not_ support these EDO > > > modes 4 and 5. Maybe someone could have a deeper look at the > > > datasheets of the newer SoCs and propose a patch to support those > > > newer controllers in the atmel nand-controller driver? I guess the > > > problem is the same in Linux, right? > > > > > > Greets > > > Alex > > > > > > > > > > > => nand onfi 0 > > > > => hsmc decode > > > > > > > > MCK rate: 200 MHz > > > > > > > > HSMC_SETUP3:0x0004 > > > > HSMC_PULSE3:0x140a140a > > > > HSMC_CYCLE3:0x00140014 > > > > HSMC_TIMINGS3: 0x880805f4 > > > > HSMC_MODE3: 0x001f0003 > > > > NCS_RD: setup: 0 (0 ns), pulse: 20 (100 ns), hold: 0 (0 ns), cycle: 20 > > > > (100 ns) > > > >NRD: setup: 0 (0 ns), pulse: 10 (50 ns), hold: 10 (50 ns), cycle: 20 > > > > (100 ns) > > > > NCS_WR: setup: 0 (0 ns), pulse: 20 (100 ns), hold: 0 (0 ns), cycle: 20 > > > > (100 ns) > > > >NWE: setup: 4 (20 ns), pulse: 10 (50 ns), hold: 6 (30 ns), cycle: 20 > > > > (100 ns) > > > > TDF optimization enabled > > > > TDF cycles: 15 (75 ns) > > > > Data Bus Width: 8-bit bus > > > > NWAIT Mode: 0 > > > > Write operation controlled by NWE signal > > > > Read operation controlled by NRD signal > > > > NFSEL (NAND Flash Selection) is set > > > > OCMS (Off Chip Memory Scrambling) is disabled > > > > TWB (WEN High to REN to Busy): 64 (320 ns) > > > > TRR (Ready to REN Low Delay): 64 (320 ns) > > > > TAR (ALE to REN Low Delay):5 (25 ns) > > > > TADL (ALE to Data Start): 71 (355 ns) > > > > TCLR (CLE to REN Low Delay): 4 (20 ns) > > > > > > > > => time nand torture 0x100 0x100 > > > > > > > > NAND torture: device 0 offset 0x100 size 0x100 (block size > > > > 0x4) > > > > Passed: 64, failed: 0 > > > > > > > > time: 22.638 seconds > > > > > > > > => nand onfi 5 > > > > => hsmc decode > > > > > > > > MCK rate: 200 MHz > > > > > > > > HSMC_SETUP3:0x0001 > > > > HSMC_PULSE3:0x07040502 > > > > HSMC_CYCLE3:0x00070005 > > > > HSMC_TIMINGS3: 0x880402f2 > > > > HSMC_MODE3: 0x001f0003 > > > > NCS_RD: setup: 0 (0 ns), pulse: 7 (35 ns), hold: 0 (0 ns), cycle: 7 (35 > > > > ns) > > > >NRD: setup: 0 (0 ns), pulse: 4 (20 ns), hold: 3 (15 ns), cycle: 7 > > > > (35 ns) > > > > NCS_WR: setup: 0 (0 ns), pulse: 5 (25 ns), hold: 0 (0 ns), cycle: 5 (25 > > > > ns) > > > >NWE: setup: 1 (5 ns), pulse: 2 (10 ns), hold: 2 (10 ns), cycle: 5 > > > > (25 ns) > > > > TDF optimization enabled > > > > TDF cycles: 15 (75 ns) > > > > Data Bus Width: 8-bit bus > > > > NWAIT Mode: 0 > > > > Write operation controlled by NWE signal > > > > Read operation controlled by NRD signal > > > > NFSEL (NAND Flash Selection) is set > > > > OCMS (Off Chip Memory Scrambling) is disabled > > > > TWB (WEN High to REN to Busy): 64 (320 ns) > > > > TRR (Ready to REN Low Delay): 4 (20 ns) > > > > TAR (ALE to REN Low Delay):2 (10 ns) > > > > TADL (ALE to Data Start): 71 (355 ns) > > > > TCLR (CLE to REN Low Delay): 2 (10 ns) > > > > > > > > => time nand torture 0x100 0x100 > > > > > > > > NAND torture: device 0 offset 0x100 size 0x100 (block size > > > > 0x4) > > > > Passed: 64, failed: 0 > > > > > > > > time: 11.661 seconds > > > > > > > > => nand info > > > > > > > > Device 0: nand0, sector size 256 KiB > > > > Manufacturer MACRONIX > > > > Model MX30LF4G28AD > > > > Device size512 MiB > > > > Page size 4096 b > > > > OOB size 256 b > > > > Erase size 262144 b > > > > ecc strength 8 bits > > > > ecc step size 512 b > > > > subpagesize 4096 b > > > > options 0x40004200 > > > > bbt options 0x00028000 > > > > > > > > Best regards, > > > > Mihai Sain > > > > I'm in favor to have it even cover by one soc family. I would like to > > confirm on imx6 and imx8. If you are not in a rush. > > Let's us test too > > Agreed. Th
