Re: [Patch v2 1/7] spi: Transform the FSL QuadSPI driver to use the SPI MEM API
On 16.12.19 12:49, Kuldeep Singh wrote: To support the SPI MEM API, instead of modifying the existing U-Boot driver, this patch adds a port of the existing Linux driver. This also has the advantage that porting changes and fixes from Linux will be easier. Porting of driver left most of the functions unchanged while few of the changes are: -Remove lock(mutexes) and irq handler as uboot is a single core execution. -Remove clock support as the changing spi speed is not supported in uboot and nor in linux. Currently tested on LS1088ARDB, LS1012ARDB, LS1046ARDB, LS1046AFRWY, LS1043AQDS, LS1021ATWR, LS2080ARDB Signed-off-by: Frieder Schrempf Signed-off-by: Ashish Kumar Signed-off-by: Kuldeep Singh Reviewed-by: Stefan Roese Tested-by: Stefan Roese Tested on the NXP i.MX6ULL EVK. Thanks, Stefan --- drivers/spi/fsl_qspi.c | 1562 +++- drivers/spi/fsl_qspi.h | 145 2 files changed, 593 insertions(+), 1114 deletions(-) delete mode 100644 drivers/spi/fsl_qspi.h diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 8e2a09df36..96178c06bc 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -1,1142 +1,766 @@ // SPDX-License-Identifier: GPL-2.0+ + /* - * Copyright 2013-2015 Freescale Semiconductor, Inc. + * Freescale QuadSPI driver. + * + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * Copyright (C) 2018 Bootlin + * Copyright (C) 2018 exceet electronics GmbH + * Copyright (C) 2018 Kontron Electronics GmbH + * Copyright (C) 2019-2020 NXP * - * Freescale Quad Serial Peripheral Interface (QSPI) driver + * Based on the original fsl-quadspi.c spi-nor driver. + * Transition to spi-mem in spi-fsl-qspi.c */ #include -#include -#include #include -#include -#include #include -#include -#include -#include -#include "fsl_qspi.h" +#include +#include +#include +#include DECLARE_GLOBAL_DATA_PTR; -#define OFFSET_BITS_MASK GENMASK(23, 0) - -#define FLASH_STATUS_WEL 0x02 - -/* SEQID */ -#define SEQID_WREN 1 -#define SEQID_FAST_READ2 -#define SEQID_RDSR 3 -#define SEQID_SE 4 -#define SEQID_CHIP_ERASE 5 -#define SEQID_PP 6 -#define SEQID_RDID 7 -#define SEQID_BE_4K8 -#ifdef CONFIG_SPI_FLASH_BAR -#define SEQID_BRRD 9 -#define SEQID_BRWR 10 -#define SEQID_RDEAR11 -#define SEQID_WREAR12 -#endif -#define SEQID_WRAR 13 -#define SEQID_RDAR 14 - -/* QSPI CMD */ -#define QSPI_CMD_PP0x02/* Page program (up to 256 bytes) */ -#define QSPI_CMD_RDSR 0x05/* Read status register */ -#define QSPI_CMD_WREN 0x06/* Write enable */ -#define QSPI_CMD_FAST_READ 0x0b/* Read data bytes (high frequency) */ -#define QSPI_CMD_BE_4K 0x20/* 4K erase */ -#define QSPI_CMD_CHIP_ERASE0xc7/* Erase whole flash chip */ -#define QSPI_CMD_SE0xd8/* Sector erase (usually 64KiB) */ -#define QSPI_CMD_RDID 0x9f/* Read JEDEC ID */ - -/* Used for Micron, winbond and Macronix flashes */ -#defineQSPI_CMD_WREAR 0xc5/* EAR register write */ -#defineQSPI_CMD_RDEAR 0xc8/* EAR reigster read */ - -/* Used for Spansion flashes only. */ -#defineQSPI_CMD_BRRD 0x16/* Bank register read */ -#defineQSPI_CMD_BRWR 0x17/* Bank register write */ - -/* Used for Spansion S25FS-S family flash only. */ -#define QSPI_CMD_RDAR 0x65/* Read any device register */ -#define QSPI_CMD_WRAR 0x71/* Write any device register */ - -/* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */ -#define QSPI_CMD_FAST_READ_4B 0x0c/* Read data bytes (high frequency) */ -#define QSPI_CMD_PP_4B 0x12/* Page program (up to 256 bytes) */ -#define QSPI_CMD_SE_4B 0xdc/* Sector erase (usually 64KiB) */ - -/* fsl_qspi_platdata flags */ -#define QSPI_FLAG_REGMAP_ENDIAN_BIGBIT(0) - -/* default SCK frequency, unit: HZ */ -#define FSL_QSPI_DEFAULT_SCK_FREQ 5000 - -/* QSPI max chipselect signals number */ -#define FSL_QSPI_MAX_CHIPSELECT_NUM 4 - -/* Controller needs driver to swap endian */ +/* + * The driver only uses one single LUT entry, that is updated on + * each call of exec_op(). Index 0 is preset at boot with a basic + * read operation, so let's use the last entry (15). + */ +#defineSEQID_LUT 15 + +/* Registers used by the driver */ +#define QUADSPI_MCR0x00 +#define QUADSPI_MCR_RESERVED_MASK GENMASK(19, 16) +#define QUADSPI_MCR_MDIS_MASK BIT(14) +#define QUADSPI_MCR_CLR_TXF_MASK BIT(11) +#define QUADSPI_MCR_CLR_RXF_MASK BIT(10) +#define QUADSPI_MCR_DDR_EN_MASKBIT(7) +#define QUADSPI_MCR_END_CFG_MASK GENMASK(3, 2) +#define QUADSPI_MCR_SWRSTHD_MASK BI
RE: [Patch v2 1/7] spi: Transform the FSL QuadSPI driver to use the SPI MEM API
Hi Priyanka, > -Original Message- > From: Priyanka Jain > Sent: Tuesday, December 17, 2019 10:38 AM > To: Kuldeep Singh ; u-boot@lists.denx.de > Cc: ja...@amarulasolutions.com; s...@denx.de; Ashish Kumar > ; frieder.schre...@kontron.de; Kuldeep Singh > ; Ashish Kumar > Subject: RE: [Patch v2 1/7] spi: Transform the FSL QuadSPI driver to use the > SPI > MEM API > > > > >-Original Message- > >From: Kuldeep Singh > >Sent: Monday, December 16, 2019 5:19 PM > >To: u-boot@lists.denx.de > >Cc: ja...@amarulasolutions.com; Priyanka Jain ; > >s...@denx.de; Ashish Kumar ; > >frieder.schre...@kontron.de; Kuldeep Singh ; > >Ashish Kumar > >Subject: [Patch v2 1/7] spi: Transform the FSL QuadSPI driver to use > >the SPI MEM API > > > >To support the SPI MEM API, instead of modifying the existing U-Boot > >driver, this patch adds a port of the existing Linux driver. > >This also has the advantage that porting changes and fixes from Linux > >will be easier. > >Porting of driver left most of the functions unchanged while few of the > >changes are: > >-Remove lock(mutexes) and irq handler as uboot is a single core execution. > >-Remove clock support as the changing spi speed is not supported in > >uboot and nor in linux. > > > >Currently tested on LS1088ARDB, LS1012ARDB, LS1046ARDB, LS1046AFRWY, > >LS1043AQDS, LS1021ATWR, LS2080ARDB > > > >Signed-off-by: Frieder Schrempf > >Signed-off-by: Ashish Kumar > >Signed-off-by: Kuldeep Singh > >--- > > drivers/spi/fsl_qspi.c | 1562 +++- > > drivers/spi/fsl_qspi.h | 145 > > 2 files changed, 593 insertions(+), 1114 deletions(-) delete mode > >100644 drivers/spi/fsl_qspi.h > > > >diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index > >8e2a09df36..96178c06bc 100644 > >--- a/drivers/spi/fsl_qspi.c > >+++ b/drivers/spi/fsl_qspi.c > >@@ -1,1142 +1,766 @@ > > // SPDX-License-Identifier: GPL-2.0+ > >+ > > /* > >- * Copyright 2013-2015 Freescale Semiconductor, Inc. > >+ * Freescale QuadSPI driver. > >+ * > >+ * Copyright (C) 2013 Freescale Semiconductor, Inc. > >+ * Copyright (C) 2018 Bootlin > >+ * Copyright (C) 2018 exceet electronics GmbH > >+ * Copyright (C) 2018 Kontron Electronics GmbH > >+ * Copyright (C) 2019-2020 NXP > Please check copyright format > It seems the changes have been brought from Linux driver. > If yes, it would be good to mention that in File header Ok. I will mention that information on top. > > * > >- * Freescale Quad Serial Peripheral Interface (QSPI) driver > >+ * Based on the original fsl-quadspi.c spi-nor driver. > >+ * Transition to spi-mem in spi-fsl-qspi.c > > */ > > > > #include > >-#include > >-#include > > #include > >-#include > >-#include > > #include > >-#include > >-#include > >-#include > >-#include "fsl_qspi.h" > >+#include > >+#include > >+#include > >+#include > > > > DECLARE_GLOBAL_DATA_PTR; > > > >-#define OFFSET_BITS_MASKGENMASK(23, 0) > >- > >-#define FLASH_STATUS_WEL0x02 > >- > >-/* SEQID */ > >-#define SEQID_WREN 1 > >-#define SEQID_FAST_READ 2 > >-#define SEQID_RDSR 3 > >-#define SEQID_SE4 > >-#define SEQID_CHIP_ERASE5 > >-#define SEQID_PP6 > >-#define SEQID_RDID 7 > >-#define SEQID_BE_4K 8 > >-#ifdef CONFIG_SPI_FLASH_BAR > >-#define SEQID_BRRD 9 > >-#define SEQID_BRWR 10 > >-#define SEQID_RDEAR 11 > >-#define SEQID_WREAR 12 > >-#endif > >-#define SEQID_WRAR 13 > >-#define SEQID_RDAR 14 > >- > >-/* QSPI CMD */ > >-#define QSPI_CMD_PP 0x02/* Page program (up to 256 > bytes) */ > >-#define QSPI_CMD_RDSR 0x05/* Read status register */ > >-#define QSPI_CMD_WREN 0x06/* Write enable */ > >-#define QSPI_CMD_FAST_READ 0x0b/* Read data bytes (high > >frequency) */ > >-#define QSPI_CMD_BE_4K 0x20/* 4K erase */ > >-#define QSPI_CMD_CHIP_ERASE 0xc7/* Erase whole flash chip */ > >-#define QSPI_CMD_SE 0xd8/* Sector erase (usually 64KiB) > */ > >-#define QSPI_CMD_RDID 0x9f/* Read JEDEC ID */ > >- > >-/* Used for Micron, winbond and Macronix flashes */ > >-#define QSPI_CMD_WREAR 0xc5/* EAR register
RE: [Patch v2 1/7] spi: Transform the FSL QuadSPI driver to use the SPI MEM API
>-Original Message- >From: Kuldeep Singh >Sent: Monday, December 16, 2019 5:19 PM >To: u-boot@lists.denx.de >Cc: ja...@amarulasolutions.com; Priyanka Jain ; >s...@denx.de; Ashish Kumar ; >frieder.schre...@kontron.de; Kuldeep Singh ; Ashish >Kumar >Subject: [Patch v2 1/7] spi: Transform the FSL QuadSPI driver to use the SPI >MEM >API > >To support the SPI MEM API, instead of modifying the existing U-Boot >driver, this patch adds a port of the existing Linux driver. >This also has the advantage that porting changes and fixes from Linux >will be easier. >Porting of driver left most of the functions unchanged while few of the >changes are: >-Remove lock(mutexes) and irq handler as uboot is a single core execution. >-Remove clock support as the changing spi speed is not supported in >uboot and nor in linux. > >Currently tested on LS1088ARDB, LS1012ARDB, LS1046ARDB, LS1046AFRWY, >LS1043AQDS, LS1021ATWR, LS2080ARDB > >Signed-off-by: Frieder Schrempf >Signed-off-by: Ashish Kumar >Signed-off-by: Kuldeep Singh >--- > drivers/spi/fsl_qspi.c | 1562 +++- > drivers/spi/fsl_qspi.h | 145 > 2 files changed, 593 insertions(+), 1114 deletions(-) > delete mode 100644 drivers/spi/fsl_qspi.h > >diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c >index 8e2a09df36..96178c06bc 100644 >--- a/drivers/spi/fsl_qspi.c >+++ b/drivers/spi/fsl_qspi.c >@@ -1,1142 +1,766 @@ > // SPDX-License-Identifier: GPL-2.0+ >+ > /* >- * Copyright 2013-2015 Freescale Semiconductor, Inc. >+ * Freescale QuadSPI driver. >+ * >+ * Copyright (C) 2013 Freescale Semiconductor, Inc. >+ * Copyright (C) 2018 Bootlin >+ * Copyright (C) 2018 exceet electronics GmbH >+ * Copyright (C) 2018 Kontron Electronics GmbH >+ * Copyright (C) 2019-2020 NXP Please check copyright format It seems the changes have been brought from Linux driver. If yes, it would be good to mention that in File header > * >- * Freescale Quad Serial Peripheral Interface (QSPI) driver >+ * Based on the original fsl-quadspi.c spi-nor driver. >+ * Transition to spi-mem in spi-fsl-qspi.c > */ > > #include >-#include >-#include > #include >-#include >-#include > #include >-#include >-#include >-#include >-#include "fsl_qspi.h" >+#include >+#include >+#include >+#include > > DECLARE_GLOBAL_DATA_PTR; > >-#define OFFSET_BITS_MASK GENMASK(23, 0) >- >-#define FLASH_STATUS_WEL 0x02 >- >-/* SEQID */ >-#define SEQID_WREN1 >-#define SEQID_FAST_READ 2 >-#define SEQID_RDSR3 >-#define SEQID_SE 4 >-#define SEQID_CHIP_ERASE 5 >-#define SEQID_PP 6 >-#define SEQID_RDID7 >-#define SEQID_BE_4K 8 >-#ifdef CONFIG_SPI_FLASH_BAR >-#define SEQID_BRRD9 >-#define SEQID_BRWR10 >-#define SEQID_RDEAR 11 >-#define SEQID_WREAR 12 >-#endif >-#define SEQID_WRAR13 >-#define SEQID_RDAR14 >- >-/* QSPI CMD */ >-#define QSPI_CMD_PP 0x02/* Page program (up to 256 bytes) */ >-#define QSPI_CMD_RDSR 0x05/* Read status register */ >-#define QSPI_CMD_WREN 0x06/* Write enable */ >-#define QSPI_CMD_FAST_READ0x0b/* Read data bytes (high >frequency) */ >-#define QSPI_CMD_BE_4K0x20/* 4K erase */ >-#define QSPI_CMD_CHIP_ERASE 0xc7/* Erase whole flash chip */ >-#define QSPI_CMD_SE 0xd8/* Sector erase (usually 64KiB) */ >-#define QSPI_CMD_RDID 0x9f/* Read JEDEC ID */ >- >-/* Used for Micron, winbond and Macronix flashes */ >-#define QSPI_CMD_WREAR 0xc5/* EAR register write */ >-#define QSPI_CMD_RDEAR 0xc8/* EAR reigster read */ >- >-/* Used for Spansion flashes only. */ >-#define QSPI_CMD_BRRD 0x16/* Bank register read >*/ >-#define QSPI_CMD_BRWR 0x17/* Bank register write >*/ >- >-/* Used for Spansion S25FS-S family flash only. */ >-#define QSPI_CMD_RDAR 0x65/* Read any device register */ >-#define QSPI_CMD_WRAR 0x71/* Write any device register */ >- >-/* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */ >-#define QSPI_CMD_FAST_READ_4B 0x0c/* Read data bytes (high >frequency) */ >-#define QSPI_CMD_PP_4B0x12/* Page program (up to 256 >bytes) */ >-#define QSPI_CMD_SE_4B0xdc/* Sector erase (usually 64KiB) >*/ >- >-/* fsl_qspi_platdata flags */ >-#define QSPI_FLAG_REGMAP_ENDIAN_BIG BIT(0) >- >-/* default SCK frequency, unit: HZ */ >-#define FSL_QSPI_DEFAULT_SCK_FREQ 5000 >- >-/* QSPI max chipselect signals number */ >-#define FSL_QSPI_MAX_CHIPSELECT_NUM 4 >- >-/* Controller needs driver to swap endian */ >+/* >+ * The driver only uses one single LUT entry, that is updated on >+ * each call of exec_op(). Index 0 is preset at boot with a basic >+ * read operation, so let's use the last entry (15). >+ */ >+#define SEQID_LUT
