RE: [v1 12/17] ddr: altera: Add SDRAM driver for Intel N5X device
> -Original Message- > From: Tan, Ley Foon > Sent: Wednesday, 14 April, 2021 6:30 PM > To: Lim, Elly Siew Chin ; u-boot@lists.denx.de > Cc: Marek Vasut ; See, Chin Liang > ; Simon Goldschmidt > ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai > Subject: RE: [v1 12/17] ddr: altera: Add SDRAM driver for Intel N5X device > > > > > -Original Message- > > From: Lim, Elly Siew Chin > > Sent: Wednesday, March 31, 2021 10:39 PM > > To: u-boot@lists.denx.de > > Cc: Marek Vasut ; Tan, Ley Foon > > ; See, Chin Liang ; > > Simon Goldschmidt ; Chee, Tien Fong > > ; Westergreen, Dalon > > ; Simon Glass ; Gan, > > Yau Wai ; Lim, Elly Siew Chin > > > > Subject: [v1 12/17] ddr: altera: Add SDRAM driver for Intel N5X device > > > > The DDR subsystem in Diamond Mesa is consisted of controller, PHY, > > memory reset manager and memory clock manager. > > > > Configuration settings of controller, PHY and memory reset manager > > is come from DDR handoff data in bitstream, which contain the register > > base addresses and user settings from Quartus. > > > > Configuration settings of memory clock manager is come from the HPS > > handoff data in bitstream, however the register base address is defined > > in device tree. > > > > The calibration is fully done in HPS, which requires IMEM and DMEM > > binaries loading to PHY SRAM for running this calibration, both > > IMEM and DMEM binaries are also part of bitstream, this bitstream > > would be loaded to OCRAM by SDM, and configured by DDR driver. > > > > Signed-off-by: Siew Chin Lim > > Signed-off-by: Tien Fong Chee > > --- > > arch/arm/mach-socfpga/include/mach/firewall.h |6 + > > .../include/mach/system_manager_soc64.h| 10 +- > > drivers/ddr/altera/Makefile|3 +- > > drivers/ddr/altera/sdram_n5x.c | 2316 > > > drivers/ddr/altera/sdram_soc64.c | 10 +- > > 5 files changed, 2342 insertions(+), 3 deletions(-) > > create mode 100644 drivers/ddr/altera/sdram_n5x.c > > [...] > > > --- /dev/null > > +++ b/drivers/ddr/altera/sdram_n5x.c > > @@ -0,0 +1,2316 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Copyright (C) 2020-2021 Intel Corporation > > + * > > + */ > > + > > +#include > Sorting this. > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include "sdram_soc64.h" > > +#include > > + > > +DECLARE_GLOBAL_DATA_PTR; > > + > > +/* MPFE NOC registers */ > > +#define FPGA2SDRAM_MGR_MAIN_SIDEBANDMGR_FLAGOUTSET0 > > 0xF8024050 > > + > > +/* Memory reset manager */ > > +#define MEM_RST_MGR_STATUS 0x8 > > + > > +/* Register and bit in memory reset manager */ > > +#define MEM_RST_MGR_STATUS_RESET_COMPLETE BIT(0) > > +#define MEM_RST_MGR_STATUS_PWROKIN_STATUS BIT(1) > > +#define MEM_RST_MGR_STATUS_CONTROLLER_RST BIT(2) > > +#define MEM_RST_MGR_STATUS_AXI_RST BIT(3) > > + > > +#define TIMEOUT_200MS 200 > > +#define TIMEOUT_5000MS5000 > > + > > +/* DDR4 umctl2 */ > > +#define DDR4_MSTR_OFFSET 0x0 > > +#define DDR4_FREQ_RATIOBIT(22) > > + > > +#define DDR4_STAT_OFFSET 0x4 > > +#define DDR4_STAT_SELFREF_TYPE (BIT(5) | BIT(4)) > > +#define DDR4_STAT_SELFREF_TYPE_SHIFT 4 > > +#define DDR4_STAT_OPERATING_MODE (BIT(2) | BIT(1) | BIT(0)) > > + > > +#define DDR4_MRCTRL0_OFFSET0x10 > > +#define DDR4_MRCTRL0_MR_TYPE BIT(0) > > +#define DDR4_MRCTRL0_MPR_ENBIT(1) > > +#define DDR4_MRCTRL0_MR_RANK (BIT(5) | BIT(4)) > > +#define DDR4_MRCTRL0_MR_RANK_SHIFT 4 > > +#define DDR4_MRCTRL0_MR_ADDR (BIT(15) | BIT(14) | > BIT(13) | > > BIT(12)) > This is mask value? If yes, can use GENMASK() macro. > Same for the defines below. Okay. > > > +#define DDR4_MRCTRL0_MR_ADDR_SHIFT 12 > > +#define DDR4_MRCTRL0_MR_WR BIT(31) > > + > > +#define DDR4_MRCTRL1_OFFSET0x14 > > +#define DDR4_MRCTRL1_MR_DATA 0x3 > > + >
RE: [v1 12/17] ddr: altera: Add SDRAM driver for Intel N5X device
> -Original Message- > From: Lim, Elly Siew Chin > Sent: Wednesday, March 31, 2021 10:39 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon > ; See, Chin Liang ; > Simon Goldschmidt ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, > Yau Wai ; Lim, Elly Siew Chin > > Subject: [v1 12/17] ddr: altera: Add SDRAM driver for Intel N5X device > > The DDR subsystem in Diamond Mesa is consisted of controller, PHY, > memory reset manager and memory clock manager. > > Configuration settings of controller, PHY and memory reset manager > is come from DDR handoff data in bitstream, which contain the register > base addresses and user settings from Quartus. > > Configuration settings of memory clock manager is come from the HPS > handoff data in bitstream, however the register base address is defined > in device tree. > > The calibration is fully done in HPS, which requires IMEM and DMEM > binaries loading to PHY SRAM for running this calibration, both > IMEM and DMEM binaries are also part of bitstream, this bitstream > would be loaded to OCRAM by SDM, and configured by DDR driver. > > Signed-off-by: Siew Chin Lim > Signed-off-by: Tien Fong Chee > --- > arch/arm/mach-socfpga/include/mach/firewall.h |6 + > .../include/mach/system_manager_soc64.h| 10 +- > drivers/ddr/altera/Makefile|3 +- > drivers/ddr/altera/sdram_n5x.c | 2316 > > drivers/ddr/altera/sdram_soc64.c | 10 +- > 5 files changed, 2342 insertions(+), 3 deletions(-) > create mode 100644 drivers/ddr/altera/sdram_n5x.c [...] > --- /dev/null > +++ b/drivers/ddr/altera/sdram_n5x.c > @@ -0,0 +1,2316 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2020-2021 Intel Corporation > + * > + */ > + > +#include Sorting this. > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include "sdram_soc64.h" > +#include > + > +DECLARE_GLOBAL_DATA_PTR; > + > +/* MPFE NOC registers */ > +#define FPGA2SDRAM_MGR_MAIN_SIDEBANDMGR_FLAGOUTSET0 > 0xF8024050 > + > +/* Memory reset manager */ > +#define MEM_RST_MGR_STATUS 0x8 > + > +/* Register and bit in memory reset manager */ > +#define MEM_RST_MGR_STATUS_RESET_COMPLETEBIT(0) > +#define MEM_RST_MGR_STATUS_PWROKIN_STATUSBIT(1) > +#define MEM_RST_MGR_STATUS_CONTROLLER_RSTBIT(2) > +#define MEM_RST_MGR_STATUS_AXI_RST BIT(3) > + > +#define TIMEOUT_200MS 200 > +#define TIMEOUT_5000MS5000 > + > +/* DDR4 umctl2 */ > +#define DDR4_MSTR_OFFSET 0x0 > +#define DDR4_FREQ_RATIO BIT(22) > + > +#define DDR4_STAT_OFFSET 0x4 > +#define DDR4_STAT_SELFREF_TYPE (BIT(5) | BIT(4)) > +#define DDR4_STAT_SELFREF_TYPE_SHIFT 4 > +#define DDR4_STAT_OPERATING_MODE (BIT(2) | BIT(1) | BIT(0)) > + > +#define DDR4_MRCTRL0_OFFSET 0x10 > +#define DDR4_MRCTRL0_MR_TYPE BIT(0) > +#define DDR4_MRCTRL0_MPR_EN BIT(1) > +#define DDR4_MRCTRL0_MR_RANK (BIT(5) | BIT(4)) > +#define DDR4_MRCTRL0_MR_RANK_SHIFT 4 > +#define DDR4_MRCTRL0_MR_ADDR (BIT(15) | BIT(14) | BIT(13) | > BIT(12)) This is mask value? If yes, can use GENMASK() macro. Same for the defines below. > +#define DDR4_MRCTRL0_MR_ADDR_SHIFT 12 > +#define DDR4_MRCTRL0_MR_WR BIT(31) > + > +#define DDR4_MRCTRL1_OFFSET 0x14 > +#define DDR4_MRCTRL1_MR_DATA 0x3 > + > +#define DDR4_MRSTAT_OFFSET 0x18 > +#define DDR4_MRSTAT_MR_WR_BUSY BIT(0) > + > +#define DDR4_MRCTRL2_OFFSET 0x1C > + > +#define DDR4_PWRCTL_OFFSET 0x30 > +#define DDR4_PWRCTL_SELFREF_EN BIT(0) > +#define DDR4_PWRCTL_POWERDOWN_EN BIT(1) > +#define DDR4_PWRCTL_EN_DFI_DRAM_CLK_DISABLE BIT(3) > +#define DDR4_PWRCTL_SELFREF_SW BIT(5) > + > +#define DDR4_PWRTMG_OFFSET 0x34 > +#define DDR4_HWLPCTL_OFFSET 0x38 > +#define DDR4_RFSHCTL0_OFFSET 0x50 > +#define DDR4_RFSHCTL1_OFFSET 0x54 > + > +#define DDR4_RFSHCTL3_OFFSET 0x60 > +#define DDR4_RFSHCTL3_DIS_AUTO_REFRESH BIT(0) > +#define DDR4_RFSHCTL3_REFRESH_MODE (BIT(6) | BIT(5) | > BIT(4)) > +#define DDR4_RFSHCTL3_REFRESH_MODE_SHIFT 4 > + > +#define DDR4_ECCCFG0_OFFSET 0x70 > +#define DDR4_ECC_MODE(BIT(2) | BIT(1) | BIT(0)) > +#define DDR4_DIS_SCRUB BIT(4) > +#define LPDDR4_ECCCFG0_ECC_REGION_MAP_GRANU_SHIFT30 > +#define LPDDR4_ECCCFG0_ECC_REGION_MAP_SHIFT 8 > + > +#define DDR4_ECCCFG1_OFFSET 0x74 > +#define LPDDR4_ECCCFG1_ECC_REGIONS_PARITY_LOCK BIT(4) > + > +#define DDR4_CRCPARCTL0_OFFSET 0xC0 > +#define DDR4_CRCPARCT
