Hi,
> On 4/7/21 11:05 AM, zhengxunli wrote:
> > The Clocking Wizard IP supports clock circuits customized
> > to your clocking requirements. The wizard support for
> > dynamically reconfiguring the clocking primitives for
> > Multiply, Divide, Phase Shift/Offset, or Duty Cycle.
> >
> > Limited by uboot clk uclass without set_phase API, this
> > patch only provides set_rate to modify the frequency and
> > set 50% duty cycle by default.
> >
> > Signed-off-by: zhengxunli
>
> Please use full name.
Okay, got it.
>
> > ---
> > drivers/clk/Kconfig | 7 ++
> > drivers/clk/Makefile | 1 +
> > drivers/clk/clk_wizard.c | 180 ++
> +
> > 3 files changed, 188 insertions(+)
> > create mode 100644 drivers/clk/clk_wizard.c
> >
> > diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> > index 4aeaa0c..4ebeccc 100644
> > --- a/drivers/clk/Kconfig
> > +++ b/drivers/clk/Kconfig
> > @@ -136,6 +136,13 @@ config CLK_ZYNQMP
> > This clock driver adds support for clock realted settings for
> > ZynqMP platform.
> >
> > +config CLK_WIZARD
>
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
> tree/drivers/staging/clocking-wizard/Kconfig?h=v5.12-rc6
>
> Small alignment with kernel would be useful.
> At least CLK_XLNX_CLKWZRD.
>
> > + bool "Enable clock wizard driver support for zynq"
> > + depends on CLK && ARCH_ZYNQ
>
> Clocking wizard is standard PL based IP not just related to Zynq. It can
> be used by Microblaze, ARM cores, etc. It means no need to have
> dependency on ZYNQ here.
>
> > + help
> > + This clock driver adds support for clock wizard setting for
> > + Zynq platform.
>
> ditto
>
Okay, I will fix in the next version.
> > +
> > config CLK_STM32MP1
> > bool "Enable RCC clock driver for STM32MP1"
> > depends on ARCH_STM32MP && CLK
> > diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> > index 645709b..d8b878c 100644
> > --- a/drivers/clk/Makefile
> > +++ b/drivers/clk/Makefile
> > @@ -43,6 +43,7 @@ obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
> > obj-$(CONFIG_CLK_VEXPRESS_OSC) += clk_vexpress_osc.o
> > obj-$(CONFIG_CLK_ZYNQ) += clk_zynq.o
> > obj-$(CONFIG_CLK_ZYNQMP) += clk_zynqmp.o
> > +obj-$(CONFIG_CLK_WIZARD) += clk_wizard.o
> > obj-$(CONFIG_ICS8N3QV01) += ics8n3qv01.o
> > obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
> > obj-$(CONFIG_SANDBOX) += clk_sandbox.o
> > diff --git a/drivers/clk/clk_wizard.c b/drivers/clk/clk_wizard.c
> > new file mode 100644
> > index 000..f5c2387
> > --- /dev/null
> > +++ b/drivers/clk/clk_wizard.c
>
> name could be also aligned with kernel to have easier match with the
kernel.
Okay, got it.
>
> > @@ -0,0 +1,180 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Xilinx 'Clocking Wizard' driver
> > + *
> > + * Copyright (c) 2021 Macronix Inc.
> > + *
> > + * Author: Zhengxun Li
> > + */
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +#define SRR 0x0
> > +
> > +#define SR 0x4
> > +#define SR_LOCKED BIT(0)
> > +
> > +#define CCR(x) (0x200 + ((x) * 4))
> > +
> > +#define FBOUT_CFG CCR(0)
> > +#define FBOUT_DIV(x) (x)
> > +#define FBOUT_GET_DIV(x) ((x) & GENMASK(7, 0))
> > +#define FBOUT_MUL(x) ((x) << 8)
> > +#define FBOUT_GET_MUL(x) (((x) & GENMASK(15, 8)) >> 8)
> > +#define FBOUT_FRAC(x) ((x) << 16)
> > +#define FBOUT_GET_FRAC(x) (((x) & GENMASK(25, 16)) >> 16)
> > +#define FBOUT_FRAC_EN BIT(26)
> > +
> > +#define FBOUT_PHASE CCR(1)
> > +
> > +#define OUT_CFG(x) CCR(2 + ((x) * 3))
> > +#define OUT_DIV(x) (x)
> > +#define OUT_GET_DIV(x) ((x) & GENMASK(7, 0))
> > +#define OUT_FRAC(x) ((x) << 8)
> > +#define OUT_GET_FRAC(x) (((x) & GENMASK(17, 8)) >> 8)
> > +#define OUT_FRAC_EN BIT(18)
> > +
> > +#define OUT_PHASE(x) CCR(3 + ((x) * 3))
> > +#define OUT_DUTY(x) CCR(4 + ((x) * 3))
> > +
> > +#define CTRL CCR(23)
> > +#define CTRL_SEN BIT(2)
> > +#define CTRL_SADDR BIT(1)
> > +#define CTRL_LOAD BIT(0)
> > +
> > +/*
>
> /** for kernel-doc as noted below.
>
> > + * MMCM Block Diagram
> > + *
> > + * ++ +-+
> > + * input ->| vco_clk_div_hw |->| vco_clk_mul_hw |--+
> > + * rate| (int divide) | | (frac multiply) | |
> > + * ++ +-+ |
> > + * |
> > + * +VCO-rate---+
> > + * |
> > + * | ++
> > + * +->| clkout[0] |-> output0 rate
> > + * | | (frac divide) |
> > + * | ++
> > + * |
> > + * | ++
> > + * +->| clkout[1] |-> output1 rate
> > + * | | (int divide) |
> > + * | ++
> > + * |
> > + * ...
> > + * |
> > + * | ++
> > + * +->| clkout[1] |-> output6 rate
> > + * | (int divide) |
> > + *
