Re: [RFC PATCH 16/17] arm: sunxi: add Allwinner T113s devicetree stub
在 2023-01-03星期二的 17:38 +，Andre Przywara写道：
> On Tue, 06 Dec 2022 13:55:02 +0800
> Icenowy Zheng wrote:
>
> Hi Icenowy,
>
> > 在 2022-12-06星期二的 00:45 +，Andre Przywara写道：
> > > This adds the basic SoC .dtsi devicetree stub for the Allwinner
> > > T113s
> > > SoC. This shares a die with the Allwinner D1 SoC (with RISC-V
> > > cores),
> > > but uses two Cortex-A7 cores instead of the T-HEAD C906 RISC-V
> > > core.
> > >
> > > Include the existing D1 devicetree stub, but add the ARM specific
> > > nodes,
> > > like for the CPU, the arch timer and the GIC.
> > >
> > > Signed-off-by: Andre Przywara
> > > ---
> > > arch/arm/dts/sun8i-t113s.dtsi | 59
> > > +++
> > > 1 file changed, 59 insertions(+)
> > > create mode 100644 arch/arm/dts/sun8i-t113s.dtsi
> > >
> > > diff --git a/arch/arm/dts/sun8i-t113s.dtsi b/arch/arm/dts/sun8i-
> > > t113s.dtsi
> > > new file mode 100644
> > > index 000..0919ce559f6
> > > --- /dev/null
> > > +++ b/arch/arm/dts/sun8i-t113s.dtsi
> > > @@ -0,0 +1,59 @@
> > > +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> > > +// Copyright (C) 2022 Arm Ltd.
> > > +
> > > +#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr
> > > +
> > > +#include
> > > +#include <../../riscv/dts/sunxi-d1s-t113.dtsi>
> >
> > Should we make a R528 DTSI which includes d1-t113.dtsi, and then
> > T113
> > DTSI which includes d1s-t113.dtsi ?
>
> If I understand Samuel correctly, the T113-s includes the DSP, in
> contrast
> to the D1s, which has fused that off.
> That would make including both sunxi-d1*-t113.dtsi files the right
> choice,
> wouldn't it? According to Samuel's list, sunxi-d1-t113.dtsi contains
> DSP
> related peripherals.
Okay, although I heard that the DSP is not fused off (because DSP RAM
is used by BROM).
>
> I don't know if there is anything DT relevant that the R528 has over
> the
> T113-s, but I don't claim to provide an R528 DT anyway, at least not
> yet,
> so we can leave this for the future, should a board or manual emerge.
>
> So this file here should to be the equivalent of sun20i-d1s.dtsi,
> providing the ARM specific bits.
>
> Does that make sense? If you agree, I would post this to Linux ASAP.
It sounds good.
>
> Cheers,
> Andre
>
>
> > > +#include <../../riscv/dts/sunxi-d1-t113.dtsi>
> > > +
> > > +/ {
> > > + interrupt-parent = <>;
> > > +
> > > + cpus {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > +
> > > + cpu0: cpu@0 {
> > > + compatible = "arm,cortex-a7";
> > > + device_type = "cpu";
> > > + reg = <0>;
> > > + clocks = < CLK_CPUX>;
> > > + clock-names = "cpu";
> > > + };
> > > +
> > > + cpu1: cpu@1 {
> > > + compatible = "arm,cortex-a7";
> > > + device_type = "cpu";
> > > + reg = <1>;
> > > + clocks = < CLK_CPUX>;
> > > + clock-names = "cpu";
> > > + };
> > > + };
> > > +
> > > + gic: interrupt-controller@1c81000 {
> > > + compatible = "arm,gic-400";
> > > + reg = <0x03021000 0x1000>,
> > > + <0x03022000 0x2000>,
> > > + <0x03024000 0x2000>,
> > > + <0x03026000 0x2000>;
> > > + interrupts = > > |
> > > IRQ_TYPE_LEVEL_HIGH)>;
> > > + interrupt-controller;
> > > + #interrupt-cells = <3>;
> > > + };
> > > +
> > > + timer {
> > > + compatible = "arm,armv7-timer";
> > > + interrupts = > > |
> > > IRQ_TYPE_LEVEL_LOW)>,
> > > + > > |
> > > IRQ_TYPE_LEVEL_LOW)>,
> > > + > > |
> > > IRQ_TYPE_LEVEL_LOW)>,
> > > + > > |
> > > IRQ_TYPE_LEVEL_LOW)>;
> > > + };
> > > +
> > > + pmu {
> > > + compatible = "arm,cortex-a7-pmu";
> > > + interrupts = ,
> > > + ;
> > > + interrupt-affinity = <>, <>;
> > > + };
> > > +};
> >
>
Re: [RFC PATCH 16/17] arm: sunxi: add Allwinner T113s devicetree stub
On Tue, 06 Dec 2022 13:55:02 +0800
Icenowy Zheng wrote:
Hi Icenowy,
> 在 2022-12-06星期二的 00:45 +，Andre Przywara写道：
> > This adds the basic SoC .dtsi devicetree stub for the Allwinner T113s
> > SoC. This shares a die with the Allwinner D1 SoC (with RISC-V cores),
> > but uses two Cortex-A7 cores instead of the T-HEAD C906 RISC-V core.
> >
> > Include the existing D1 devicetree stub, but add the ARM specific
> > nodes,
> > like for the CPU, the arch timer and the GIC.
> >
> > Signed-off-by: Andre Przywara
> > ---
> > arch/arm/dts/sun8i-t113s.dtsi | 59
> > +++
> > 1 file changed, 59 insertions(+)
> > create mode 100644 arch/arm/dts/sun8i-t113s.dtsi
> >
> > diff --git a/arch/arm/dts/sun8i-t113s.dtsi b/arch/arm/dts/sun8i-
> > t113s.dtsi
> > new file mode 100644
> > index 000..0919ce559f6
> > --- /dev/null
> > +++ b/arch/arm/dts/sun8i-t113s.dtsi
> > @@ -0,0 +1,59 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> > +// Copyright (C) 2022 Arm Ltd.
> > +
> > +#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr
> > +
> > +#include
> > +#include <../../riscv/dts/sunxi-d1s-t113.dtsi>
>
> Should we make a R528 DTSI which includes d1-t113.dtsi, and then T113
> DTSI which includes d1s-t113.dtsi ?
If I understand Samuel correctly, the T113-s includes the DSP, in contrast
to the D1s, which has fused that off.
That would make including both sunxi-d1*-t113.dtsi files the right choice,
wouldn't it? According to Samuel's list, sunxi-d1-t113.dtsi contains DSP
related peripherals.
I don't know if there is anything DT relevant that the R528 has over the
T113-s, but I don't claim to provide an R528 DT anyway, at least not yet,
so we can leave this for the future, should a board or manual emerge.
So this file here should to be the equivalent of sun20i-d1s.dtsi,
providing the ARM specific bits.
Does that make sense? If you agree, I would post this to Linux ASAP.
Cheers,
Andre
> > +#include <../../riscv/dts/sunxi-d1-t113.dtsi>
> > +
> > +/ {
> > + interrupt-parent = <>;
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + cpu0: cpu@0 {
> > + compatible = "arm,cortex-a7";
> > + device_type = "cpu";
> > + reg = <0>;
> > + clocks = < CLK_CPUX>;
> > + clock-names = "cpu";
> > + };
> > +
> > + cpu1: cpu@1 {
> > + compatible = "arm,cortex-a7";
> > + device_type = "cpu";
> > + reg = <1>;
> > + clocks = < CLK_CPUX>;
> > + clock-names = "cpu";
> > + };
> > + };
> > +
> > + gic: interrupt-controller@1c81000 {
> > + compatible = "arm,gic-400";
> > + reg = <0x03021000 0x1000>,
> > + <0x03022000 0x2000>,
> > + <0x03024000 0x2000>,
> > + <0x03026000 0x2000>;
> > + interrupts = > IRQ_TYPE_LEVEL_HIGH)>;
> > + interrupt-controller;
> > + #interrupt-cells = <3>;
> > + };
> > +
> > + timer {
> > + compatible = "arm,armv7-timer";
> > + interrupts = > IRQ_TYPE_LEVEL_LOW)>,
> > + > IRQ_TYPE_LEVEL_LOW)>,
> > + > IRQ_TYPE_LEVEL_LOW)>,
> > + > IRQ_TYPE_LEVEL_LOW)>;
> > + };
> > +
> > + pmu {
> > + compatible = "arm,cortex-a7-pmu";
> > + interrupts = ,
> > + ;
> > + interrupt-affinity = <>, <>;
> > + };
> > +};
>
Re: [RFC PATCH 16/17] arm: sunxi: add Allwinner T113s devicetree stub
在 2022-12-06星期二的 00:45 +，Andre Przywara写道：
> This adds the basic SoC .dtsi devicetree stub for the Allwinner T113s
> SoC. This shares a die with the Allwinner D1 SoC (with RISC-V cores),
> but uses two Cortex-A7 cores instead of the T-HEAD C906 RISC-V core.
>
> Include the existing D1 devicetree stub, but add the ARM specific
> nodes,
> like for the CPU, the arch timer and the GIC.
>
> Signed-off-by: Andre Przywara
> ---
> arch/arm/dts/sun8i-t113s.dtsi | 59
> +++
> 1 file changed, 59 insertions(+)
> create mode 100644 arch/arm/dts/sun8i-t113s.dtsi
>
> diff --git a/arch/arm/dts/sun8i-t113s.dtsi b/arch/arm/dts/sun8i-
> t113s.dtsi
> new file mode 100644
> index 000..0919ce559f6
> --- /dev/null
> +++ b/arch/arm/dts/sun8i-t113s.dtsi
> @@ -0,0 +1,59 @@
> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> +// Copyright (C) 2022 Arm Ltd.
> +
> +#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr
> +
> +#include
> +#include <../../riscv/dts/sunxi-d1s-t113.dtsi>
Should we make a R528 DTSI which includes d1-t113.dtsi, and then T113
DTSI which includes d1s-t113.dtsi ?
> +#include <../../riscv/dts/sunxi-d1-t113.dtsi>
> +
> +/ {
> + interrupt-parent = <>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + compatible = "arm,cortex-a7";
> + device_type = "cpu";
> + reg = <0>;
> + clocks = < CLK_CPUX>;
> + clock-names = "cpu";
> + };
> +
> + cpu1: cpu@1 {
> + compatible = "arm,cortex-a7";
> + device_type = "cpu";
> + reg = <1>;
> + clocks = < CLK_CPUX>;
> + clock-names = "cpu";
> + };
> + };
> +
> + gic: interrupt-controller@1c81000 {
> + compatible = "arm,gic-400";
> + reg = <0x03021000 0x1000>,
> + <0x03022000 0x2000>,
> + <0x03024000 0x2000>,
> + <0x03026000 0x2000>;
> + interrupts = IRQ_TYPE_LEVEL_HIGH)>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + };
> +
> + timer {
> + compatible = "arm,armv7-timer";
> + interrupts = IRQ_TYPE_LEVEL_LOW)>,
> + IRQ_TYPE_LEVEL_LOW)>,
> + IRQ_TYPE_LEVEL_LOW)>,
> + IRQ_TYPE_LEVEL_LOW)>;
> + };
> +
> + pmu {
> + compatible = "arm,cortex-a7-pmu";
> + interrupts = ,
> + ;
> + interrupt-affinity = <>, <>;
> + };
> +};
