Re: [U-Boot] [PATCH] drivers: mtd: add Microchip PIC32 internal non-CFI flash driver.
On 16 March 2016 at 16:37, Purna Chandra Mandal wrote: > On 03/15/2016 05:35 PM, Jagan Teki wrote: > >> On 14 March 2016 at 19:37, Purna Chandra Mandal >> wrote: >>> Jagan. >>> >>> On 03/14/2016 07:16 PM, Jagan Teki wrote: >>> On Monday 14 March 2016 07:00 PM, Purna Chandra Mandal wrote: > On 03/14/2016 06:13 PM, Daniel Schwierzeck wrote: >> 2016-03-10 14:12 GMT+01:00 Purna Chandra Mandal >> : >>> PIC32 embedded flash banks are memory mapped, directly read by CPU, >>> and programming (erase followed by write) operation on them are >>> handled by on-chip NVM controller. >>> Signed-off-by: Purna Chandra Mandal >>> --- >>> drivers/mtd/Kconfig | 6 + >>> drivers/mtd/Makefile | 1 + >>> drivers/mtd/pic32_flash.c | 377 >>> ++ BTW: this driver need to be write in mtd driver mode, see for existing drivers and let me know for any help. >>> Will take up this activity [of supporting MTD] later on. For the time-being >>> we are >>> not using mtd on embedded flash, mainly using for environment and bootcode >>> which >>> are at well-known offset, size defined in include/configs/. >> I understand your concern, but It look very hard to maintain the new >> drivers with non-dm model. > > If issue is only non-dm model I can add DM support with exception that it > will not > implement MTD functionality. OK, Adding mtd dm is straight forward with registering MTD_UCLASS and mtd_info ops please check drivers/mtd/altera_qspi.c for more info. Mean while I will come back again for my inputs. > >> My suggestions are better to add this on existing mtd(cfi or >> something) I guess ie "not possible" or move this driver to your soc >> or board code for time being till mtd uclass addition or write a fresh >> mtd dm driver. > > PIC32 flash devices are non CFI/JEDEC compliant so no way we can separate one > flash > chip from other. Even though flash devices are parallel erase and program on > these > flash chips are performed through NVM controller (serial interface). So we > can't > directly port the functionality on CFI driver. > > I like the idea of adding this driver under arch/soc/ or board/. But that is > where it was > initially added, but based on review comment it is moved to drivers/mtd/. > > Please suggest me a way! -- Jagan. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] drivers: mtd: add Microchip PIC32 internal non-CFI flash driver.
On 03/15/2016 05:35 PM, Jagan Teki wrote: > On 14 March 2016 at 19:37, Purna Chandra Mandal > wrote: >> Jagan. >> >> On 03/14/2016 07:16 PM, Jagan Teki wrote: >> >>> On Monday 14 March 2016 07:00 PM, Purna Chandra Mandal wrote: On 03/14/2016 06:13 PM, Daniel Schwierzeck wrote: > 2016-03-10 14:12 GMT+01:00 Purna Chandra Mandal > : >> PIC32 embedded flash banks are memory mapped, directly read by CPU, >> and programming (erase followed by write) operation on them are >> handled by on-chip NVM controller. >> Signed-off-by: Purna Chandra Mandal >> --- >> drivers/mtd/Kconfig | 6 + >> drivers/mtd/Makefile | 1 + >> drivers/mtd/pic32_flash.c | 377 >> ++ >>> BTW: this driver need to be write in mtd driver mode, see for existing >>> drivers and let me know for any help. >> Will take up this activity [of supporting MTD] later on. For the time-being >> we are >> not using mtd on embedded flash, mainly using for environment and bootcode >> which >> are at well-known offset, size defined in include/configs/. > I understand your concern, but It look very hard to maintain the new > drivers with non-dm model. If issue is only non-dm model I can add DM support with exception that it will not implement MTD functionality. > My suggestions are better to add this on existing mtd(cfi or > something) I guess ie "not possible" or move this driver to your soc > or board code for time being till mtd uclass addition or write a fresh > mtd dm driver. PIC32 flash devices are non CFI/JEDEC compliant so no way we can separate one flash chip from other. Even though flash devices are parallel erase and program on these flash chips are performed through NVM controller (serial interface). So we can't directly port the functionality on CFI driver. I like the idea of adding this driver under arch/soc/ or board/. But that is where it was initially added, but based on review comment it is moved to drivers/mtd/. Please suggest me a way! > thanks! ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] drivers: mtd: add Microchip PIC32 internal non-CFI flash driver.
On 14 March 2016 at 19:37, Purna Chandra Mandal wrote: > Jagan. > > On 03/14/2016 07:16 PM, Jagan Teki wrote: > >> On Monday 14 March 2016 07:00 PM, Purna Chandra Mandal wrote: >>> On 03/14/2016 06:13 PM, Daniel Schwierzeck wrote: 2016-03-10 14:12 GMT+01:00 Purna Chandra Mandal : > PIC32 embedded flash banks are memory mapped, directly read by CPU, > and programming (erase followed by write) operation on them are > handled by on-chip NVM controller. > Signed-off-by: Purna Chandra Mandal > --- > drivers/mtd/Kconfig | 6 + > drivers/mtd/Makefile | 1 + > drivers/mtd/pic32_flash.c | 377 > ++ >> BTW: this driver need to be write in mtd driver mode, see for existing >> drivers and let me know for any help. > > Will take up this activity [of supporting MTD] later on. For the time-being > we are > not using mtd on embedded flash, mainly using for environment and bootcode > which > are at well-known offset, size defined in include/configs/. I understand your concern, but It look very hard to maintain the new drivers with non-dm model. My suggestions are better to add this on existing mtd(cfi or something) I guess ie "not possible" or move this driver to your soc or board code for time being till mtd uclass addition or write a fresh mtd dm driver. thanks! -- Jagan. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] drivers: mtd: add Microchip PIC32 internal non-CFI flash driver.
Jagan. On 03/14/2016 07:16 PM, Jagan Teki wrote: > On Monday 14 March 2016 07:00 PM, Purna Chandra Mandal wrote: >> On 03/14/2016 06:13 PM, Daniel Schwierzeck wrote: >>> 2016-03-10 14:12 GMT+01:00 Purna Chandra Mandal >>> : PIC32 embedded flash banks are memory mapped, directly read by CPU, and programming (erase followed by write) operation on them are handled by on-chip NVM controller. Signed-off-by: Purna Chandra Mandal --- drivers/mtd/Kconfig | 6 + drivers/mtd/Makefile | 1 + drivers/mtd/pic32_flash.c | 377 ++ > BTW: this driver need to be write in mtd driver mode, see for existing > drivers and let me know for any help. Will take up this activity [of supporting MTD] later on. For the time-being we are not using mtd on embedded flash, mainly using for environment and bootcode which are at well-known offset, size defined in include/configs/. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] drivers: mtd: add Microchip PIC32 internal non-CFI flash driver.
On Monday 14 March 2016 07:00 PM, Purna Chandra Mandal wrote: On 03/14/2016 06:13 PM, Daniel Schwierzeck wrote: 2016-03-10 14:12 GMT+01:00 Purna Chandra Mandal : PIC32 embedded flash banks are memory mapped, directly read by CPU, and programming (erase followed by write) operation on them are handled by on-chip NVM controller. Signed-off-by: Purna Chandra Mandal --- drivers/mtd/Kconfig | 6 + drivers/mtd/Makefile | 1 + drivers/mtd/pic32_flash.c | 377 ++ BTW: this driver need to be write in mtd driver mode, see for existing drivers and let me know for any help. -- Jagan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] drivers: mtd: add Microchip PIC32 internal non-CFI flash driver.
On 03/14/2016 06:13 PM, Daniel Schwierzeck wrote:
> 2016-03-10 14:12 GMT+01:00 Purna Chandra Mandal :
>> PIC32 embedded flash banks are memory mapped, directly read by CPU,
>> and programming (erase followed by write) operation on them are
>> handled by on-chip NVM controller.
>>
>> Signed-off-by: Purna Chandra Mandal
>>
>> ---
>>
>> drivers/mtd/Kconfig | 6 +
>> drivers/mtd/Makefile | 1 +
>> drivers/mtd/pic32_flash.c | 377
>> ++
>> include/flash.h | 5 +-
>> 4 files changed, 388 insertions(+), 1 deletion(-)
>> create mode 100644 drivers/mtd/pic32_flash.c
>>
>> diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
>> index c58841e..e3c6b9f 100644
>> --- a/drivers/mtd/Kconfig
>> +++ b/drivers/mtd/Kconfig
>> @@ -30,6 +30,12 @@ config ALTERA_QSPI
>>
>> endmenu
>>
>> +config FLASH_PIC32
>> + bool "Microchip PIC32 Flash driver"
> you should add: depends on MACH_PIC32
ack. Will add,
>> + help
>> + This enables access to Microchip PIC32 internal non-CFI flash
>> + chips through PIC32 Non-Volatile-Memory Controller.
>> +
>> source "drivers/mtd/nand/Kconfig"
>>
>> source "drivers/mtd/spi/Kconfig"
>> diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile
>> index 7f018a4..9380085 100644
>> --- a/drivers/mtd/Makefile
>> +++ b/drivers/mtd/Makefile
>> @@ -19,4 +19,5 @@ obj-$(CONFIG_HAS_DATAFLASH) += dataflash.o
>> obj-$(CONFIG_FTSMC020) += ftsmc020.o
>> obj-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o
>> obj-$(CONFIG_MW_EEPROM) += mw_eeprom.o
>> +obj-$(CONFIG_FLASH_PIC32) += pic32_flash.o
>> obj-$(CONFIG_ST_SMI) += st_smi.o
>> diff --git a/drivers/mtd/pic32_flash.c b/drivers/mtd/pic32_flash.c
>> new file mode 100644
>> index 000..9a226b1
>> --- /dev/null
>> +++ b/drivers/mtd/pic32_flash.c
>> @@ -0,0 +1,377 @@
>> +/*
>> + * Copyright (C) 2015
>> + * Cristian Birsan
>> + * Purna Chandra Mandal
>> + *
>> + * SPDX-License-Identifier:GPL-2.0+
>> + */
>> +
>> +#include
>> +#include
>> +#include
>> +#include
>> +
>> +/* NVM Controller registers */
>> +struct pic32_reg_nvm {
>> + struct pic32_reg_atomic ctrl;
>> + struct pic32_reg_atomic key;
>> + struct pic32_reg_atomic addr;
>> + struct pic32_reg_atomic data;
>> +};
>> +
>> +/* NVM operations */
>> +#define NVMOP_NOP 0
>> +#define NVMOP_WORD_WRITE 1
>> +#define NVMOP_PAGE_ERASE 4
>> +
>> +/* NVM control bits */
>> +#define NVM_WR BIT(15)
>> +#define NVM_WREN BIT(14)
>> +#define NVM_WRERR BIT(13)
>> +#define NVM_LVDERR BIT(12)
>> +
>> +/* NVM programming unlock register */
>> +#define LOCK_KEY 0x0
>> +#define UNLOCK_KEY10xaa996655
>> +#define UNLOCK_KEY20x556699aa
>> +
>> +/* PIC32 flash banks consist of number of pages, each page
>> + * into number of row and rows are into number of words.
>> + * Here we will maintain page information instead of sector.
>> + */
>> +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
>> +static struct pic32_reg_nvm *nvm_regs_p;
>> +
>> +static inline void flash_initiate_operation(u32 nvmop)
>> +{
>> + /* set operation */
>> + writel(nvmop, &nvm_regs_p->ctrl.raw);
>> +
>> + /* enable flash write */
>> + writel(NVM_WREN, &nvm_regs_p->ctrl.set);
>> +
>> + /* unlock sequence */
>> + writel(LOCK_KEY, &nvm_regs_p->key.raw);
>> + writel(UNLOCK_KEY1, &nvm_regs_p->key.raw);
>> + writel(UNLOCK_KEY2, &nvm_regs_p->key.raw);
>> +
>> + /* initiate operation */
>> + writel(NVM_WR, &nvm_regs_p->ctrl.set);
>> +}
>> +
>> +static int flash_wait_till_busy(const char *func, ulong timeout)
>> +{
>> + int ret = wait_for_bit(__func__, &nvm_regs_p->ctrl.raw,
>> + NVM_WR, false, timeout, false);
>> +
>> + return ret ? ERR_TIMOUT : ERR_OK;
>> +}
>> +
>> +static inline int flash_complete_operation(void)
>> +{
>> + u32 v;
>> +
>> + v = readl(&nvm_regs_p->ctrl.raw);
>> + if (v & NVM_WRERR) {
>> + printf("Error in Block Erase - Lock Bit may be set!\n");
>> + flash_initiate_operation(NVMOP_NOP);
>> + return ERR_PROTECTED;
>> + }
>> +
>> + if (v & NVM_LVDERR) {
>> + printf("Error in Block Erase - low-vol detected!\n");
>> + flash_initiate_operation(NVMOP_NOP);
>> + return ERR_NOT_ERASED;
>> + }
>> +
>> + /* disable flash write or erase operation */
>> + writel(NVM_WREN, &nvm_regs_p->ctrl.clr);
>> +
>> + return ERR_OK;
>> +}
>> +
>> +int flash_erase(flash_info_t *info, int s_first, int s_last)
>> +{
>> + ulong sect_start, sect_end, flags;
>> + int prot, sect;
>> + int rc;
>> +
>> + if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_MCHP) {
>> + printf("Can't erase unknown flash type %08lx - aborted\n",
>> + info->f
Re: [U-Boot] [PATCH] drivers: mtd: add Microchip PIC32 internal non-CFI flash driver.
2016-03-10 14:12 GMT+01:00 Purna Chandra Mandal :
> PIC32 embedded flash banks are memory mapped, directly read by CPU,
> and programming (erase followed by write) operation on them are
> handled by on-chip NVM controller.
>
> Signed-off-by: Purna Chandra Mandal
>
> ---
>
> drivers/mtd/Kconfig | 6 +
> drivers/mtd/Makefile | 1 +
> drivers/mtd/pic32_flash.c | 377
> ++
> include/flash.h | 5 +-
> 4 files changed, 388 insertions(+), 1 deletion(-)
> create mode 100644 drivers/mtd/pic32_flash.c
>
> diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
> index c58841e..e3c6b9f 100644
> --- a/drivers/mtd/Kconfig
> +++ b/drivers/mtd/Kconfig
> @@ -30,6 +30,12 @@ config ALTERA_QSPI
>
> endmenu
>
> +config FLASH_PIC32
> + bool "Microchip PIC32 Flash driver"
you should add: depends on MACH_PIC32
> + help
> + This enables access to Microchip PIC32 internal non-CFI flash
> + chips through PIC32 Non-Volatile-Memory Controller.
> +
> source "drivers/mtd/nand/Kconfig"
>
> source "drivers/mtd/spi/Kconfig"
> diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile
> index 7f018a4..9380085 100644
> --- a/drivers/mtd/Makefile
> +++ b/drivers/mtd/Makefile
> @@ -19,4 +19,5 @@ obj-$(CONFIG_HAS_DATAFLASH) += dataflash.o
> obj-$(CONFIG_FTSMC020) += ftsmc020.o
> obj-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o
> obj-$(CONFIG_MW_EEPROM) += mw_eeprom.o
> +obj-$(CONFIG_FLASH_PIC32) += pic32_flash.o
> obj-$(CONFIG_ST_SMI) += st_smi.o
> diff --git a/drivers/mtd/pic32_flash.c b/drivers/mtd/pic32_flash.c
> new file mode 100644
> index 000..9a226b1
> --- /dev/null
> +++ b/drivers/mtd/pic32_flash.c
> @@ -0,0 +1,377 @@
> +/*
> + * Copyright (C) 2015
> + * Cristian Birsan
> + * Purna Chandra Mandal
> + *
> + * SPDX-License-Identifier:GPL-2.0+
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +
> +/* NVM Controller registers */
> +struct pic32_reg_nvm {
> + struct pic32_reg_atomic ctrl;
> + struct pic32_reg_atomic key;
> + struct pic32_reg_atomic addr;
> + struct pic32_reg_atomic data;
> +};
> +
> +/* NVM operations */
> +#define NVMOP_NOP 0
> +#define NVMOP_WORD_WRITE 1
> +#define NVMOP_PAGE_ERASE 4
> +
> +/* NVM control bits */
> +#define NVM_WR BIT(15)
> +#define NVM_WREN BIT(14)
> +#define NVM_WRERR BIT(13)
> +#define NVM_LVDERR BIT(12)
> +
> +/* NVM programming unlock register */
> +#define LOCK_KEY 0x0
> +#define UNLOCK_KEY10xaa996655
> +#define UNLOCK_KEY20x556699aa
> +
> +/* PIC32 flash banks consist of number of pages, each page
> + * into number of row and rows are into number of words.
> + * Here we will maintain page information instead of sector.
> + */
> +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
> +static struct pic32_reg_nvm *nvm_regs_p;
> +
> +static inline void flash_initiate_operation(u32 nvmop)
> +{
> + /* set operation */
> + writel(nvmop, &nvm_regs_p->ctrl.raw);
> +
> + /* enable flash write */
> + writel(NVM_WREN, &nvm_regs_p->ctrl.set);
> +
> + /* unlock sequence */
> + writel(LOCK_KEY, &nvm_regs_p->key.raw);
> + writel(UNLOCK_KEY1, &nvm_regs_p->key.raw);
> + writel(UNLOCK_KEY2, &nvm_regs_p->key.raw);
> +
> + /* initiate operation */
> + writel(NVM_WR, &nvm_regs_p->ctrl.set);
> +}
> +
> +static int flash_wait_till_busy(const char *func, ulong timeout)
> +{
> + int ret = wait_for_bit(__func__, &nvm_regs_p->ctrl.raw,
> + NVM_WR, false, timeout, false);
> +
> + return ret ? ERR_TIMOUT : ERR_OK;
> +}
> +
> +static inline int flash_complete_operation(void)
> +{
> + u32 v;
> +
> + v = readl(&nvm_regs_p->ctrl.raw);
> + if (v & NVM_WRERR) {
> + printf("Error in Block Erase - Lock Bit may be set!\n");
> + flash_initiate_operation(NVMOP_NOP);
> + return ERR_PROTECTED;
> + }
> +
> + if (v & NVM_LVDERR) {
> + printf("Error in Block Erase - low-vol detected!\n");
> + flash_initiate_operation(NVMOP_NOP);
> + return ERR_NOT_ERASED;
> + }
> +
> + /* disable flash write or erase operation */
> + writel(NVM_WREN, &nvm_regs_p->ctrl.clr);
> +
> + return ERR_OK;
> +}
> +
> +int flash_erase(flash_info_t *info, int s_first, int s_last)
> +{
> + ulong sect_start, sect_end, flags;
> + int prot, sect;
> + int rc;
> +
> + if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_MCHP) {
> + printf("Can't erase unknown flash type %08lx - aborted\n",
> + info->flash_id);
> + return ERR_UNKNOWN_FLASH_VENDOR;
> + }
> +
> + if ((s_first < 0) || (s_first > s_last)) {
> + printf("- no sectors to erase\n");
> + return ERR_INVAL;
>
Re: [U-Boot] [PATCH] drivers: mtd: add Microchip PIC32 internal non-CFI flash driver.
On 03/10/2016 07:11 PM, Jagan Teki wrote: > On Thursday 10 March 2016 06:42 PM, Purna Chandra Mandal wrote: >> PIC32 embedded flash banks are memory mapped, directly read by CPU, >> and programming (erase followed by write) operation on them are >> handled by on-chip NVM controller. > > Can you please add some more description to understand bit more, which kind > of flash it is, parallel NOR? > Jagan, These are parallel NOR flash divided into number of banks to allow erase/programming in one while fetch/execution continues from other. As the flash is memory-mapped code stored can be directly executed from flash (XIP), also there is additional hardware logic to prefetch and cache contents to improve code execution. These flash can also be used to store user data. In PIC32 there are two sets of embedded flash memory of same type - boot flash, and program flash; early-boot-code executes from boot-flash and one bank of program-flash is used for u-boot, other bank for environment. > thanks! > -- > Jagan. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] drivers: mtd: add Microchip PIC32 internal non-CFI flash driver.
On Thursday 10 March 2016 06:42 PM, Purna Chandra Mandal wrote: PIC32 embedded flash banks are memory mapped, directly read by CPU, and programming (erase followed by write) operation on them are handled by on-chip NVM controller. Can you please add some more description to understand bit more, which kind of flash it is, parallel NOR? thanks! -- Jagan. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
