Hi Felix,
On Sunday 27 September 2009 23:56:12 Felix Radensky wrote:
> Reorganize DDR2 ECC handling to use common code for
> SPD DIMMs and soldered SDRAM. Also, use common code
> to display SDRAM info (ECC, CAS latency) for SPD and
> soldered SDRAM variants.
Thanks. This is a first step into consolidation of the PPC4xx ECC handling.
You didn't include the DDR (non-DDR2) ECC handling though. My understanding
was that this should be done as well. I tried to merge this stuff today and
I'll send a patch for this DDR & DDR2 ECC handling merge soon.
Some other minor issues with this patch.
I do get this compilation warning:
Configuring for kilauea board...
44x_spd_ddr2.c:102: warning: 'wait_ddr_idle' defined but not used
44x_spd_ddr2.c:114: warning: 'sdram_memsize' defined but not used
textdata bss dec hex filename
286528 20680 46556 353764 565e4 ./u-boot
Additionally the patch has some whitespace problems:
[ste...@stefan-desktop u-boot-ppc4xx (4xx-ecc)]$ git am -s
patches_misc/\[PATCH\]\ ppc4xx\:\ Reorganize\ DDR2\ ECC\ handling.mbox
Applying: ppc4xx: Reorganize DDR2 ECC handling
/home/stefan/git/u-boot/u-boot-ppc4xx/.git/rebase-apply/patch:77: trailing
whitespace.
#endif
/home/stefan/git/u-boot/u-boot-ppc4xx/.git/rebase-apply/patch:137: trailing
whitespace.
#if defined(CONFIG_440)
warning: 2 lines applied after fixing whitespace errors.
No need to clean this up. I already silenced the warnings in my addon patch.
Thanks.
Cheers,
Stefan
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: off...@denx.de
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot