Re: [U-Boot] [PATCH 05/10] arm: socfpga: arria10: Added support for Arria 10 SoC dev kit

[Marek Vasut]

On 12/09/2016 10:55 AM, Chee, Tien Fong wrote:
> On Rab, 2016-12-07 at 14:57 +0100, Marek Vasut wrote:
>> On 12/07/2016 12:21 PM, Chee, Tien Fong wrote:
>>>
>>> On Sel, 2016-12-06 at 13:51 +0100, Marek Vasut wrote:

 On 12/06/2016 09:07 AM, Chee Tien Fong wrote:
>
>
> From: Tien Fong Chee 
>
> Signed-off-by: Tien Fong Chee 
> Cc: Marek Vasut 
> Cc: Dinh Nguyen 
> Cc: Chin Liang See 
> Cc: Tien Fong 
> ---
>  arch/arm/mach-socfpga/include/mach/base_addr_a10.h |   11 +-
>  arch/arm/mach-socfpga/system_manager.c |4 +-
>  drivers/fpga/socfpga.c |7 +-
>  include/configs/socfpga_arria10_socdk.h|  152
> +--
>  4 files changed, 151 insertions(+), 23 deletions(-)
>
> diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> index 902c321..487a5dc 100644
> --- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> +++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> @@ -1,7 +1,7 @@
>  /*
> - * Copyright (C) 2014 Altera Corporation 
> + * Copyright (C) 2014-2016 Altera Corporation 
>   *
> - * SPDX-License-Identifier:  GPL-2.0+
> + * SPDX-License-Identifier:  GPL-2.0
 Can you change license this way ?

>>> Okay, i will revert this change. I discussed with Chin Liang today,
>>> and
>>> we decided to let owner to make the changes. How about the year
>>> change
>>> 2014-2016?
>> To change a license of a file, you need to get an ACK from every
>> single
>> contributor to that file.
>>
>> Year change I believe is fine.
>>
>> [...]
>>
> Okay, noted.
>>>

>
> @@ -89,6 +120,95 @@
>   " root=${qspiroot} rw
> rootfstype=${qspirootfstype};"\
>   "bootm ${loadaddr} - ${fdt_addr}\0"
>  
> -/* The rest of the configuration is shared */
> -#include 
> +/*
> + * External memory configurations
> + */
 Why is this being duplicated in board support code when it
 previously
 was in common code ? That's just wrong.

>>> I found that many conflicts between the board support code and
>>> common
>>> code. It is safe for Arria10 having its own setting here. What do
>>> you
>>> think?
>> It looks like 95% of the stuff below is the same as the stuff in
>> socfpga-common.h , the rest can be pulled from DT or ifdef'd .
>>
> If socfpga-common.h is preferred, then i have to use ifdef method, are
> you ok with this? However, this would look a bit messy, because some
> #define setting in here, and other #define setting in socfpga-common.h
> under same category or peripheral configuration group.

Looks like there are only about two or three differences between the
stuff below and socfpga_common.h , so just put it into common , it
should be OK.


>
> +#define PHYS_SDRAM_1   0x0
> +#define PHYS_SDRAM_1_SIZE  0x8000
> +#define CONFIG_SYS_SDRAM_BASE  0
> +#define CONFIG_NR_DRAM_BANKS   1
> +#define CONFIG_SYS_MEMTEST_START   0
> +#define CONFIG_SYS_MEMTEST_END 0x10
> +
> +/*
> + * Serial / UART configurations
> + */
> +#define CONFIG_SYS_NS16550_SERIAL
> +#define CONFIG_SYS_NS16550_MEM32
> +#define CONFIG_SYS_NS16550_REG_SIZE-4
> +#define CONFIG_SYS_NS16550_COM1SOCFPGA_UART1_ADDRESS
> +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400,
> 57600, 115200}
> +#define CONFIG_SYS_NS16550_CLK (5000)
> +#define CONFIG_CONS_INDEX  1
> +#define CONFIG_BAUDRATE115200
> +
> +/*
> + * L4 OSC1 Timer 0
> + */
> +/* This timer use eosc1 where the clock frequency is fixed
> + * throughout any condition */
> +#define CONFIG_SYS_TIMERBASE SOCFPGA_SYSTIMER0_
> ADDR
> ESS
> +/* address of timer counter value */
> +#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE
> +
> 0x4)
> +/* reload value when timer count to zero */
> +#define TIMER_LOAD_VAL   0x
> +/* Clocks source frequency to timer */
> +#define CONFIG_SYS_TIMER_RATE(2500)
> +
> +/* DesignWare timer is a countdown timer */
> +#define CONFIG_SYS_TIMER_COUNTS_DOWN
> +
> +/*
> + * L4 Watchdog configurations
> + */
> +#ifdef CONFIG_HW_WATCHDOG
> +#define CONFIG_DESIGNWARE_WATCHDOG
> +#define CONFIG_DW_WDT_BASE   SOCFPGA_L4WD0_ADDRES
> S
> +#define CONFIG_HPS_CLK_OSC1_HZ   2500
> +#define CONFIG_DW_WDT_CLOCK_KHZ  (CONFIG_HPS_CLK
> _OSC
> 1_HZ / 1000)
> +#define CONFIG_HW_WATCHDOG_TIMEOUT_MS(2000)
> +#endif

Re: [U-Boot] [PATCH 05/10] arm: socfpga: arria10: Added support for Arria 10 SoC dev kit

[Chee, Tien Fong]

On Rab, 2016-12-07 at 14:57 +0100, Marek Vasut wrote:
> On 12/07/2016 12:21 PM, Chee, Tien Fong wrote:
> > 
> > On Sel, 2016-12-06 at 13:51 +0100, Marek Vasut wrote:
> > > 
> > > On 12/06/2016 09:07 AM, Chee Tien Fong wrote:
> > > > 
> > > > 
> > > > From: Tien Fong Chee 
> > > > 
> > > > Signed-off-by: Tien Fong Chee 
> > > > Cc: Marek Vasut 
> > > > Cc: Dinh Nguyen 
> > > > Cc: Chin Liang See 
> > > > Cc: Tien Fong 
> > > > ---
> > > >  arch/arm/mach-socfpga/include/mach/base_addr_a10.h |   11 +-
> > > >  arch/arm/mach-socfpga/system_manager.c |4 +-
> > > >  drivers/fpga/socfpga.c |7 +-
> > > >  include/configs/socfpga_arria10_socdk.h|  152
> > > > +--
> > > >  4 files changed, 151 insertions(+), 23 deletions(-)
> > > > 
> > > > diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> > > > b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> > > > index 902c321..487a5dc 100644
> > > > --- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> > > > +++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> > > > @@ -1,7 +1,7 @@
> > > >  /*
> > > > - * Copyright (C) 2014 Altera Corporation 
> > > > + * Copyright (C) 2014-2016 Altera Corporation 
> > > >   *
> > > > - * SPDX-License-Identifier:GPL-2.0+
> > > > + * SPDX-License-Identifier:GPL-2.0
> > > Can you change license this way ?
> > > 
> > Okay, i will revert this change. I discussed with Chin Liang today,
> > and
> > we decided to let owner to make the changes. How about the year
> > change
> > 2014-2016?
> To change a license of a file, you need to get an ACK from every
> single
> contributor to that file.
> 
> Year change I believe is fine.
> 
> [...]
> 
Okay, noted.
> > 
> > > 
> > > > 
> > > > @@ -89,6 +120,95 @@
> > > >     " root=${qspiroot} rw
> > > > rootfstype=${qspirootfstype};"\
> > > >     "bootm ${loadaddr} - ${fdt_addr}\0"
> > > >  
> > > > -/* The rest of the configuration is shared */
> > > > -#include 
> > > > +/*
> > > > + * External memory configurations
> > > > + */
> > > Why is this being duplicated in board support code when it
> > > previously
> > > was in common code ? That's just wrong.
> > > 
> > I found that many conflicts between the board support code and
> > common
> > code. It is safe for Arria10 having its own setting here. What do
> > you
> > think?
> It looks like 95% of the stuff below is the same as the stuff in
> socfpga-common.h , the rest can be pulled from DT or ifdef'd .
> 
If socfpga-common.h is preferred, then i have to use ifdef method, are
you ok with this? However, this would look a bit messy, because some
#define setting in here, and other #define setting in socfpga-common.h
under same category or peripheral configuration group.
> > 
> > > 
> > > > 
> > > > +#define PHYS_SDRAM_1   0x0
> > > > +#define PHYS_SDRAM_1_SIZE  0x8000
> > > > +#define CONFIG_SYS_SDRAM_BASE  0
> > > > +#define CONFIG_NR_DRAM_BANKS   1
> > > > +#define CONFIG_SYS_MEMTEST_START   0
> > > > +#define CONFIG_SYS_MEMTEST_END 0x10
> > > > +
> > > > +/*
> > > > + * Serial / UART configurations
> > > > + */
> > > > +#define CONFIG_SYS_NS16550_SERIAL
> > > > +#define CONFIG_SYS_NS16550_MEM32
> > > > +#define CONFIG_SYS_NS16550_REG_SIZE-4
> > > > +#define CONFIG_SYS_NS16550_COM1SOCFPGA_UART1_ADDRESS
> > > > +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400,
> > > > 57600, 115200}
> > > > +#define CONFIG_SYS_NS16550_CLK (5000)
> > > > +#define CONFIG_CONS_INDEX  1
> > > > +#define CONFIG_BAUDRATE115200
> > > > +
> > > > +/*
> > > > + * L4 OSC1 Timer 0
> > > > + */
> > > > +/* This timer use eosc1 where the clock frequency is fixed
> > > > + * throughout any condition */
> > > > +#define CONFIG_SYS_TIMERBASE   SOCFPGA_SYSTIMER0_
> > > > ADDR
> > > > ESS
> > > > +/* address of timer counter value */
> > > > +#define CONFIG_SYS_TIMER_COUNTER   (CONFIG_SYS_TIMERBASE
> > > > +
> > > > 0x4)
> > > > +/* reload value when timer count to zero */
> > > > +#define TIMER_LOAD_VAL 0x
> > > > +/* Clocks source frequency to timer */
> > > > +#define CONFIG_SYS_TIMER_RATE  (2500)
> > > > +
> > > > +/* DesignWare timer is a countdown timer */
> > > > +#define CONFIG_SYS_TIMER_COUNTS_DOWN
> > > > +
> > > > +/*
> > > > + * L4 Watchdog configurations
> > > > + */
> > > > +#ifdef CONFIG_HW_WATCHDOG
> > > > +#define CONFIG_DESIGNWARE_WATCHDOG
> > > > +#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRES
> > > > S
> > > > +#define CONFIG_HPS_CLK_OSC1_HZ 2500
> > > > +#define CONFIG_DW_WDT_CLOCK_KHZ(CONFIG_HPS_CLK
> > > > _OSC
> > > > 1_HZ / 1000)
> > > > +#define CONFIG_HW_WATCHDOG_TIMEOUT_MS  (2000)
> > > > 

Re: [U-Boot] [PATCH 05/10] arm: socfpga: arria10: Added support for Arria 10 SoC dev kit

[Marek Vasut]

On 12/07/2016 12:21 PM, Chee, Tien Fong wrote:
> On Sel, 2016-12-06 at 13:51 +0100, Marek Vasut wrote:
>> On 12/06/2016 09:07 AM, Chee Tien Fong wrote:
>>>
>>> From: Tien Fong Chee 
>>>
>>> Signed-off-by: Tien Fong Chee 
>>> Cc: Marek Vasut 
>>> Cc: Dinh Nguyen 
>>> Cc: Chin Liang See 
>>> Cc: Tien Fong 
>>> ---
>>>  arch/arm/mach-socfpga/include/mach/base_addr_a10.h |   11 +-
>>>  arch/arm/mach-socfpga/system_manager.c |4 +-
>>>  drivers/fpga/socfpga.c |7 +-
>>>  include/configs/socfpga_arria10_socdk.h|  152
>>> +--
>>>  4 files changed, 151 insertions(+), 23 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
>>> b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
>>> index 902c321..487a5dc 100644
>>> --- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
>>> +++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
>>> @@ -1,7 +1,7 @@
>>>  /*
>>> - * Copyright (C) 2014 Altera Corporation 
>>> + * Copyright (C) 2014-2016 Altera Corporation 
>>>   *
>>> - * SPDX-License-Identifier:GPL-2.0+
>>> + * SPDX-License-Identifier:GPL-2.0
>> Can you change license this way ?
>>
> Okay, i will revert this change. I discussed with Chin Liang today, and
> we decided to let owner to make the changes. How about the year change
> 2014-2016?

To change a license of a file, you need to get an ACK from every single
contributor to that file.

Year change I believe is fine.

[...]

>>> @@ -89,6 +120,95 @@
>>> " root=${qspiroot} rw
>>> rootfstype=${qspirootfstype};"\
>>> "bootm ${loadaddr} - ${fdt_addr}\0"
>>>  
>>> -/* The rest of the configuration is shared */
>>> -#include 
>>> +/*
>>> + * External memory configurations
>>> + */
>> Why is this being duplicated in board support code when it previously
>> was in common code ? That's just wrong.
>>
> I found that many conflicts between the board support code and common
> code. It is safe for Arria10 having its own setting here. What do you
> think?

It looks like 95% of the stuff below is the same as the stuff in
socfpga-common.h , the rest can be pulled from DT or ifdef'd .

>>> +#define PHYS_SDRAM_1   0x0
>>> +#define PHYS_SDRAM_1_SIZE  0x8000
>>> +#define CONFIG_SYS_SDRAM_BASE  0
>>> +#define CONFIG_NR_DRAM_BANKS   1
>>> +#define CONFIG_SYS_MEMTEST_START   0
>>> +#define CONFIG_SYS_MEMTEST_END 0x10
>>> +
>>> +/*
>>> + * Serial / UART configurations
>>> + */
>>> +#define CONFIG_SYS_NS16550_SERIAL
>>> +#define CONFIG_SYS_NS16550_MEM32
>>> +#define CONFIG_SYS_NS16550_REG_SIZE-4
>>> +#define CONFIG_SYS_NS16550_COM1SOCFPGA_UART1_ADDRESS
>>> +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400,
>>> 57600, 115200}
>>> +#define CONFIG_SYS_NS16550_CLK (5000)
>>> +#define CONFIG_CONS_INDEX  1
>>> +#define CONFIG_BAUDRATE115200
>>> +
>>> +/*
>>> + * L4 OSC1 Timer 0
>>> + */
>>> +/* This timer use eosc1 where the clock frequency is fixed
>>> + * throughout any condition */
>>> +#define CONFIG_SYS_TIMERBASE   SOCFPGA_SYSTIMER0_ADDR
>>> ESS
>>> +/* address of timer counter value */
>>> +#define CONFIG_SYS_TIMER_COUNTER   (CONFIG_SYS_TIMERBASE +
>>> 0x4)
>>> +/* reload value when timer count to zero */
>>> +#define TIMER_LOAD_VAL 0x
>>> +/* Clocks source frequency to timer */
>>> +#define CONFIG_SYS_TIMER_RATE  (2500)
>>> +
>>> +/* DesignWare timer is a countdown timer */
>>> +#define CONFIG_SYS_TIMER_COUNTS_DOWN
>>> +
>>> +/*
>>> + * L4 Watchdog configurations
>>> + */
>>> +#ifdef CONFIG_HW_WATCHDOG
>>> +#define CONFIG_DESIGNWARE_WATCHDOG
>>> +#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
>>> +#define CONFIG_HPS_CLK_OSC1_HZ 2500
>>> +#define CONFIG_DW_WDT_CLOCK_KHZ(CONFIG_HPS_CLK_OSC
>>> 1_HZ / 1000)
>>> +#define CONFIG_HW_WATCHDOG_TIMEOUT_MS  (2000)
>>> +#endif
>>> +
>>> +/*
>>> + * SDMMC configurations
>>> + */
>>> +#ifdef CONFIG_CMD_MMC
>>> +#define CONFIG_MMC
>>> +#define CONFIG_BOUNCE_BUFFER
>>> +#define CONFIG_GENERIC_MMC
>>> +#define CONFIG_DWMMC
>>> +#define CONFIG_SOCFPGA_DWMMC
>>> +#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH1024
>>> +#define CONFIG_SYS_MMC_MAX_BLK_COUNT   256
>>> +#endif
>>> +
>>> +/*
>>> + * Flash configurations
>>> + */
>>> +#define CONFIG_SYS_MAX_FLASH_BANKS 1
>>> +#define CONFIG_SYS_NO_FLASH
>>> +
>>> +/* SPL configuration */
>>> +#define CONFIG_SPL_FRAMEWORK
>>> +#define CONFIG_SPL_RAM_DEVICE
>>> +#define CONFIG_SPL_TEXT_BASE   CONFIG_SYS_INIT_RAM_AD
>>> DR
>>> +#define CONFIG_SPL_MAX_SIZECONFIG_SYS_INIT
>>> _RAM_SIZE
>>> +
>>> +#ifdef CONFIG_SPL_BUILD
>>> +#define CONFIG_SYS_MALLOC_SIMPLE
>>> +#endif
>>> +
>>> 

Re: [U-Boot] [PATCH 05/10] arm: socfpga: arria10: Added support for Arria 10 SoC dev kit

[Chee, Tien Fong]

On Sel, 2016-12-06 at 13:51 +0100, Marek Vasut wrote:
> On 12/06/2016 09:07 AM, Chee Tien Fong wrote:
> > 
> > From: Tien Fong Chee 
> > 
> > Signed-off-by: Tien Fong Chee 
> > Cc: Marek Vasut 
> > Cc: Dinh Nguyen 
> > Cc: Chin Liang See 
> > Cc: Tien Fong 
> > ---
> >  arch/arm/mach-socfpga/include/mach/base_addr_a10.h |   11 +-
> >  arch/arm/mach-socfpga/system_manager.c |4 +-
> >  drivers/fpga/socfpga.c |7 +-
> >  include/configs/socfpga_arria10_socdk.h|  152
> > +--
> >  4 files changed, 151 insertions(+), 23 deletions(-)
> > 
> > diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> > b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> > index 902c321..487a5dc 100644
> > --- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> > +++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> > @@ -1,7 +1,7 @@
> >  /*
> > - * Copyright (C) 2014 Altera Corporation 
> > + * Copyright (C) 2014-2016 Altera Corporation 
> >   *
> > - * SPDX-License-Identifier:GPL-2.0+
> > + * SPDX-License-Identifier:GPL-2.0
> Can you change license this way ?
> 
Okay, i will revert this change. I discussed with Chin Liang today, and
we decided to let owner to make the changes. How about the year change
2014-2016?
> > 
> >   */
> >  
> >  #ifndef _SOCFPGA_A10_BASE_HARDWARE_H_
> > @@ -35,11 +35,14 @@
> >  
> >  #define SOCFPGA_ECC_OCRAM_ADDRESS  0xff8c3000
> >  #define SOCFPGA_UART0_ADDRESS  0xffc02000
> > -#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd0
> > +#define SOCFPGA_SYSTIMER0_ADDRESS  0xffd0
> > +#define SOCFPGA_SYSTIMER1_ADDRESS  0xffd00100
> >  #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
> >  #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
> This should be in a separate patch.
> 
> > 
> > -#define SOCFPGA_SDR_ADDRESS0xffcfb000
> > +#define SOCFPGA_SDR_ADDRESS
> > 0xffcfb000
> > +#define SOCFPGA_NOC_L4_PRIV_FLT_OFST0xffd11000
> > +#define SOCFPGA_NOC_FW_H2F_SCR_OFST0xffd13
> > 500
> >  #define SOCFPGA_SDR_SCHEDULER_ADDRESS  0xffd12400
> >  #define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS 0xffd13200
> >  #define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS  0xffd13300
> > diff --git a/arch/arm/mach-socfpga/system_manager.c
> > b/arch/arm/mach-socfpga/system_manager.c
> > index 9e1c3fd..e1f0082 100644
> > --- a/arch/arm/mach-socfpga/system_manager.c
> > +++ b/arch/arm/mach-socfpga/system_manager.c
> This should also be in a separate patch, don't go hacking common code
> in
> board-support patch.
> 
Okay, i will move these changes to separate patch. Those removed
#define is no longer valid.
> > 
> > @@ -1,5 +1,5 @@
> >  /*
> > - * Copyright (C) 2013 Altera Corporation 
> > + * Copyright (C) 2013-2016 Altera Corporation 
> >   *
> >   * SPDX-License-Identifier:GPL-2.0+
> >   */
> > @@ -11,8 +11,10 @@
> >  
> >  DECLARE_GLOBAL_DATA_PTR;
> >  
> > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> >  static struct socfpga_system_manager *sysmgr_regs =
> >     (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> > +#endif
> >  
> >  /*
> >   * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux
> > setting.
> > diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
> > index bfefafd..7fd922e 100644
> > --- a/drivers/fpga/socfpga.c
> > +++ b/drivers/fpga/socfpga.c
> > @@ -1,5 +1,5 @@
> >  /*
> > - * Copyright (C) 2012 Altera Corporation 
> > + * Copyright (C) 2012-2016 Altera Corporation 
> >   * All rights reserved.
> >   *
> >   * SPDX-License-Identifier:BSD-3-Clause
> > @@ -19,8 +19,10 @@ DECLARE_GLOBAL_DATA_PTR;
> >  
> >  static struct socfpga_fpga_manager *fpgamgr_regs =
> >     (struct socfpga_fpga_manager
> > *)SOCFPGA_FPGAMGRREGS_ADDRESS;
> > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> >  static struct socfpga_system_manager *sysmgr_regs =
> >     (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> > +#endif
> >  
> >  /* Set CD ratio */
> >  static void fpgamgr_set_cd_ratio(unsigned long ratio)
> > @@ -267,9 +269,10 @@ int socfpga_load(Altera_desc *desc, const void
> > *rbf_data, size_t rbf_size)
> >     }
> >  
> >     /* Prior programming the FPGA, all bridges need to be shut
> > off */
> > -
> > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> >     /* Disable all signals from hps peripheral controller to
> > fpga */
> >     writel(0, _regs->fpgaintfgrp_module);
> > +#endif
> >  
> >     /* Disable all signals from FPGA to HPS SDRAM */
> >  #define SDR_CTRLGRP_FPGAPORTRST_ADDRESS0x5080
> > diff --git a/include/configs/socfpga_arria10_socdk.h
> > b/include/configs/socfpga_arria10_socdk.h
> > index 577f60f..15c7a28 100644
> > --- 

Re: [U-Boot] [PATCH 05/10] arm: socfpga: arria10: Added support for Arria 10 SoC dev kit

[Marek Vasut]

On 12/06/2016 09:07 AM, Chee Tien Fong wrote:
> From: Tien Fong Chee 
> 
> Signed-off-by: Tien Fong Chee 
> Cc: Marek Vasut 
> Cc: Dinh Nguyen 
> Cc: Chin Liang See 
> Cc: Tien Fong 
> ---
>  arch/arm/mach-socfpga/include/mach/base_addr_a10.h |   11 +-
>  arch/arm/mach-socfpga/system_manager.c |4 +-
>  drivers/fpga/socfpga.c |7 +-
>  include/configs/socfpga_arria10_socdk.h|  152 +--
>  4 files changed, 151 insertions(+), 23 deletions(-)
> 
> diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h 
> b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> index 902c321..487a5dc 100644
> --- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> +++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> @@ -1,7 +1,7 @@
>  /*
> - * Copyright (C) 2014 Altera Corporation 
> + * Copyright (C) 2014-2016 Altera Corporation 
>   *
> - * SPDX-License-Identifier:  GPL-2.0+
> + * SPDX-License-Identifier:  GPL-2.0

Can you change license this way ?

>   */
>  
>  #ifndef _SOCFPGA_A10_BASE_HARDWARE_H_
> @@ -35,11 +35,14 @@
>  
>  #define SOCFPGA_ECC_OCRAM_ADDRESS0xff8c3000
>  #define SOCFPGA_UART0_ADDRESS0xffc02000
> -#define SOCFPGA_OSC1TIMER0_ADDRESS   0xffd0
> +#define SOCFPGA_SYSTIMER0_ADDRESS0xffd0
> +#define SOCFPGA_SYSTIMER1_ADDRESS0xffd00100
>  #define SOCFPGA_CLKMGR_ADDRESS   0xffd04000
>  #define SOCFPGA_RSTMGR_ADDRESS   0xffd05000

This should be in a separate patch.

> -#define SOCFPGA_SDR_ADDRESS  0xffcfb000
> +#define SOCFPGA_SDR_ADDRESS  0xffcfb000
> +#define SOCFPGA_NOC_L4_PRIV_FLT_OFST0xffd11000
> +#define SOCFPGA_NOC_FW_H2F_SCR_OFST  0xffd13500
>  #define SOCFPGA_SDR_SCHEDULER_ADDRESS0xffd12400
>  #define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS   0xffd13200
>  #define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS0xffd13300
> diff --git a/arch/arm/mach-socfpga/system_manager.c 
> b/arch/arm/mach-socfpga/system_manager.c
> index 9e1c3fd..e1f0082 100644
> --- a/arch/arm/mach-socfpga/system_manager.c
> +++ b/arch/arm/mach-socfpga/system_manager.c

This should also be in a separate patch, don't go hacking common code in
board-support patch.

> @@ -1,5 +1,5 @@
>  /*
> - * Copyright (C) 2013 Altera Corporation 
> + * Copyright (C) 2013-2016 Altera Corporation 
>   *
>   * SPDX-License-Identifier:  GPL-2.0+
>   */
> @@ -11,8 +11,10 @@
>  
>  DECLARE_GLOBAL_DATA_PTR;
>  
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>  static struct socfpga_system_manager *sysmgr_regs =
>   (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> +#endif
>  
>  /*
>   * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting.
> diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
> index bfefafd..7fd922e 100644
> --- a/drivers/fpga/socfpga.c
> +++ b/drivers/fpga/socfpga.c
> @@ -1,5 +1,5 @@
>  /*
> - * Copyright (C) 2012 Altera Corporation 
> + * Copyright (C) 2012-2016 Altera Corporation 
>   * All rights reserved.
>   *
>   * SPDX-License-Identifier:  BSD-3-Clause
> @@ -19,8 +19,10 @@ DECLARE_GLOBAL_DATA_PTR;
>  
>  static struct socfpga_fpga_manager *fpgamgr_regs =
>   (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>  static struct socfpga_system_manager *sysmgr_regs =
>   (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> +#endif
>  
>  /* Set CD ratio */
>  static void fpgamgr_set_cd_ratio(unsigned long ratio)
> @@ -267,9 +269,10 @@ int socfpga_load(Altera_desc *desc, const void 
> *rbf_data, size_t rbf_size)
>   }
>  
>   /* Prior programming the FPGA, all bridges need to be shut off */
> -
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>   /* Disable all signals from hps peripheral controller to fpga */
>   writel(0, _regs->fpgaintfgrp_module);
> +#endif
>  
>   /* Disable all signals from FPGA to HPS SDRAM */
>  #define SDR_CTRLGRP_FPGAPORTRST_ADDRESS  0x5080
> diff --git a/include/configs/socfpga_arria10_socdk.h 
> b/include/configs/socfpga_arria10_socdk.h
> index 577f60f..15c7a28 100644
> --- a/include/configs/socfpga_arria10_socdk.h
> +++ b/include/configs/socfpga_arria10_socdk.h
> @@ -1,5 +1,5 @@
>  /*
> - *  Copyright (C) 2015 Altera Corporation 
> + *  Copyright (C) 2015-2016 Altera Corporation 
>   *
>   * SPDX-License-Identifier:  GPL-2.0
>   */
> @@ -16,36 +16,67 @@
>  
>  #define CONFIG_CMD_ASKENV
>  #define CONFIG_CMD_BOOTZ
> -#define CONFIG_CMD_CACHE
> -#define CONFIG_CMD_DHCP
>  #define CONFIG_CMD_EXT4
>  #define CONFIG_CMD_EXT4_WRITE
> -#define CONFIG_CMD_FAT
> -#define CONFIG_CMD_FS_GENERIC
>  #define CONFIG_CMD_GREPENV
> -#define CONFIG_CMD_MMC
>  #define CONFIG_CMD_PING
>  
>