On Mon, Oct 9, 2017 at 4:11 AM, Calvin Johnson wrote:
> This patch adds PFE driver into U-Boot.
>
> Following are the main driver files:-
> pfe.c: provides low level helper functions to initialize PFE internal
> processor engines and other hardware blocks.
> pfe_driver.c: provides probe functions, initialization functions
> and packet send and receive functions.
> pfe_eth.c: provides high level gemac, phy and mdio initialization
> functions.
> pfe_firmware.c: provides functions to load firmware into PFE
> internal processor engines.
>
> Signed-off-by: Calvin Johnson
> Signed-off-by: Anjaneyulu Jagarlmudi
> ---
> drivers/net/pfe_eth/Kconfig|8 +
> drivers/net/pfe_eth/Makefile | 10 +
> drivers/net/pfe_eth/pfe.c | 1161
>
> drivers/net/pfe_eth/pfe_driver.c | 626 +++
> drivers/net/pfe_eth/pfe_eth.c | 545 +
> drivers/net/pfe_eth/pfe_firmware.c | 230 +++
> 6 files changed, 2580 insertions(+)
> create mode 100644 drivers/net/pfe_eth/Kconfig
> create mode 100644 drivers/net/pfe_eth/Makefile
> create mode 100644 drivers/net/pfe_eth/pfe.c
> create mode 100644 drivers/net/pfe_eth/pfe_driver.c
> create mode 100644 drivers/net/pfe_eth/pfe_eth.c
> create mode 100644 drivers/net/pfe_eth/pfe_firmware.c
>
> diff --git a/drivers/net/pfe_eth/Kconfig b/drivers/net/pfe_eth/Kconfig
> new file mode 100644
> index 000..b9996df
> --- /dev/null
> +++ b/drivers/net/pfe_eth/Kconfig
> @@ -0,0 +1,8 @@
> +config UTIL_PE_DISABLED
> + bool
> + help
> + Disable UTIL processor engine of PFE
> +
> +config SYS_FSL_PPFE_ADDR
> + hex "PFE base address"
> + default 0x0400
> diff --git a/drivers/net/pfe_eth/Makefile b/drivers/net/pfe_eth/Makefile
> new file mode 100644
> index 000..e78f1bf
> --- /dev/null
> +++ b/drivers/net/pfe_eth/Makefile
> @@ -0,0 +1,10 @@
> +# Copyright 2015-2016 Freescale Semiconductor, Inc.
> +# Copyright 2017 NXP
> +#
> +# SPDX-License-Identifier:GPL-2.0+
> +
> +# Layerscape PFE driver
> +obj-y += pfe.o \
> +pfe_driver.o \
> +pfe_eth.o \
> +pfe_firmware.o
> diff --git a/drivers/net/pfe_eth/pfe.c b/drivers/net/pfe_eth/pfe.c
> new file mode 100644
> index 000..fc6631e
> --- /dev/null
> +++ b/drivers/net/pfe_eth/pfe.c
> @@ -0,0 +1,1161 @@
> +/*
> + * Copyright 2015-2016 Freescale Semiconductor, Inc.
> + * Copyright 2017 NXP
> + *
> + * SPDX-License-Identifier:GPL-2.0+
> + */
> +#include
> +#include
> +
> +void *ddr_base_addr;
> +unsigned long ddr_phys_base_addr;
> +static struct pe_info pe[MAX_PE];
> +
> +/*
> + * Initializes the PFE library.
> + * Must be called before using any of the library functions.
> + *
> + * @param[in] cbus_baseCBUS virtual base address (as mapped
> in
> + * the host CPU address space)
> + * @param[in] ddr_base DDR virtual base address (as mapped in
> + * the host CPU address space)
> + * @param[in] ddr_phys_baseDDR physical base address (as mapped in
> + * platform)
> + */
> +void pfe_lib_init(void *ddr_base, unsigned long ddr_phys_base)
Could you use some loops here to consolidate this code some?
> +{
> + ddr_base_addr = ddr_base;
> + ddr_phys_base_addr = ddr_phys_base;
> +
> + pe[CLASS0_ID].dmem_base_addr = (u32)CLASS_DMEM_BASE_ADDR(0);
> + pe[CLASS0_ID].pmem_base_addr = (u32)CLASS_IMEM_BASE_ADDR(0);
> + pe[CLASS0_ID].pmem_size = (u32)CLASS_IMEM_SIZE;
> + pe[CLASS0_ID].mem_access_wdata = (void *)CLASS_MEM_ACCESS_WDATA;
> + pe[CLASS0_ID].mem_access_addr = (void *)CLASS_MEM_ACCESS_ADDR;
> + pe[CLASS0_ID].mem_access_rdata = (void *)CLASS_MEM_ACCESS_RDATA;
> +
> + pe[CLASS1_ID].dmem_base_addr = (u32)CLASS_DMEM_BASE_ADDR(1);
> + pe[CLASS1_ID].pmem_base_addr = (u32)CLASS_IMEM_BASE_ADDR(1);
> + pe[CLASS1_ID].pmem_size = (u32)CLASS_IMEM_SIZE;
> + pe[CLASS1_ID].mem_access_wdata = (void *)CLASS_MEM_ACCESS_WDATA;
> + pe[CLASS1_ID].mem_access_addr = (void *)CLASS_MEM_ACCESS_ADDR;
> + pe[CLASS1_ID].mem_access_rdata = (void *)CLASS_MEM_ACCESS_RDATA;
> +
> + pe[CLASS2_ID].dmem_base_addr = (u32)CLASS_DMEM_BASE_ADDR(2);
> + pe[CLASS2_ID].pmem_base_addr = (u32)CLASS_IMEM_BASE_ADDR(2);
> + pe[CLASS2_ID].pmem_size = (u32)CLASS_IMEM_SIZE;
> + pe[CLASS2_ID].mem_access_wdata = (void *)CLASS_MEM_ACCESS_WDATA;
> + pe[CLASS2_ID].mem_access_addr = (void *)CLASS_MEM_ACCESS_ADDR;
> + pe[CLASS2_ID].mem_access_rdata = (void *)CLASS_MEM_ACCESS_RDATA;
> +
> + pe[CLASS3_ID].dmem_base_addr = (u32)CLASS_DMEM_BASE_ADDR(3);
> + pe[CLASS3_ID].pmem_base_addr = (u32)CLASS_IMEM_BASE_ADDR(3);
> + pe[CLASS3_ID].pmem_size = (u32)CLASS_IMEM_SIZE;
> + pe[CLASS3_ID].mem_access_wdata = (void *)CLASS_MEM_ACCESS_WDATA;
> + pe[CLASS3_ID].mem_access_addr = (void *)CLASS_MEM_AC
