Re: [U-Boot] [PATCH 2/3] MIPS: fix inconsistency in config option for cache operation mode
Mike, there was some issue with this patch? Commit ab2a98b11716364bc5a8c43cdfa7fee176cda1d8 missed to use the new config option in dcache_enable(). Fix this to avoid inconsistencies if someone wants to disable and enable D-caches. Signed-off-by: Daniel Schwierzeck daniel.schwierz...@googlemail.com --- arch/mips/cpu/mips32/cache.S |6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S index 5ce0ec4..e683e8b 100644 --- a/arch/mips/cpu/mips32/cache.S +++ b/arch/mips/cpu/mips32/cache.S @@ -30,6 +30,10 @@ #include asm/addrspace.h #include asm/cacheops.h +#ifndef CONFIG_SYS_MIPS_CACHE_MODE +#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT +#endif + #define RA t8 /* @@ -224,7 +228,7 @@ LEAF(dcache_enable) mfc0t0, CP0_CONFIG ori t0, CONF_CM_CMASK xorit0, CONF_CM_CMASK - ori t0, CONF_CM_CACHABLE_NONCOHERENT + ori t0, CONFIG_SYS_MIPS_CACHE_MODE mtc0t0, CP0_CONFIG jr ra END(dcache_enable) Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/3] MIPS: fix inconsistency in config option for cache operation mode
Hi, On Tue, Apr 3, 2012 at 3:40 PM, Marek Vasut ma...@denx.de wrote: Mike, there was some issue with this patch? Commit ab2a98b11716364bc5a8c43cdfa7fee176cda1d8 missed to use the new config option in dcache_enable(). this commit refers to a patch that I sent a while ago as preparation for supporting Lantiq SoCs. Some Lantiq SoCs wants CONF_CM_CACHABLE_NO_WA instead of the hard-coded CONF_CM_CACHABLE_NONCOHERENT. So I created a config option for the required cache mode. Fix this to avoid inconsistencies if someone wants to disable and enable D-caches. Signed-off-by: Daniel Schwierzeck daniel.schwierz...@googlemail.com --- arch/mips/cpu/mips32/cache.S | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S index 5ce0ec4..e683e8b 100644 --- a/arch/mips/cpu/mips32/cache.S +++ b/arch/mips/cpu/mips32/cache.S @@ -30,6 +30,10 @@ #include asm/addrspace.h #include asm/cacheops.h +#ifndef CONFIG_SYS_MIPS_CACHE_MODE +#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT +#endif + #define RA t8 /* @@ -224,7 +228,7 @@ LEAF(dcache_enable) mfc0 t0, CP0_CONFIG ori t0, CONF_CM_CMASK xori t0, CONF_CM_CMASK - ori t0, CONF_CM_CACHABLE_NONCOHERENT + ori t0, CONFIG_SYS_MIPS_CACHE_MODE mtc0 t0, CP0_CONFIG jr ra END(dcache_enable) Best regards, Marek Vasut I only changed start.S and forgot to change this code part too. That is why I created this patch to fix this inconsistency. -- Best regards, Daniel ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/3] MIPS: fix inconsistency in config option for cache operation mode
Dear Daniel Schwierzeck, Hi, On Tue, Apr 3, 2012 at 3:40 PM, Marek Vasut ma...@denx.de wrote: Mike, there was some issue with this patch? Commit ab2a98b11716364bc5a8c43cdfa7fee176cda1d8 missed to use the new config option in dcache_enable(). this commit refers to a patch that I sent a while ago as preparation for supporting Lantiq SoCs. Some Lantiq SoCs wants CONF_CM_CACHABLE_NO_WA instead of the hard-coded CONF_CM_CACHABLE_NONCOHERENT. So I created a config option for the required cache mode. Fix this to avoid inconsistencies if someone wants to disable and enable D-caches. Signed-off-by: Daniel Schwierzeck daniel.schwierz...@googlemail.com --- arch/mips/cpu/mips32/cache.S |6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S index 5ce0ec4..e683e8b 100644 --- a/arch/mips/cpu/mips32/cache.S +++ b/arch/mips/cpu/mips32/cache.S @@ -30,6 +30,10 @@ #include asm/addrspace.h #include asm/cacheops.h +#ifndef CONFIG_SYS_MIPS_CACHE_MODE +#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT +#endif + #define RA t8 /* @@ -224,7 +228,7 @@ LEAF(dcache_enable) mfc0t0, CP0_CONFIG ori t0, CONF_CM_CMASK xorit0, CONF_CM_CMASK - ori t0, CONF_CM_CACHABLE_NONCOHERENT + ori t0, CONFIG_SYS_MIPS_CACHE_MODE mtc0t0, CP0_CONFIG jr ra END(dcache_enable) Best regards, Marek Vasut I only changed start.S and forgot to change this code part too. That is why I created this patch to fix this inconsistency. I see ... so this fixes some other commit. What was Shinya-san's concern, that you only changed this file? Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/3] MIPS: fix inconsistency in config option for cache operation mode
On Tuesday 03 April 2012 09:40:08 Marek Vasut wrote: Mike, there was some issue with this patch? i had feedback on the endian flags last time Daniel posted it, but i don't think i ever gave feedback on this ... i certainly don't know mips asm beyond the extreme basics ;). was there a patchwork URL or mailing list archive for me to check ? -mike signature.asc Description: This is a digitally signed message part. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/3] MIPS: fix inconsistency in config option for cache operation mode
On Wed, Apr 4, 2012 at 1:09 AM, Marek Vasut ma...@denx.de wrote: I only changed start.S and forgot to change this code part too. That is why I created this patch to fix this inconsistency. I see ... so this fixes some other commit. What was Shinya-san's concern, that you only changed this file? On Wed, Apr 4, 2012 at 5:33 AM, Mike Frysinger vap...@gentoo.org wrote: On Tuesday 03 April 2012 09:40:08 Marek Vasut wrote: Mike, there was some issue with this patch? i had feedback on the endian flags last time Daniel posted it, but i don't think i ever gave feedback on this ... i certainly don't know mips asm beyond the extreme basics ;). Apologies for confusing, I intended to refer to PATCH 3/3, not 2/3. If everybody is Ok with 3/3 as-is, I'm fine. Shinya ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
