Re: [U-Boot] [PATCH 2/5] powerpc/85xx: Read board switch settings on p1_p2_rdb

2011-03-08 Thread McClintock Matthew-B29882 
On Sun, Mar 6, 2011 at 10:17 PM, Kumar Gala  wrote:
> +               if (i2c_data & 0x1) {
> +                       setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
> +                       puts("SD/MMC : 8-bit Mode\n");
> +                       puts("eSPI : Disabled\n");
> +               } else {
> +                       puts("SD/MMC : 4-bit Mode\n");
> +                       puts("eSPI : Enabled\n");

I think this bit is actually important for the p1_p2_rdb_pc boards
also? Is this handled by the CPLD somehow or do we need to do the same
thing?

'IO0 - "read-only" CFG_SDWIDTH SW2[1].

-M
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Re: [U-Boot] [PATCH 2/5] powerpc/85xx: Read board switch settings on p1_p2_rdb

2011-03-09 Thread Kumar Gala 

On Mar 9, 2011, at 12:38 AM, McClintock Matthew-B29882 wrote:

> On Sun, Mar 6, 2011 at 10:17 PM, Kumar Gala  wrote:
>> +   if (i2c_data & 0x1) {
>> +   setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
>> +   puts("SD/MMC : 8-bit Mode\n");
>> +   puts("eSPI : Disabled\n");
>> +   } else {
>> +   puts("SD/MMC : 4-bit Mode\n");
>> +   puts("eSPI : Enabled\n");
> 
> I think this bit is actually important for the p1_p2_rdb_pc boards
> also? Is this handled by the CPLD somehow or do we need to do the same
> thing?
> 
> 'IO0 - "read-only" CFG_SDWIDTH SW2[1].

the setting of pmuxcr?  SW has to do that.

- k
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Re: [U-Boot] [PATCH 2/5] powerpc/85xx: Read board switch settings on p1_p2_rdb

2011-03-09 Thread McClintock Matthew-B29882 
On Wed, Mar 9, 2011 at 9:36 AM, Kumar Gala  wrote:
> the setting of pmuxcr?  SW has to do that.
>

But we don't do this based off the switch value currently on
p1_p2_rdb_pc boards.

-M
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Re: [U-Boot] [PATCH 2/5] powerpc/85xx: Read board switch settings on p1_p2_rdb

2011-03-25 Thread Kumar Gala 

On Mar 6, 2011, at 10:17 PM, Kumar Gala wrote:

> From: Priyanka Jain 
> 
> PCA9557 is parallel I/O expansion device on I2C bus which stores various
> board switch settings like NOR Flash-Bank selection, SD Data width.
> 
> On board:
> switch SW5[6] is to select width for eSDHC
>ON  - 4-bit [Enable eSPI]
>OFF - 8-bit [Disable eSPI]
> 
> switch SW4[8] is to select NOR Flash Bank for Booting
>OFF - Primary Bank
>ON  - Secondary Bank
> 
> Read board switch settings on p1_p2_rdb and configure corresponding
> eSDHC width.
> 
> Signed-off-by: Priyanka Jain 
> Signed-off-by: Dipen Dudhat 
> Signed-off-by: Kumar Gala 
> ---
> board/freescale/p1_p2_rdb/p1_p2_rdb.c |   25 +
> include/configs/P1_P2_RDB.h   |2 ++
> 2 files changed, 27 insertions(+), 0 deletions(-)

applied to 85xx next

- k
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