On Sun, Oct 9, 2011 at 2:22 PM, Wolfgang Denk wrote:
> Dear Anton Staaf,
>
> In message <1317763491-7274-1-git-send-email-robot...@chromium.org> you wrote:
>> The cache line alignment issue has gone around a couple of times now. This
>> patch set implements all of the details that we have discussed about the
>> implementation of ALLOC_CACHE_ALIGN_BUFFER other than the switch to the Linux
>> style L1_CACHE_BYTES, L1_CACHE_SHIFT, and ARCH_DMA_MINALIGN defines mentioned
>> by Mike Frysinger. It also includes patches that use the macro to fix MMC
>> and ext2 buffers, as well as define the CONFIG_SYS_CACHELINE_SIZE value for
>> Tegra and add a default value for CONFIG_SYS_CACHELINE_SIZE with a warning if
>> it is used.
>>
>> About the Linux defines that Mike suggests. It may make sense to move these
>> patches over to use that mechanism, especially since there are only a few
>> configs that define CONFIG_SYS_CACHELINE_SIZE anyway. Also, since this is an
>> architecture specific parameter and not a board specific one it makes sense
>> that these configs would be architecture specific. I am also not supper
>> happy
>> with the fact that most boards generate a warning with this patchset, because
>> they don't set CONFIG_SYS_CACHELINE_SIZE. But I'm not sure that silently
>> providing a default is a good idea.
>>
>> I think we can discuss the relative merrits of that move independently of the
>> implementation of this fix though, and I wanted to get this discussion going
>> again.
>
> Sorry, but I'm going to back out all these patches from my tree again.
>
> I can;t get this to work.
>
> With the patches applied, I get all kinds of "#warning
> CONFIG_SYS_CACHELINE_SIZE not defined, using __BIGGEST_ALIGNMENT__"
> for Power Atchitecture systems (ppc4xx expecially).
>
> Stefan Roese provided the "ppc: Include in common.h" and
> "ppc: Fix DBSR_IAx defines in " to fix this on PPC, but
> now I see the same on ARM, like that:
>
> Configuring for jornada board...
> In file included from /home/wd/git/u-boot/work/lib/asm-offsets.c:18:0:
> /home/wd/git/u-boot/work/include/common.h:825:2: warning: #warning
> CONFIG_SYS_CACHELINE_SIZE not defined, using __BIGGEST_ALIGNMENT__ [-Wcpp]
> In file included from hello_world.c:24:0:
> /home/wd/git/u-boot/work/include/common.h:825:2: warning: #warning
> CONFIG_SYS_CACHELINE_SIZE not defined, using __BIGGEST_ALIGNMENT__ [-Wcpp]
> In file included from /home/wd/git/u-boot/work/include/exports.h:6:0,
> from stubs.c:1:
> /home/wd/git/u-boot/work/include/common.h:825:2: warning: #warning
> CONFIG_SYS_CACHELINE_SIZE not defined, using __BIGGEST_ALIGNMENT__ [-Wcpp]
> ^Carm-linux-gnueabi-size: '/work/wd/tmp-arm/u-boot': No such file
>
>
>
> Please fix, and resubmit. Please make sure to run MAKEALL not only
> for your boards, but for some architectures (say, ARM, MIPS and PPC).
Yup, I was surprised that it went in so quickly actually. I did point
out the warnings that would be generated. But perhaps I should have
been more clear about just how many would be generated. I'll look
into a solution. I am hoping that it won't be that I need to
understand the cache line sizes of all architectures and fix them all
to define CONFIG_SYS_CACHELINE_SIZE. :)
Thanks,
Anton
> Thanks.
>
> Best regards,
>
> Wolfgang Denk
>
> --
> DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
> "When anyone says `theoretically,' they really mean `not really.'"
> - David Parnas
>
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