Re: [U-Boot] [PATCH v3 08/14] MIPS: Add support for Microchip PIC32MZ[DA] SoC family.
On 01/13/2016 08:19 PM, Daniel Schwierzeck wrote:
> Am Dienstag, den 12.01.2016, 15:48 +0530 schrieb Purna Chandra Mandal:
>> Add Microchip PIC32MZ[DA] SoC family support.
>>
>> Signed-off-by: Purna Chandra Mandal
>>
>> ---
>>
>> Changes in v3:
>> - drop forcing CONFIG_MIPS_BOOT_* selection in mach-pic32/Kconfig
>> - indent assembly instructions in delay slot
>> - made GPIO-nodes child of pinctrl-node in devicetree
>> - replace pic32_ioremap() with ioremap()
>>
>> Changes in v2:
>> - drop board_early_init_f
>> - use macro LEAF(), END() for lowlevel_init assembly
>> - move initialization of board_init_f() argument to common start.S
>> - move initdram() from board/microchip/ to mach-pic32/cpu.c
>> - remove MIPS virtual address in favor physical one in dts file
>>
>> arch/mips/dts/pic32mzda.dtsi | 153
>> ++
>> arch/mips/mach-pic32/Kconfig | 20 +++-
>> arch/mips/mach-pic32/Makefile | 2 +-
>> arch/mips/mach-pic32/cpu.c| 147
>>
>> arch/mips/mach-pic32/include/mach/pic32.h | 3 +
>> arch/mips/mach-pic32/lowlevel_init.S | 27 ++
>> arch/mips/mach-pic32/reset.c | 36 +++
>> 7 files changed, 386 insertions(+), 2 deletions(-)
>> create mode 100644 arch/mips/dts/pic32mzda.dtsi
>> create mode 100644 arch/mips/mach-pic32/lowlevel_init.S
>> create mode 100644 arch/mips/mach-pic32/reset.c
>>
>> diff --git a/arch/mips/dts/pic32mzda.dtsi
>> b/arch/mips/dts/pic32mzda.dtsi
>> new file mode 100644
>> index 000..fe8b13a
>> --- /dev/null
>> +++ b/arch/mips/dts/pic32mzda.dtsi
>> @@ -0,0 +1,153 @@
>> +/*
>> + * Copyright 2015 Microchip Technology, Inc.
>> + * Purna Chandra Mandal,
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#include
>> +#include
>> +#include
>> +#include "skeleton.dtsi"
>> +
>> +/ {
>> +compatible = "microchip,pic32mzda", "microchip,pic32mz";
>> +
>> +aliases {
>> +gpio0 = &gpioA;
>> +gpio1 = &gpioB;
>> +gpio2 = &gpioC;
>> +gpio3 = &gpioD;
>> +gpio4 = &gpioE;
>> +gpio5 = &gpioF;
>> +gpio6 = &gpioG;
>> +gpio7 = &gpioH;
>> +gpio8 = &gpioJ;
>> +gpio9 = &gpioK;
>> +};
>> +
>> +cpus {
>> +cpu@0 {
>> +compatible = "mips,mips14kc";
>> +};
>> +};
>> +
>> +clock: clk@1f801200 {
>> +compatible = "microchip,pic32mzda_clk";
>> +reg = <0x1f801200 0x1000>;
>> +clock-cells = <1>;
>> +};
>> +
>> +uart1: serial@1f822000 {
>> +compatible = "microchip,pic32mzda-uart";
>> +reg = <0x1f822000 0x50>;
>> +interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
>> +status = "disabled";
>> +clocks = <&clock PB2CLK>;
>> +};
>> +
>> +uart2: serial@1f822200 {
>> +compatible = "microchip,pic32mzda-uart";
>> +reg = <0x1f822200 0x50>;
>> +interrupts = <145 IRQ_TYPE_LEVEL_HIGH>;
>> +clocks = <&clock PB2CLK>;
>> +status = "disabled";
>> +};
>> +
>> +uart6: serial@1f822a00 {
>> +compatible = "microchip,pic32mzda-uart";
>> +reg = <0x1f822a00 0x50>;
>> +interrupts = <188 IRQ_TYPE_LEVEL_HIGH>;
>> +clocks = <&clock PB2CLK>;
>> +status = "disabled";
>> +};
>> +
>> +evic: interrupt-controller@1f81 {
>> +compatible = "microchip,pic32mzda-evic";
>> +interrupt-controller;
>> +#interrupt-cells = <2>;
>> +reg = <0x1f81 0x1000>;
>> +};
>> +
>> +pinctrl: pinctrl@1f801400 {
>> +compatible = "microchip,pic32mzda-pinctrl";
>> +reg = <0x1f801400 0x100>, /* in */
>> + <0x1f801500 0x200>, /* out */
>> + <0x1f86 0xa00>; /* port */
>> +reg-names = "ppsin","ppsout","port";
>> +status = "disabled";
>> +
>> +ranges = <0 0x1f86 0xa00>;
>> +#address-cells = <1>;
>> +#size-cells = <1>;
>> +gpioA: gpio0@0 {
>> +compatible = "microchip,pic32mzda-gpio";
>> +reg = <0x000 0x48>;
>> +gpio-controller;
>> +#gpio-cells = <2>;
>> +};
>> +
>> +gpioB: gpio1@100 {
>> +compatible = "microchip,pic32mzda-gpio";
>> +reg = <0x100 0x48>;
>> +gpio-controller;
>> +#gpio-cells = <2>;
>> +};
>> +
>> +gpioC: gpio2@200 {
>> +compatible = "microchip,pic32mzda-gpio";
>> +reg = <0x200 0x48>;
>> +gpio-controller;
>> +#gpio-cells = <2>;
>> +};
>> +
>> +gpioD: gpio3@300 {
>> +compatible =
Re: [U-Boot] [PATCH v3 08/14] MIPS: Add support for Microchip PIC32MZ[DA] SoC family.
Am Dienstag, den 12.01.2016, 15:48 +0530 schrieb Purna Chandra Mandal:
> Add Microchip PIC32MZ[DA] SoC family support.
>
> Signed-off-by: Purna Chandra Mandal
>
> ---
>
> Changes in v3:
> - drop forcing CONFIG_MIPS_BOOT_* selection in mach-pic32/Kconfig
> - indent assembly instructions in delay slot
> - made GPIO-nodes child of pinctrl-node in devicetree
> - replace pic32_ioremap() with ioremap()
>
> Changes in v2:
> - drop board_early_init_f
> - use macro LEAF(), END() for lowlevel_init assembly
> - move initialization of board_init_f() argument to common start.S
> - move initdram() from board/microchip/ to mach-pic32/cpu.c
> - remove MIPS virtual address in favor physical one in dts file
>
> arch/mips/dts/pic32mzda.dtsi | 153
> ++
> arch/mips/mach-pic32/Kconfig | 20 +++-
> arch/mips/mach-pic32/Makefile | 2 +-
> arch/mips/mach-pic32/cpu.c| 147
>
> arch/mips/mach-pic32/include/mach/pic32.h | 3 +
> arch/mips/mach-pic32/lowlevel_init.S | 27 ++
> arch/mips/mach-pic32/reset.c | 36 +++
> 7 files changed, 386 insertions(+), 2 deletions(-)
> create mode 100644 arch/mips/dts/pic32mzda.dtsi
> create mode 100644 arch/mips/mach-pic32/lowlevel_init.S
> create mode 100644 arch/mips/mach-pic32/reset.c
>
> diff --git a/arch/mips/dts/pic32mzda.dtsi
> b/arch/mips/dts/pic32mzda.dtsi
> new file mode 100644
> index 000..fe8b13a
> --- /dev/null
> +++ b/arch/mips/dts/pic32mzda.dtsi
> @@ -0,0 +1,153 @@
> +/*
> + * Copyright 2015 Microchip Technology, Inc.
> + * Purna Chandra Mandal,
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include
> +#include
> +#include
> +#include "skeleton.dtsi"
> +
> +/ {
> + compatible = "microchip,pic32mzda", "microchip,pic32mz";
> +
> + aliases {
> + gpio0 = &gpioA;
> + gpio1 = &gpioB;
> + gpio2 = &gpioC;
> + gpio3 = &gpioD;
> + gpio4 = &gpioE;
> + gpio5 = &gpioF;
> + gpio6 = &gpioG;
> + gpio7 = &gpioH;
> + gpio8 = &gpioJ;
> + gpio9 = &gpioK;
> + };
> +
> + cpus {
> + cpu@0 {
> + compatible = "mips,mips14kc";
> + };
> + };
> +
> + clock: clk@1f801200 {
> + compatible = "microchip,pic32mzda_clk";
> + reg = <0x1f801200 0x1000>;
> + clock-cells = <1>;
> + };
> +
> + uart1: serial@1f822000 {
> + compatible = "microchip,pic32mzda-uart";
> + reg = <0x1f822000 0x50>;
> + interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + clocks = <&clock PB2CLK>;
> + };
> +
> + uart2: serial@1f822200 {
> + compatible = "microchip,pic32mzda-uart";
> + reg = <0x1f822200 0x50>;
> + interrupts = <145 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clock PB2CLK>;
> + status = "disabled";
> + };
> +
> + uart6: serial@1f822a00 {
> + compatible = "microchip,pic32mzda-uart";
> + reg = <0x1f822a00 0x50>;
> + interrupts = <188 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clock PB2CLK>;
> + status = "disabled";
> + };
> +
> + evic: interrupt-controller@1f81 {
> + compatible = "microchip,pic32mzda-evic";
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + reg = <0x1f81 0x1000>;
> + };
> +
> + pinctrl: pinctrl@1f801400 {
> + compatible = "microchip,pic32mzda-pinctrl";
> + reg = <0x1f801400 0x100>, /* in */
> + <0x1f801500 0x200>, /* out */
> + <0x1f86 0xa00>; /* port */
> + reg-names = "ppsin","ppsout","port";
> + status = "disabled";
> +
> + ranges = <0 0x1f86 0xa00>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + gpioA: gpio0@0 {
> + compatible = "microchip,pic32mzda-gpio";
> + reg = <0x000 0x48>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +
> + gpioB: gpio1@100 {
> + compatible = "microchip,pic32mzda-gpio";
> + reg = <0x100 0x48>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +
> + gpioC: gpio2@200 {
> + compatible = "microchip,pic32mzda-gpio";
> + reg = <0x200 0x48>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +
> + gpioD: gpio3@300 {
> + compatible = "microchip,pic32mzda-gpio";
> + reg = <0x300 0x48>;
> + gpio-controller
