Re: [U-Boot] [PATCH v8 4/8] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading
On 2/14/19 4:23 PM, Chee, Tien Fong wrote:
> On Thu, 2019-02-14 at 16:15 +0100, Marek Vasut wrote:
>> On 2/14/19 4:14 PM, Chee, Tien Fong wrote:
>>>
>>> On Thu, 2019-02-14 at 13:29 +0100, Marek Vasut wrote:
On 2/14/19 1:14 PM, Chee, Tien Fong wrote:
>
>
> On Thu, 2019-02-14 at 11:41 +0100, Marek Vasut wrote:
>>
>>
>> On 2/14/19 7:44 AM, Chee, Tien Fong wrote:
>>>
>>>
>>>
>>> On Wed, 2019-02-13 at 17:20 +0100, Marek Vasut wrote:
On 2/13/19 3:18 PM, tien.fong.c...@intel.com wrote:
>
>
>
>
> From: Tien Fong Chee
>
> Add FPGA driver to support program FPGA with FPGA
> bitstream
> loading
> from
> filesystem. The driver are designed based on generic
> firmware
> loader
> framework. The driver can handle FPGA program operation
> from
> loading FPGA
> bitstream in flash to memory and then to program FPGA.
>
> Signed-off-by: Tien Fong Chee >
>
> ---
>
> changes for v8
> - Added codes to discern bitstream type based on fpga
> node
> name.
>
> changes for v7
> - Restructure the FPGA driver to support both
> peripheral
> bitstream
> and core
> bitstream bundled into FIT image.
> - Support loadable property for core bitstream. User
> can
> set
> loadable
> in DDR for better performance. This loading would be
> done
> in
> one
> large
> chunk instead of chunk by chunk loading with small
> memory
> buffer.
> ---
> arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts |
> 17 +
> .../include/mach/fpga_manager_arria10.h|
> 39
> +-
> drivers/fpga/socfpga_arria10.c |
> 467
> -
> 3 files changed, 500 insertions(+), 23 deletions(-)
>
> diff --git
> a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> index 998d811..14f1967 100644
> --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> [...]
>
>>
>>
>>>
>>>
>
>
> - * FPGA Manager to program the FPGA. This is the
> interface
> used by
> FPGA driver.
> - * Return 0 for sucess, non-zero for error.
> - */
> +char *get_fpga_filename(const void *fdt, int *len)
> +{
> + char *fpga_filename = NULL;
> + int node_offset;
> +
> + fdtdec_find_aliases_for_id(gd->fdt_blob,
> "fpga_mgr",
> + COMPAT_ALTERA_SOCFPGA_
> FPGA
> 0,
> + _offset, 1);
> +
> + ofnode fpgamgr_node =
> offset_to_ofnode(node_offset);
> +
> + if (ofnode_valid(fpgamgr_node))
> + fpga_filename = (char
> *)ofnode_read_string(fpgamgr_node,
> + "altr,
> bits
> trea
> m");
> +
> +
Why is the cast needed ?
>>> The return string would be eventually set to the char
>>> *filename
>>> in
>>> common struct fpga_fsinfo. So, the cast here is to avoid
>>> the
>>> warning
>>> from compiler.
>> I presume if the compiler generates a warning, it's for a
>> reason.
>> What
>> warning is that ?
> drivers/fpga/socfpga_arria10.c: In function
> 'get_fpga_filename':
> drivers/fpga/socfpga_arria10.c:466:17: warning: assignment
> discards
> 'const' qualifier from pointer target type [-Wdiscarded-
> qualifiers]
> fpga_filename = ofnode_read_string(fpgamgr_node,
Add missing const then ?
>>> Then this requires change on common struct fpga_fsinfo, this would
>>> impact to other user using this. Why the cast is not allow as we
>>> only
>>> reading the filename?
>> If the string isn't const, someone can write it. If someone writes
>> this
>> string, won't it corrupt the DT ?
> Yes, but this would not happen in this driver, right?
> I don't know also why this common struct declare without the const, may
> be it supports the write?
I think so, maybe you should check that.
--
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v8 4/8] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading
On Thu, 2019-02-14 at 16:15 +0100, Marek Vasut wrote:
> On 2/14/19 4:14 PM, Chee, Tien Fong wrote:
> >
> > On Thu, 2019-02-14 at 13:29 +0100, Marek Vasut wrote:
> > >
> > > On 2/14/19 1:14 PM, Chee, Tien Fong wrote:
> > > >
> > > >
> > > > On Thu, 2019-02-14 at 11:41 +0100, Marek Vasut wrote:
> > > > >
> > > > >
> > > > > On 2/14/19 7:44 AM, Chee, Tien Fong wrote:
> > > > > >
> > > > > >
> > > > > >
> > > > > > On Wed, 2019-02-13 at 17:20 +0100, Marek Vasut wrote:
> > > > > > >
> > > > > > >
> > > > > > >
> > > > > > > On 2/13/19 3:18 PM, tien.fong.c...@intel.com wrote:
> > > > > > > >
> > > > > > > >
> > > > > > > >
> > > > > > > >
> > > > > > > > From: Tien Fong Chee
> > > > > > > >
> > > > > > > > Add FPGA driver to support program FPGA with FPGA
> > > > > > > > bitstream
> > > > > > > > loading
> > > > > > > > from
> > > > > > > > filesystem. The driver are designed based on generic
> > > > > > > > firmware
> > > > > > > > loader
> > > > > > > > framework. The driver can handle FPGA program operation
> > > > > > > > from
> > > > > > > > loading FPGA
> > > > > > > > bitstream in flash to memory and then to program FPGA.
> > > > > > > >
> > > > > > > > Signed-off-by: Tien Fong Chee > > > > > > > >
> > > > > > > >
> > > > > > > > ---
> > > > > > > >
> > > > > > > > changes for v8
> > > > > > > > - Added codes to discern bitstream type based on fpga
> > > > > > > > node
> > > > > > > > name.
> > > > > > > >
> > > > > > > > changes for v7
> > > > > > > > - Restructure the FPGA driver to support both
> > > > > > > > peripheral
> > > > > > > > bitstream
> > > > > > > > and core
> > > > > > > > bitstream bundled into FIT image.
> > > > > > > > - Support loadable property for core bitstream. User
> > > > > > > > can
> > > > > > > > set
> > > > > > > > loadable
> > > > > > > > in DDR for better performance. This loading would be
> > > > > > > > done
> > > > > > > > in
> > > > > > > > one
> > > > > > > > large
> > > > > > > > chunk instead of chunk by chunk loading with small
> > > > > > > > memory
> > > > > > > > buffer.
> > > > > > > > ---
> > > > > > > > arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts |
> > > > > > > > 17 +
> > > > > > > > .../include/mach/fpga_manager_arria10.h|
> > > > > > > > 39
> > > > > > > > +-
> > > > > > > > drivers/fpga/socfpga_arria10.c |
> > > > > > > > 467
> > > > > > > > -
> > > > > > > > 3 files changed, 500 insertions(+), 23 deletions(-)
> > > > > > > >
> > > > > > > > diff --git
> > > > > > > > a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > > > > > b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > > > > > index 998d811..14f1967 100644
> > > > > > > > --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > > > > > +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > [...]
> > > >
> > > > >
> > > > >
> > > > > >
> > > > > >
> > > > > > >
> > > > > > >
> > > > > > > >
> > > > > > > >
> > > > > > > > - * FPGA Manager to program the FPGA. This is the
> > > > > > > > interface
> > > > > > > > used by
> > > > > > > > FPGA driver.
> > > > > > > > - * Return 0 for sucess, non-zero for error.
> > > > > > > > - */
> > > > > > > > +char *get_fpga_filename(const void *fdt, int *len)
> > > > > > > > +{
> > > > > > > > + char *fpga_filename = NULL;
> > > > > > > > + int node_offset;
> > > > > > > > +
> > > > > > > > + fdtdec_find_aliases_for_id(gd->fdt_blob,
> > > > > > > > "fpga_mgr",
> > > > > > > > + COMPAT_ALTERA_SOCFPGA_
> > > > > > > > FPGA
> > > > > > > > 0,
> > > > > > > > + _offset, 1);
> > > > > > > > +
> > > > > > > > + ofnode fpgamgr_node =
> > > > > > > > offset_to_ofnode(node_offset);
> > > > > > > > +
> > > > > > > > + if (ofnode_valid(fpgamgr_node))
> > > > > > > > + fpga_filename = (char
> > > > > > > > *)ofnode_read_string(fpgamgr_node,
> > > > > > > > + "altr,
> > > > > > > > bits
> > > > > > > > trea
> > > > > > > > m");
> > > > > > > > +
> > > > > > > > +
> > > > > > > Why is the cast needed ?
> > > > > > The return string would be eventually set to the char
> > > > > > *filename
> > > > > > in
> > > > > > common struct fpga_fsinfo. So, the cast here is to avoid
> > > > > > the
> > > > > > warning
> > > > > > from compiler.
> > > > > I presume if the compiler generates a warning, it's for a
> > > > > reason.
> > > > > What
> > > > > warning is that ?
> > > > drivers/fpga/socfpga_arria10.c: In function
> > > > 'get_fpga_filename':
> > > > drivers/fpga/socfpga_arria10.c:466:17: warning: assignment
> > > > discards
> > > > 'const' qualifier from pointer target type [-Wdiscarded-
> > > > qualifiers]
> > > > fpga_filename = ofnode_read_string(fpgamgr_node,
> > > Add missing const then ?
> > Then this requires change on common struct fpga_fsinfo, this would
> > impact to other user using this. Why the
Re: [U-Boot] [PATCH v8 4/8] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading
On 2/14/19 4:14 PM, Chee, Tien Fong wrote:
> On Thu, 2019-02-14 at 13:29 +0100, Marek Vasut wrote:
>> On 2/14/19 1:14 PM, Chee, Tien Fong wrote:
>>>
>>> On Thu, 2019-02-14 at 11:41 +0100, Marek Vasut wrote:
On 2/14/19 7:44 AM, Chee, Tien Fong wrote:
>
>
> On Wed, 2019-02-13 at 17:20 +0100, Marek Vasut wrote:
>>
>>
>> On 2/13/19 3:18 PM, tien.fong.c...@intel.com wrote:
>>>
>>>
>>>
>>> From: Tien Fong Chee
>>>
>>> Add FPGA driver to support program FPGA with FPGA bitstream
>>> loading
>>> from
>>> filesystem. The driver are designed based on generic
>>> firmware
>>> loader
>>> framework. The driver can handle FPGA program operation
>>> from
>>> loading FPGA
>>> bitstream in flash to memory and then to program FPGA.
>>>
>>> Signed-off-by: Tien Fong Chee
>>>
>>> ---
>>>
>>> changes for v8
>>> - Added codes to discern bitstream type based on fpga node
>>> name.
>>>
>>> changes for v7
>>> - Restructure the FPGA driver to support both peripheral
>>> bitstream
>>> and core
>>> bitstream bundled into FIT image.
>>> - Support loadable property for core bitstream. User can
>>> set
>>> loadable
>>> in DDR for better performance. This loading would be done
>>> in
>>> one
>>> large
>>> chunk instead of chunk by chunk loading with small memory
>>> buffer.
>>> ---
>>> arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 17 +
>>> .../include/mach/fpga_manager_arria10.h| 39
>>> +-
>>> drivers/fpga/socfpga_arria10.c | 467
>>> -
>>> 3 files changed, 500 insertions(+), 23 deletions(-)
>>>
>>> diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
>>> b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
>>> index 998d811..14f1967 100644
>>> --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
>>> +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
>>> [...]
>>>
>
>>
>>>
>>> - * FPGA Manager to program the FPGA. This is the interface
>>> used by
>>> FPGA driver.
>>> - * Return 0 for sucess, non-zero for error.
>>> - */
>>> +char *get_fpga_filename(const void *fdt, int *len)
>>> +{
>>> + char *fpga_filename = NULL;
>>> + int node_offset;
>>> +
>>> + fdtdec_find_aliases_for_id(gd->fdt_blob,
>>> "fpga_mgr",
>>> + COMPAT_ALTERA_SOCFPGA_FPGA
>>> 0,
>>> + _offset, 1);
>>> +
>>> + ofnode fpgamgr_node =
>>> offset_to_ofnode(node_offset);
>>> +
>>> + if (ofnode_valid(fpgamgr_node))
>>> + fpga_filename = (char
>>> *)ofnode_read_string(fpgamgr_node,
>>> + "altr,bits
>>> trea
>>> m");
>>> +
>>> +
>> Why is the cast needed ?
> The return string would be eventually set to the char *filename
> in
> common struct fpga_fsinfo. So, the cast here is to avoid the
> warning
> from compiler.
I presume if the compiler generates a warning, it's for a reason.
What
warning is that ?
>>> drivers/fpga/socfpga_arria10.c: In function 'get_fpga_filename':
>>> drivers/fpga/socfpga_arria10.c:466:17: warning: assignment discards
>>> 'const' qualifier from pointer target type [-Wdiscarded-qualifiers]
>>> fpga_filename = ofnode_read_string(fpgamgr_node,
>> Add missing const then ?
> Then this requires change on common struct fpga_fsinfo, this would
> impact to other user using this. Why the cast is not allow as we only
> reading the filename?
If the string isn't const, someone can write it. If someone writes this
string, won't it corrupt the DT ?
--
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v8 4/8] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading
On Thu, 2019-02-14 at 13:29 +0100, Marek Vasut wrote:
> On 2/14/19 1:14 PM, Chee, Tien Fong wrote:
> >
> > On Thu, 2019-02-14 at 11:41 +0100, Marek Vasut wrote:
> > >
> > > On 2/14/19 7:44 AM, Chee, Tien Fong wrote:
> > > >
> > > >
> > > > On Wed, 2019-02-13 at 17:20 +0100, Marek Vasut wrote:
> > > > >
> > > > >
> > > > > On 2/13/19 3:18 PM, tien.fong.c...@intel.com wrote:
> > > > > >
> > > > > >
> > > > > >
> > > > > > From: Tien Fong Chee
> > > > > >
> > > > > > Add FPGA driver to support program FPGA with FPGA bitstream
> > > > > > loading
> > > > > > from
> > > > > > filesystem. The driver are designed based on generic
> > > > > > firmware
> > > > > > loader
> > > > > > framework. The driver can handle FPGA program operation
> > > > > > from
> > > > > > loading FPGA
> > > > > > bitstream in flash to memory and then to program FPGA.
> > > > > >
> > > > > > Signed-off-by: Tien Fong Chee
> > > > > >
> > > > > > ---
> > > > > >
> > > > > > changes for v8
> > > > > > - Added codes to discern bitstream type based on fpga node
> > > > > > name.
> > > > > >
> > > > > > changes for v7
> > > > > > - Restructure the FPGA driver to support both peripheral
> > > > > > bitstream
> > > > > > and core
> > > > > > bitstream bundled into FIT image.
> > > > > > - Support loadable property for core bitstream. User can
> > > > > > set
> > > > > > loadable
> > > > > > in DDR for better performance. This loading would be done
> > > > > > in
> > > > > > one
> > > > > > large
> > > > > > chunk instead of chunk by chunk loading with small memory
> > > > > > buffer.
> > > > > > ---
> > > > > > arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 17 +
> > > > > > .../include/mach/fpga_manager_arria10.h| 39
> > > > > > +-
> > > > > > drivers/fpga/socfpga_arria10.c | 467
> > > > > > -
> > > > > > 3 files changed, 500 insertions(+), 23 deletions(-)
> > > > > >
> > > > > > diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > > > b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > > > index 998d811..14f1967 100644
> > > > > > --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > > > +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > [...]
> >
> > >
> > > >
> > > > >
> > > > > >
> > > > > > - * FPGA Manager to program the FPGA. This is the interface
> > > > > > used by
> > > > > > FPGA driver.
> > > > > > - * Return 0 for sucess, non-zero for error.
> > > > > > - */
> > > > > > +char *get_fpga_filename(const void *fdt, int *len)
> > > > > > +{
> > > > > > + char *fpga_filename = NULL;
> > > > > > + int node_offset;
> > > > > > +
> > > > > > + fdtdec_find_aliases_for_id(gd->fdt_blob,
> > > > > > "fpga_mgr",
> > > > > > + COMPAT_ALTERA_SOCFPGA_FPGA
> > > > > > 0,
> > > > > > + _offset, 1);
> > > > > > +
> > > > > > + ofnode fpgamgr_node =
> > > > > > offset_to_ofnode(node_offset);
> > > > > > +
> > > > > > + if (ofnode_valid(fpgamgr_node))
> > > > > > + fpga_filename = (char
> > > > > > *)ofnode_read_string(fpgamgr_node,
> > > > > > + "altr,bits
> > > > > > trea
> > > > > > m");
> > > > > > +
> > > > > > +
> > > > > Why is the cast needed ?
> > > > The return string would be eventually set to the char *filename
> > > > in
> > > > common struct fpga_fsinfo. So, the cast here is to avoid the
> > > > warning
> > > > from compiler.
> > > I presume if the compiler generates a warning, it's for a reason.
> > > What
> > > warning is that ?
> > drivers/fpga/socfpga_arria10.c: In function 'get_fpga_filename':
> > drivers/fpga/socfpga_arria10.c:466:17: warning: assignment discards
> > 'const' qualifier from pointer target type [-Wdiscarded-qualifiers]
> > fpga_filename = ofnode_read_string(fpgamgr_node,
> Add missing const then ?
Then this requires change on common struct fpga_fsinfo, this would
impact to other user using this. Why the cast is not allow as we only
reading the filename?
>
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Re: [U-Boot] [PATCH v8 4/8] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading
On 2/14/19 1:14 PM, Chee, Tien Fong wrote:
> On Thu, 2019-02-14 at 11:41 +0100, Marek Vasut wrote:
>> On 2/14/19 7:44 AM, Chee, Tien Fong wrote:
>>>
>>> On Wed, 2019-02-13 at 17:20 +0100, Marek Vasut wrote:
On 2/13/19 3:18 PM, tien.fong.c...@intel.com wrote:
>
>
> From: Tien Fong Chee
>
> Add FPGA driver to support program FPGA with FPGA bitstream
> loading
> from
> filesystem. The driver are designed based on generic firmware
> loader
> framework. The driver can handle FPGA program operation from
> loading FPGA
> bitstream in flash to memory and then to program FPGA.
>
> Signed-off-by: Tien Fong Chee
>
> ---
>
> changes for v8
> - Added codes to discern bitstream type based on fpga node
> name.
>
> changes for v7
> - Restructure the FPGA driver to support both peripheral
> bitstream
> and core
> bitstream bundled into FIT image.
> - Support loadable property for core bitstream. User can set
> loadable
> in DDR for better performance. This loading would be done in
> one
> large
> chunk instead of chunk by chunk loading with small memory
> buffer.
> ---
> arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 17 +
> .../include/mach/fpga_manager_arria10.h| 39 +-
> drivers/fpga/socfpga_arria10.c | 467
> -
> 3 files changed, 500 insertions(+), 23 deletions(-)
>
> diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> index 998d811..14f1967 100644
> --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> [...]
>
> - * FPGA Manager to program the FPGA. This is the interface
> used by
> FPGA driver.
> - * Return 0 for sucess, non-zero for error.
> - */
> +char *get_fpga_filename(const void *fdt, int *len)
> +{
> + char *fpga_filename = NULL;
> + int node_offset;
> +
> + fdtdec_find_aliases_for_id(gd->fdt_blob, "fpga_mgr",
> + COMPAT_ALTERA_SOCFPGA_FPGA0,
> + _offset, 1);
> +
> + ofnode fpgamgr_node = offset_to_ofnode(node_offset);
> +
> + if (ofnode_valid(fpgamgr_node))
> + fpga_filename = (char
> *)ofnode_read_string(fpgamgr_node,
> + "altr,bitstrea
> m");
> +
> +
Why is the cast needed ?
>>> The return string would be eventually set to the char *filename in
>>> common struct fpga_fsinfo. So, the cast here is to avoid the
>>> warning
>>> from compiler.
>> I presume if the compiler generates a warning, it's for a reason.
>> What
>> warning is that ?
> drivers/fpga/socfpga_arria10.c: In function 'get_fpga_filename':
> drivers/fpga/socfpga_arria10.c:466:17: warning: assignment discards
> 'const' qualifier from pointer target type [-Wdiscarded-qualifiers]
> fpga_filename = ofnode_read_string(fpgamgr_node,
Add missing const then ?
--
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v8 4/8] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading
On Thu, 2019-02-14 at 11:41 +0100, Marek Vasut wrote:
> On 2/14/19 7:44 AM, Chee, Tien Fong wrote:
> >
> > On Wed, 2019-02-13 at 17:20 +0100, Marek Vasut wrote:
> > >
> > > On 2/13/19 3:18 PM, tien.fong.c...@intel.com wrote:
> > > >
> > > >
> > > > From: Tien Fong Chee
> > > >
> > > > Add FPGA driver to support program FPGA with FPGA bitstream
> > > > loading
> > > > from
> > > > filesystem. The driver are designed based on generic firmware
> > > > loader
> > > > framework. The driver can handle FPGA program operation from
> > > > loading FPGA
> > > > bitstream in flash to memory and then to program FPGA.
> > > >
> > > > Signed-off-by: Tien Fong Chee
> > > >
> > > > ---
> > > >
> > > > changes for v8
> > > > - Added codes to discern bitstream type based on fpga node
> > > > name.
> > > >
> > > > changes for v7
> > > > - Restructure the FPGA driver to support both peripheral
> > > > bitstream
> > > > and core
> > > > bitstream bundled into FIT image.
> > > > - Support loadable property for core bitstream. User can set
> > > > loadable
> > > > in DDR for better performance. This loading would be done in
> > > > one
> > > > large
> > > > chunk instead of chunk by chunk loading with small memory
> > > > buffer.
> > > > ---
> > > > arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 17 +
> > > > .../include/mach/fpga_manager_arria10.h| 39 +-
> > > > drivers/fpga/socfpga_arria10.c | 467
> > > > -
> > > > 3 files changed, 500 insertions(+), 23 deletions(-)
> > > >
> > > > diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > index 998d811..14f1967 100644
> > > > --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
[...]
> > > > - * FPGA Manager to program the FPGA. This is the interface
> > > > used by
> > > > FPGA driver.
> > > > - * Return 0 for sucess, non-zero for error.
> > > > - */
> > > > +char *get_fpga_filename(const void *fdt, int *len)
> > > > +{
> > > > + char *fpga_filename = NULL;
> > > > + int node_offset;
> > > > +
> > > > + fdtdec_find_aliases_for_id(gd->fdt_blob, "fpga_mgr",
> > > > + COMPAT_ALTERA_SOCFPGA_FPGA0,
> > > > + _offset, 1);
> > > > +
> > > > + ofnode fpgamgr_node = offset_to_ofnode(node_offset);
> > > > +
> > > > + if (ofnode_valid(fpgamgr_node))
> > > > + fpga_filename = (char
> > > > *)ofnode_read_string(fpgamgr_node,
> > > > + "altr,bitstrea
> > > > m");
> > > > +
> > > > +
> > > Why is the cast needed ?
> > The return string would be eventually set to the char *filename in
> > common struct fpga_fsinfo. So, the cast here is to avoid the
> > warning
> > from compiler.
> I presume if the compiler generates a warning, it's for a reason.
> What
> warning is that ?
drivers/fpga/socfpga_arria10.c: In function 'get_fpga_filename':
drivers/fpga/socfpga_arria10.c:466:17: warning: assignment discards
'const' qualifier from pointer target type [-Wdiscarded-qualifiers]
fpga_filename = ofnode_read_string(fpgamgr_node,
>
[...]
___
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Re: [U-Boot] [PATCH v8 4/8] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading
On Thu, 2019-02-14 at 11:41 +0100, Marek Vasut wrote:
> On 2/14/19 7:44 AM, Chee, Tien Fong wrote:
> >
> > On Wed, 2019-02-13 at 17:20 +0100, Marek Vasut wrote:
> > >
> > > On 2/13/19 3:18 PM, tien.fong.c...@intel.com wrote:
> > > >
> > > >
> > > > From: Tien Fong Chee
> > > >
> > > > Add FPGA driver to support program FPGA with FPGA bitstream
> > > > loading
> > > > from
> > > > filesystem. The driver are designed based on generic firmware
> > > > loader
> > > > framework. The driver can handle FPGA program operation from
> > > > loading FPGA
> > > > bitstream in flash to memory and then to program FPGA.
> > > >
> > > > Signed-off-by: Tien Fong Chee
> > > >
> > > > ---
> > > >
> > > > changes for v8
> > > > - Added codes to discern bitstream type based on fpga node
> > > > name.
> > > >
> > > > changes for v7
> > > > - Restructure the FPGA driver to support both peripheral
> > > > bitstream
> > > > and core
> > > > bitstream bundled into FIT image.
> > > > - Support loadable property for core bitstream. User can set
> > > > loadable
> > > > in DDR for better performance. This loading would be done in
> > > > one
> > > > large
> > > > chunk instead of chunk by chunk loading with small memory
> > > > buffer.
> > > > ---
> > > > arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 17 +
> > > > .../include/mach/fpga_manager_arria10.h| 39 +-
> > > > drivers/fpga/socfpga_arria10.c | 467
> > > > -
> > > > 3 files changed, 500 insertions(+), 23 deletions(-)
> > > >
> > > > diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > index 998d811..14f1967 100644
> > > > --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > @@ -18,6 +18,23 @@
> > > > /dts-v1/;
> > > > #include "socfpga_arria10_socdk.dtsi"
> > > >
> > > > +/ {
> > > > + chosen {
> > > > + firmware-loader = _loader0;
> > > Should be a phandle.
> > Can we change this label to phandle stage by stage, may be after
> > fpga
> > driver? This requires time working on firmware loader.
> We should fix this as soon as possible, otherwise people might find
> this
> bad example and wonder why it doesn't work once this is changed.
Okay.
>
> >
> > >
> > >
> > > >
> > > >
> > > > + };
> > > > +
> > > > + fs_loader0: fs-loader@0 {
> > > > + u-boot,dm-pre-reloc;
> > > > + compatible = "u-boot,fs-loader";
> > > > + phandlepart = < 1>;
> > > > + };
> > > > +};
> > > > +
> > > > +_mgr {
> > > > + u-boot,dm-pre-reloc;
> > > > + altr,bitstream = "fit_spl_fpga.itb";
> > > > +};
> > > > +
> > > > {
> > > > u-boot,dm-pre-reloc;
> > > > status = "okay";
> [...]
>
> >
> > >
> > > >
> > > > - * FPGA Manager to program the FPGA. This is the interface
> > > > used by
> > > > FPGA driver.
> > > > - * Return 0 for sucess, non-zero for error.
> > > > - */
> > > > +char *get_fpga_filename(const void *fdt, int *len)
> > > > +{
> > > > + char *fpga_filename = NULL;
> > > > + int node_offset;
> > > > +
> > > > + fdtdec_find_aliases_for_id(gd->fdt_blob, "fpga_mgr",
> > > > + COMPAT_ALTERA_SOCFPGA_FPGA0,
> > > > + _offset, 1);
> > > > +
> > > > + ofnode fpgamgr_node = offset_to_ofnode(node_offset);
> > > > +
> > > > + if (ofnode_valid(fpgamgr_node))
> > > > + fpga_filename = (char
> > > > *)ofnode_read_string(fpgamgr_node,
> > > > + "altr,bitstrea
> > > > m");
> > > > +
> > > > +
> > > Why is the cast needed ?
> > The return string would be eventually set to the char *filename in
> > common struct fpga_fsinfo. So, the cast here is to avoid the
> > warning
> > from compiler.
> I presume if the compiler generates a warning, it's for a reason.
> What
> warning is that ?
>
> >
> > >
> > > Drop the two newlines.
> > Okay.
> > >
> > >
> > > >
> > > >
> > > > + return fpga_filename;
> > > > +}
> > > > +
> > > > +static void get_rbf_image_info(struct rbf_info *rbf, u16
> > > > *buffer)
> > > > +{
> > > > + /*
> > > > + * Magic ID starting at:
> > > > + * -> 1st dword[15:0] in periph.rbf
> > > > + * -> 2nd dword[15:0] in core.rbf
> > > > + * Note: dword == 32 bits
> > > > + */
> > > > + u32 word_reading_max = 2;
> > > > + u32 i;
> > > > +
> > > > + for (i = 0; i < word_reading_max; i++) {
> > > > + if (*(buffer + i) ==
> > > > FPGA_SOCFPGA_A10_RBF_UNENCRYPTED) {
> > > > + rbf->security = unencrypted;
> > > > + } else if (*(buffer + i) ==
> > > > FPGA_SOCFPGA_A10_RBF_ENCRYPTED) {
> > > > + rbf->security = encrypted;
> > > > + } else if (*(buffer + i + 1) ==
> > > > +
Re: [U-Boot] [PATCH v8 4/8] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading
On 2/14/19 7:44 AM, Chee, Tien Fong wrote:
> On Wed, 2019-02-13 at 17:20 +0100, Marek Vasut wrote:
>> On 2/13/19 3:18 PM, tien.fong.c...@intel.com wrote:
>>>
>>> From: Tien Fong Chee
>>>
>>> Add FPGA driver to support program FPGA with FPGA bitstream loading
>>> from
>>> filesystem. The driver are designed based on generic firmware
>>> loader
>>> framework. The driver can handle FPGA program operation from
>>> loading FPGA
>>> bitstream in flash to memory and then to program FPGA.
>>>
>>> Signed-off-by: Tien Fong Chee
>>>
>>> ---
>>>
>>> changes for v8
>>> - Added codes to discern bitstream type based on fpga node name.
>>>
>>> changes for v7
>>> - Restructure the FPGA driver to support both peripheral bitstream
>>> and core
>>> bitstream bundled into FIT image.
>>> - Support loadable property for core bitstream. User can set
>>> loadable
>>> in DDR for better performance. This loading would be done in one
>>> large
>>> chunk instead of chunk by chunk loading with small memory buffer.
>>> ---
>>> arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 17 +
>>> .../include/mach/fpga_manager_arria10.h| 39 +-
>>> drivers/fpga/socfpga_arria10.c | 467
>>> -
>>> 3 files changed, 500 insertions(+), 23 deletions(-)
>>>
>>> diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
>>> b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
>>> index 998d811..14f1967 100644
>>> --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
>>> +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
>>> @@ -18,6 +18,23 @@
>>> /dts-v1/;
>>> #include "socfpga_arria10_socdk.dtsi"
>>>
>>> +/ {
>>> + chosen {
>>> + firmware-loader = _loader0;
>> Should be a phandle.
> Can we change this label to phandle stage by stage, may be after fpga
> driver? This requires time working on firmware loader.
We should fix this as soon as possible, otherwise people might find this
bad example and wonder why it doesn't work once this is changed.
>>
>>>
>>> + };
>>> +
>>> + fs_loader0: fs-loader@0 {
>>> + u-boot,dm-pre-reloc;
>>> + compatible = "u-boot,fs-loader";
>>> + phandlepart = < 1>;
>>> + };
>>> +};
>>> +
>>> +_mgr {
>>> + u-boot,dm-pre-reloc;
>>> + altr,bitstream = "fit_spl_fpga.itb";
>>> +};
>>> +
>>> {
>>> u-boot,dm-pre-reloc;
>>> status = "okay";
[...]
>>> - * FPGA Manager to program the FPGA. This is the interface used by
>>> FPGA driver.
>>> - * Return 0 for sucess, non-zero for error.
>>> - */
>>> +char *get_fpga_filename(const void *fdt, int *len)
>>> +{
>>> + char *fpga_filename = NULL;
>>> + int node_offset;
>>> +
>>> + fdtdec_find_aliases_for_id(gd->fdt_blob, "fpga_mgr",
>>> + COMPAT_ALTERA_SOCFPGA_FPGA0,
>>> + _offset, 1);
>>> +
>>> + ofnode fpgamgr_node = offset_to_ofnode(node_offset);
>>> +
>>> + if (ofnode_valid(fpgamgr_node))
>>> + fpga_filename = (char
>>> *)ofnode_read_string(fpgamgr_node,
>>> + "altr,bitstream");
>>> +
>>> +
>> Why is the cast needed ?
> The return string would be eventually set to the char *filename in
> common struct fpga_fsinfo. So, the cast here is to avoid the warning
> from compiler.
I presume if the compiler generates a warning, it's for a reason. What
warning is that ?
>> Drop the two newlines.
> Okay.
>>
>>>
>>> + return fpga_filename;
>>> +}
>>> +
>>> +static void get_rbf_image_info(struct rbf_info *rbf, u16 *buffer)
>>> +{
>>> + /*
>>> + * Magic ID starting at:
>>> + * -> 1st dword[15:0] in periph.rbf
>>> + * -> 2nd dword[15:0] in core.rbf
>>> + * Note: dword == 32 bits
>>> + */
>>> + u32 word_reading_max = 2;
>>> + u32 i;
>>> +
>>> + for (i = 0; i < word_reading_max; i++) {
>>> + if (*(buffer + i) ==
>>> FPGA_SOCFPGA_A10_RBF_UNENCRYPTED) {
>>> + rbf->security = unencrypted;
>>> + } else if (*(buffer + i) ==
>>> FPGA_SOCFPGA_A10_RBF_ENCRYPTED) {
>>> + rbf->security = encrypted;
>>> + } else if (*(buffer + i + 1) ==
>>> + FPGA_SOCFPGA_A10_RBF_UNENCRYPTED)
>>> {
>>> + rbf->security = unencrypted;
>>> + } else if (*(buffer + i + 1) ==
>>> + FPGA_SOCFPGA_A10_RBF_ENCRYPTED) {
>>> + rbf->security = encrypted;
>>> + } else {
>>> + rbf->security = invalid;
>>> + continue;
>>> + }
>>> +
>>> + /* PERIPH RBF(buffer + i + 1), CORE RBF(buffer + i
>>> + 2) */
>>> + if (*(buffer + i + 1) ==
>>> FPGA_SOCFPGA_A10_RBF_PERIPH) {
>>> + rbf->section = periph_section;
>>> + break;
>>> + } else if (*(buffer + i + 1) ==
>>> FPGA_SOCFPGA_A10_RBF_CORE) {
>>> + rbf->section = core_section;
>>> + break;
>>> + } else if (*(buffer + i + 2) ==
>>>
Re: [U-Boot] [PATCH v8 4/8] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading
On Wed, 2019-02-13 at 17:20 +0100, Marek Vasut wrote:
> On 2/13/19 3:18 PM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Add FPGA driver to support program FPGA with FPGA bitstream loading
> > from
> > filesystem. The driver are designed based on generic firmware
> > loader
> > framework. The driver can handle FPGA program operation from
> > loading FPGA
> > bitstream in flash to memory and then to program FPGA.
> >
> > Signed-off-by: Tien Fong Chee
> >
> > ---
> >
> > changes for v8
> > - Added codes to discern bitstream type based on fpga node name.
> >
> > changes for v7
> > - Restructure the FPGA driver to support both peripheral bitstream
> > and core
> > bitstream bundled into FIT image.
> > - Support loadable property for core bitstream. User can set
> > loadable
> > in DDR for better performance. This loading would be done in one
> > large
> > chunk instead of chunk by chunk loading with small memory buffer.
> > ---
> > arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 17 +
> > .../include/mach/fpga_manager_arria10.h| 39 +-
> > drivers/fpga/socfpga_arria10.c | 467
> > -
> > 3 files changed, 500 insertions(+), 23 deletions(-)
> >
> > diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > index 998d811..14f1967 100644
> > --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > @@ -18,6 +18,23 @@
> > /dts-v1/;
> > #include "socfpga_arria10_socdk.dtsi"
> >
> > +/ {
> > + chosen {
> > + firmware-loader = _loader0;
> Should be a phandle.
Can we change this label to phandle stage by stage, may be after fpga
driver? This requires time working on firmware loader.
>
> >
> > + };
> > +
> > + fs_loader0: fs-loader@0 {
> > + u-boot,dm-pre-reloc;
> > + compatible = "u-boot,fs-loader";
> > + phandlepart = < 1>;
> > + };
> > +};
> > +
> > +_mgr {
> > + u-boot,dm-pre-reloc;
> > + altr,bitstream = "fit_spl_fpga.itb";
> > +};
> > +
> > {
> > u-boot,dm-pre-reloc;
> > status = "okay";
> > diff --git a/arch/arm/mach-
> > socfpga/include/mach/fpga_manager_arria10.h b/arch/arm/mach-
> > socfpga/include/mach/fpga_manager_arria10.h
> > index 09d13f6..5ef15bb 100644
> > --- a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> > +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> > @@ -1,9 +1,13 @@
> > /* SPDX-License-Identifier: GPL-2.0 */
> > /*
> > - * Copyright (C) 2017 Intel Corporation
> > + * Copyright (C) 2017-2019 Intel Corporation
> > * All rights reserved.
> > */
> >
> > +#include
> > +#include
> > +#include
> > +
> > #ifndef _FPGA_MANAGER_ARRIA10_H_
> > #define _FPGA_MANAGER_ARRIA10_H_
> >
> > @@ -51,6 +55,10 @@
> > #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK
> > BIT(24)
> > #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB
> > 16
> >
> > +#define FPGA_SOCFPGA_A10_RBF_UNENCRYPTED 0xa65c
> > +#define FPGA_SOCFPGA_A10_RBF_ENCRYPTED 0xa65d
> > +#define FPGA_SOCFPGA_A10_RBF_PERIPH0x0001
> > +#define FPGA_SOCFPGA_A10_RBF_CORE 0x8001
> > #ifndef __ASSEMBLY__
> >
> > struct socfpga_fpga_manager {
> > @@ -88,12 +96,39 @@ struct socfpga_fpga_manager {
> > u32 imgcfg_fifo_status;
> > };
> >
> > +enum rbf_type {
> > + unknown,
> > + periph_section,
> > + core_section
> > +};
> > +
> > +enum rbf_security {
> > + invalid,
> > + unencrypted,
> > + encrypted
> > +};
> > +
> > +struct rbf_info {
> > + enum rbf_type section;
> > + enum rbf_security security;
> > +};
> > +
> > +struct fpga_loadfs_info {
> > + fpga_fs_info *fpga_fsinfo;
> > + u32 remaining;
> > + u32 offset;
> > + struct rbf_info rbfinfo;
> > +};
> > +
> > /* Functions */
> > int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size);
> > int fpgamgr_program_finish(void);
> > int is_fpgamgr_user_mode(void);
> > int fpgamgr_wait_early_user_mode(void);
> > -
> > +int is_fpgamgr_early_user_mode(void);
> > +char *get_fpga_filename(const void *fdt, int *len);
> > +int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf,
> > size_t bsize,
> > + u32 offset);
> > #endif /* __ASSEMBLY__ */
> >
> > #endif /* _FPGA_MANAGER_ARRIA10_H_ */
> > diff --git a/drivers/fpga/socfpga_arria10.c
> > b/drivers/fpga/socfpga_arria10.c
> > index 114dd91..630d5a3 100644
> > --- a/drivers/fpga/socfpga_arria10.c
> > +++ b/drivers/fpga/socfpga_arria10.c
> > @@ -1,8 +1,7 @@
> > // SPDX-License-Identifier: GPL-2.0
> > /*
> > - * Copyright (C) 2017 Intel Corporation
> > + * Copyright (C) 2017-2019 Intel Corporation
> > */
> > -
> > #include
> > #include
> > #include
> > @@ -10,8 +9,11 @@
> > #include
> > #include
> > #include
> > +#include
> > #include
> > +#include
> > #include
> > +#include
> > #include
> > #include
>
Re: [U-Boot] [PATCH v8 4/8] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading
On 2/13/19 3:18 PM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> Add FPGA driver to support program FPGA with FPGA bitstream loading from
> filesystem. The driver are designed based on generic firmware loader
> framework. The driver can handle FPGA program operation from loading FPGA
> bitstream in flash to memory and then to program FPGA.
>
> Signed-off-by: Tien Fong Chee
>
> ---
>
> changes for v8
> - Added codes to discern bitstream type based on fpga node name.
>
> changes for v7
> - Restructure the FPGA driver to support both peripheral bitstream and core
> bitstream bundled into FIT image.
> - Support loadable property for core bitstream. User can set loadable
> in DDR for better performance. This loading would be done in one large
> chunk instead of chunk by chunk loading with small memory buffer.
> ---
> arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 17 +
> .../include/mach/fpga_manager_arria10.h| 39 +-
> drivers/fpga/socfpga_arria10.c | 467
> -
> 3 files changed, 500 insertions(+), 23 deletions(-)
>
> diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> index 998d811..14f1967 100644
> --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> @@ -18,6 +18,23 @@
> /dts-v1/;
> #include "socfpga_arria10_socdk.dtsi"
>
> +/ {
> + chosen {
> + firmware-loader = _loader0;
Should be a phandle.
> + };
> +
> + fs_loader0: fs-loader@0 {
> + u-boot,dm-pre-reloc;
> + compatible = "u-boot,fs-loader";
> + phandlepart = < 1>;
> + };
> +};
> +
> +_mgr {
> + u-boot,dm-pre-reloc;
> + altr,bitstream = "fit_spl_fpga.itb";
> +};
> +
> {
> u-boot,dm-pre-reloc;
> status = "okay";
> diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> index 09d13f6..5ef15bb 100644
> --- a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> @@ -1,9 +1,13 @@
> /* SPDX-License-Identifier: GPL-2.0 */
> /*
> - * Copyright (C) 2017 Intel Corporation
> + * Copyright (C) 2017-2019 Intel Corporation
> * All rights reserved.
> */
>
> +#include
> +#include
> +#include
> +
> #ifndef _FPGA_MANAGER_ARRIA10_H_
> #define _FPGA_MANAGER_ARRIA10_H_
>
> @@ -51,6 +55,10 @@
> #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK BIT(24)
> #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB16
>
> +#define FPGA_SOCFPGA_A10_RBF_UNENCRYPTED 0xa65c
> +#define FPGA_SOCFPGA_A10_RBF_ENCRYPTED 0xa65d
> +#define FPGA_SOCFPGA_A10_RBF_PERIPH 0x0001
> +#define FPGA_SOCFPGA_A10_RBF_CORE0x8001
> #ifndef __ASSEMBLY__
>
> struct socfpga_fpga_manager {
> @@ -88,12 +96,39 @@ struct socfpga_fpga_manager {
> u32 imgcfg_fifo_status;
> };
>
> +enum rbf_type {
> + unknown,
> + periph_section,
> + core_section
> +};
> +
> +enum rbf_security {
> + invalid,
> + unencrypted,
> + encrypted
> +};
> +
> +struct rbf_info {
> + enum rbf_type section;
> + enum rbf_security security;
> +};
> +
> +struct fpga_loadfs_info {
> + fpga_fs_info *fpga_fsinfo;
> + u32 remaining;
> + u32 offset;
> + struct rbf_info rbfinfo;
> +};
> +
> /* Functions */
> int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size);
> int fpgamgr_program_finish(void);
> int is_fpgamgr_user_mode(void);
> int fpgamgr_wait_early_user_mode(void);
> -
> +int is_fpgamgr_early_user_mode(void);
> +char *get_fpga_filename(const void *fdt, int *len);
> +int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
> + u32 offset);
> #endif /* __ASSEMBLY__ */
>
> #endif /* _FPGA_MANAGER_ARRIA10_H_ */
> diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
> index 114dd91..630d5a3 100644
> --- a/drivers/fpga/socfpga_arria10.c
> +++ b/drivers/fpga/socfpga_arria10.c
> @@ -1,8 +1,7 @@
> // SPDX-License-Identifier: GPL-2.0
> /*
> - * Copyright (C) 2017 Intel Corporation
> + * Copyright (C) 2017-2019 Intel Corporation
> */
> -
> #include
> #include
> #include
> @@ -10,8 +9,11 @@
> #include
> #include
> #include
> +#include
> #include
> +#include
> #include
> +#include
> #include
> #include
>
> @@ -64,7 +66,7 @@ static int wait_for_user_mode(void)
> 1, FPGA_TIMEOUT_MSEC, false);
> }
>
> -static int is_fpgamgr_early_user_mode(void)
> +int is_fpgamgr_early_user_mode(void)
> {
> return (readl(_manager_base->imgcfg_stat) &
> ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK) != 0;
> @@ -92,9 +94,10 @@ int fpgamgr_wait_early_user_mode(void)
> sizeof(sync_data));
> udelay(FPGA_TIMEOUT_MSEC);
>
