[uClinux-dev] [PATCH 11/11] m68knommu: clean up ColdFire 54xx General Timer definitions

2012-09-20 Thread gerg 
From: Greg Ungerer 

Convert the ColdFire 54xx CPU General Timer register address definitions to
include the MCF_MBAR peripheral region offset. This makes them consistent
with all other 54xx address register definitions (in m54xxsim.h).

The goal is to reduce different definitions used (some including offsets and
others not) causing bugs when used incorrectly.

Signed-off-by: Greg Ungerer 
---
 arch/m68k/include/asm/m54xxgpt.h|   40 +-
 arch/m68k/platform/coldfire/m54xx.c |6 ++--
 drivers/watchdog/m54xx_wdt.c|   21 -
 3 files changed, 33 insertions(+), 34 deletions(-)

diff --git a/arch/m68k/include/asm/m54xxgpt.h b/arch/m68k/include/asm/m54xxgpt.h
index df75dd8..0b69cd1 100644
--- a/arch/m68k/include/asm/m54xxgpt.h
+++ b/arch/m68k/include/asm/m54xxgpt.h
@@ -16,26 +16,26 @@
 */
 
 /* Register read/write macros */
-#define MCF_GPT_GMS0   0x000800
-#define MCF_GPT_GCIR0  0x000804
-#define MCF_GPT_GPWM0  0x000808
-#define MCF_GPT_GSR0   0x00080C
-#define MCF_GPT_GMS1   0x000810
-#define MCF_GPT_GCIR1  0x000814
-#define MCF_GPT_GPWM1  0x000818
-#define MCF_GPT_GSR1   0x00081C
-#define MCF_GPT_GMS2   0x000820
-#define MCF_GPT_GCIR2  0x000824
-#define MCF_GPT_GPWM2  0x000828
-#define MCF_GPT_GSR2   0x00082C
-#define MCF_GPT_GMS3   0x000830
-#define MCF_GPT_GCIR3  0x000834
-#define MCF_GPT_GPWM3  0x000838
-#define MCF_GPT_GSR3   0x00083C
-#define MCF_GPT_GMS(x) (0x000800+((x)*0x010))
-#define MCF_GPT_GCIR(x)(0x000804+((x)*0x010))
-#define MCF_GPT_GPWM(x)(0x000808+((x)*0x010))
-#define MCF_GPT_GSR(x) (0x00080C+((x)*0x010))
+#define MCF_GPT_GMS0   (MCF_MBAR + 0x000800)
+#define MCF_GPT_GCIR0  (MCF_MBAR + 0x000804)
+#define MCF_GPT_GPWM0  (MCF_MBAR + 0x000808)
+#define MCF_GPT_GSR0   (MCF_MBAR + 0x00080C)
+#define MCF_GPT_GMS1   (MCF_MBAR + 0x000810)
+#define MCF_GPT_GCIR1  (MCF_MBAR + 0x000814)
+#define MCF_GPT_GPWM1  (MCF_MBAR + 0x000818)
+#define MCF_GPT_GSR1   (MCF_MBAR + 0x00081C)
+#define MCF_GPT_GMS2   (MCF_MBAR + 0x000820)
+#define MCF_GPT_GCIR2  (MCF_MBAR + 0x000824)
+#define MCF_GPT_GPWM2  (MCF_MBAR + 0x000828)
+#define MCF_GPT_GSR2   (MCF_MBAR + 0x00082C)
+#define MCF_GPT_GMS3   (MCF_MBAR + 0x000830)
+#define MCF_GPT_GCIR3  (MCF_MBAR + 0x000834)
+#define MCF_GPT_GPWM3  (MCF_MBAR + 0x000838)
+#define MCF_GPT_GSR3   (MCF_MBAR + 0x00083C)
+#define MCF_GPT_GMS(x) (MCF_MBAR + 0x000800 + ((x) * 0x010))
+#define MCF_GPT_GCIR(x)(MCF_MBAR + 0x000804 + ((x) * 0x010))
+#define MCF_GPT_GPWM(x)(MCF_MBAR + 0x000808 + ((x) * 0x010))
+#define MCF_GPT_GSR(x) (MCF_MBAR + 0x00080C + ((x) * 0x010))
 
 /* Bit definitions and macros for MCF_GPT_GMS */
 #define MCF_GPT_GMS_TMS(x) (((x)&0x0007)<<0)
diff --git a/arch/m68k/platform/coldfire/m54xx.c 
b/arch/m68k/platform/coldfire/m54xx.c
index 1f7c7fd..b587bf3 100644
--- a/arch/m68k/platform/coldfire/m54xx.c
+++ b/arch/m68k/platform/coldfire/m54xx.c
@@ -44,10 +44,10 @@ static void mcf54xx_reset(void)
 {
/* disable interrupts and enable the watchdog */
asm("movew #0x2700, %sr\n");
-   __raw_writel(0, MCF_MBAR + MCF_GPT_GMS0);
-   __raw_writel(MCF_GPT_GCIR_CNT(1), MCF_MBAR + MCF_GPT_GCIR0);
+   __raw_writel(0, MCF_GPT_GMS0);
+   __raw_writel(MCF_GPT_GCIR_CNT(1), MCF_GPT_GCIR0);
__raw_writel(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4),
-   MCF_MBAR + MCF_GPT_GMS0);
+   MCF_GPT_GMS0);
 }
 
 /***/
diff --git a/drivers/watchdog/m54xx_wdt.c b/drivers/watchdog/m54xx_wdt.c
index 663cad8..173494a 100644
--- a/drivers/watchdog/m54xx_wdt.c
+++ b/drivers/watchdog/m54xx_wdt.c
@@ -46,17 +46,17 @@ static void wdt_enable(void)
unsigned int gms0;
 
/* preserve GPIO usage, if any */
-   gms0 = __raw_readl(MCF_MBAR + MCF_GPT_GMS0);
+   gms0 = __raw_readl(MCF_GPT_GMS0);
if (gms0 & MCF_GPT_GMS_TMS_GPIO)
gms0 &= (MCF_GPT_GMS_TMS_GPIO | MCF_GPT_GMS_GPIO_MASK
| MCF_GPT_GMS_OD);
else
gms0 = MCF_GPT_GMS_TMS_GPIO | MCF_GPT_GMS_OD;
-   __raw_writel(gms0, MCF_MBAR + MCF_GPT_GMS0);
+   __raw_writel(gms0, MCF_GPT_GMS0);
__raw_writel(MCF_GPT_GCIR_PRE(heartbeat*(MCF_BUSCLK/0x)) |
-   MCF_GPT_GCIR_CNT(0x), MCF_MBAR + MCF_GPT_GCIR0);
+   MCF_GPT_GCIR_CNT(0x), MCF_GPT_GCIR0);
gms0 |= MCF_GPT_GMS_OCPW(0xA5) | MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE;
-   __raw_writel(gms0, MCF_MBAR + MCF_GPT_GMS0);
+   __raw_writel(gms0, MCF_GPT_GMS0);
 }
 
 static void wdt_disable(void)
@@ -64,18 +64,18 @@ static void wdt_disable(void)
unsigned int gms

[uClinux-dev] [PATCH 10/11] m68knommu: clean up Pin Assignment definitions for the 54xx ColdFire CPU

2012-09-20 Thread gerg 
From: Greg Ungerer 

The Pin Assignment register definitions for the ColdFire 54xx CPU family are
inconsistently named and defined compared to the other ColdFire part
definitions. Rename them with the same prefix as used on other parts,
MCFGPIO_PAR_, and make their definitions include the MCF_MBAR periphperal
region offset.

Signed-off-by: Greg Ungerer 
---
 arch/m68k/include/asm/m54xxsim.h|   21 ++---
 arch/m68k/platform/coldfire/m54xx.c |   10 --
 arch/m68k/platform/coldfire/pci.c   |4 ++--
 3 files changed, 20 insertions(+), 15 deletions(-)

diff --git a/arch/m68k/include/asm/m54xxsim.h b/arch/m68k/include/asm/m54xxsim.h
index d6a5079..d3bd838 100644
--- a/arch/m68k/include/asm/m54xxsim.h
+++ b/arch/m68k/include/asm/m54xxsim.h
@@ -70,15 +70,25 @@
 #defineMCFEPORT_EPFR   (MCF_MBAR + 0xf0c)  /* Flags */
 
 /*
- * Some PSC related definitions
+ * Pin Assignment register definitions
  */
-#define MCF_PAR_PSC(x) (0x000A4F-((x)&0x3))
+#define MCFGPIO_PAR_FBCTL  (MCF_MBAR + 0xA40)
+#define MCFGPIO_PAR_FBCS   (MCF_MBAR + 0xA42)
+#define MCFGPIO_PAR_DMA(MCF_MBAR + 0xA43)
+#define MCFGPIO_PAR_FECI2CIRQ  (MCF_MBAR + 0xA44)
+#define MCFGPIO_PAR_PCIBG  (MCF_MBAR + 0xA48)  /* PCI bus grant */
+#define MCFGPIO_PAR_PCIBR  (MCF_MBAR + 0xA4A)  /* PCI */
+#define MCFGPIO_PAR_PSC0   (MCF_MBAR + 0xA4F)
+#define MCFGPIO_PAR_PSC1   (MCF_MBAR + 0xA4E)
+#define MCFGPIO_PAR_PSC2   (MCF_MBAR + 0xA4D)
+#define MCFGPIO_PAR_PSC3   (MCF_MBAR + 0xA4C)
+#define MCFGPIO_PAR_DSPI   (MCF_MBAR + 0xA50)
+#define MCFGPIO_PAR_TIMER  (MCF_MBAR + 0xA52)
+
 #define MCF_PAR_SDA(0x0008)
 #define MCF_PAR_SCL(0x0004)
 #define MCF_PAR_PSC_TXD(0x04)
 #define MCF_PAR_PSC_RXD(0x08)
-#define MCF_PAR_PSC_RTS(x) (((x)&0x03)<<4)
-#define MCF_PAR_PSC_CTS(x) (((x)&0x03)<<6)
 #define MCF_PAR_PSC_CTS_GPIO   (0x00)
 #define MCF_PAR_PSC_CTS_BCLK   (0x80)
 #define MCF_PAR_PSC_CTS_CTS(0xC0)
@@ -87,7 +97,4 @@
 #define MCF_PAR_PSC_RTS_RTS(0x30)
 #define MCF_PAR_PSC_CANRX  (0x40)
 
-#define MCF_PAR_PCIBG  (CONFIG_MBAR + 0xa48)   /* PCI bus grant */
-#define MCF_PAR_PCIBR  (CONFIG_MBAR + 0xa4a)   /* PCI */
-
 #endif /* m54xxsim_h */
diff --git a/arch/m68k/platform/coldfire/m54xx.c 
b/arch/m68k/platform/coldfire/m54xx.c
index 2081c6c..1f7c7fd 100644
--- a/arch/m68k/platform/coldfire/m54xx.c
+++ b/arch/m68k/platform/coldfire/m54xx.c
@@ -30,14 +30,12 @@
 static void __init m54xx_uarts_init(void)
 {
/* enable io pins */
-   __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD,
-   MCF_MBAR + MCF_PAR_PSC(0));
+   __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC0);
__raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS,
-   MCF_MBAR + MCF_PAR_PSC(1));
+   MCFGPIO_PAR_PSC1);
__raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS |
-   MCF_PAR_PSC_CTS_CTS, MCF_MBAR + MCF_PAR_PSC(2));
-   __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD,
-   MCF_MBAR + MCF_PAR_PSC(3));
+   MCF_PAR_PSC_CTS_CTS, MCFGPIO_PAR_PSC2);
+   __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC3);
 }
 
 /***/
diff --git a/arch/m68k/platform/coldfire/pci.c 
b/arch/m68k/platform/coldfire/pci.c
index 553210d..8572246 100644
--- a/arch/m68k/platform/coldfire/pci.c
+++ b/arch/m68k/platform/coldfire/pci.c
@@ -272,8 +272,8 @@ static int __init mcf_pci_init(void)
PACR_EXTMINTE(0x1f), PACR);
 
/* Set required multi-function pins for PCI bus use */
-   __raw_writew(0x3ff, MCF_PAR_PCIBG);
-   __raw_writew(0x3ff, MCF_PAR_PCIBR);
+   __raw_writew(0x3ff, MCFGPIO_PAR_PCIBG);
+   __raw_writew(0x3ff, MCFGPIO_PAR_PCIBR);
 
/* Set up config space for local host bus controller */
__raw_writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
-- 
1.7.0.4

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[uClinux-dev] [PATCH 07/11] m68knommu: use read/write IO access functions in ColdFire m532x setup code

2012-09-20 Thread gerg 
From: Greg Ungerer 

Get rid of the use of local IO access macros and switch to using the standard
read*/write* family of access functions for the ColdFire m532x setup code.

Signed-off-by: Greg Ungerer 
---
 arch/m68k/include/asm/m532xsim.h|  104 +---
 arch/m68k/platform/coldfire/m532x.c |  183 +--
 2 files changed, 139 insertions(+), 148 deletions(-)

diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h
index d4092fa..8668e47 100644
--- a/arch/m68k/include/asm/m532xsim.h
+++ b/arch/m68k/include/asm/m532xsim.h
@@ -15,10 +15,6 @@
 
 #include 
 
-#define MCF_REG32(x) (*(volatile unsigned long  *)(x))
-#define MCF_REG16(x) (*(volatile unsigned short *)(x))
-#define MCF_REG08(x) (*(volatile unsigned char  *)(x))
-
 #define MCFINT_VECBASE  64
 #define MCFINT_UART026  /* Interrupt number for UART0 */
 #define MCFINT_UART127  /* Interrupt number for UART1 */
@@ -38,7 +34,7 @@
 
 #defineMCF_IRQ_QSPI(MCFINT_VECBASE + MCFINT_QSPI)
 
-#define MCF_WTM_WCRMCF_REG16(0xFC098000)
+#define MCF_WTM_WCR0xFC098000
 
 /*
  * Define the 532x SIM register set addresses.
@@ -181,13 +177,13 @@
  */
 
 /* Register read/write macros */
-#define MCF_CCM_CCR   MCF_REG16(0xFC0A0004)
-#define MCF_CCM_RCON  MCF_REG16(0xFC0A0008)
-#define MCF_CCM_CIR   MCF_REG16(0xFC0A000A)
-#define MCF_CCM_MISCCRMCF_REG16(0xFC0A0010)
-#define MCF_CCM_CDR   MCF_REG16(0xFC0A0012)
-#define MCF_CCM_UHCSR MCF_REG16(0xFC0A0014)
-#define MCF_CCM_UOCSR MCF_REG16(0xFC0A0016)
+#define MCF_CCM_CCR   0xFC0A0004
+#define MCF_CCM_RCON  0xFC0A0008
+#define MCF_CCM_CIR   0xFC0A000A
+#define MCF_CCM_MISCCR0xFC0A0010
+#define MCF_CCM_CDR   0xFC0A0012
+#define MCF_CCM_UHCSR 0xFC0A0014
+#define MCF_CCM_UOCSR 0xFC0A0016
 
 /* Bit definitions and macros for MCF_CCM_CCR */
 #define MCF_CCM_CCR_RESERVED  (0x0001)
@@ -256,27 +252,24 @@
  */
 
 /* Register read/write macros */
-#define MCF_FBCS0_CSAR MCF_REG32(0xFC008000)
-#define MCF_FBCS0_CSMR MCF_REG32(0xFC008004)
-#define MCF_FBCS0_CSCR MCF_REG32(0xFC008008)
-#define MCF_FBCS1_CSAR MCF_REG32(0xFC00800C)
-#define MCF_FBCS1_CSMR MCF_REG32(0xFC008010)
-#define MCF_FBCS1_CSCR MCF_REG32(0xFC008014)
-#define MCF_FBCS2_CSAR MCF_REG32(0xFC008018)
-#define MCF_FBCS2_CSMR MCF_REG32(0xFC00801C)
-#define MCF_FBCS2_CSCR MCF_REG32(0xFC008020)
-#define MCF_FBCS3_CSAR MCF_REG32(0xFC008024)
-#define MCF_FBCS3_CSMR MCF_REG32(0xFC008028)
-#define MCF_FBCS3_CSCR MCF_REG32(0xFC00802C)
-#define MCF_FBCS4_CSAR MCF_REG32(0xFC008030)
-#define MCF_FBCS4_CSMR MCF_REG32(0xFC008034)
-#define MCF_FBCS4_CSCR MCF_REG32(0xFC008038)
-#define MCF_FBCS5_CSAR MCF_REG32(0xFC00803C)
-#define MCF_FBCS5_CSMR MCF_REG32(0xFC008040)
-#define MCF_FBCS5_CSCR MCF_REG32(0xFC008044)
-#define MCF_FBCS_CSAR(x)   MCF_REG32(0xFC008000+((x)*0x00C))
-#define MCF_FBCS_CSMR(x)   MCF_REG32(0xFC008004+((x)*0x00C))
-#define MCF_FBCS_CSCR(x)   MCF_REG32(0xFC008008+((x)*0x00C))
+#define MCF_FBCS0_CSAR 0xFC008000
+#define MCF_FBCS0_CSMR 0xFC008004
+#define MCF_FBCS0_CSCR 0xFC008008
+#define MCF_FBCS1_CSAR 0xFC00800C
+#define MCF_FBCS1_CSMR 0xFC008010
+#define MCF_FBCS1_CSCR 0xFC008014
+#define MCF_FBCS2_CSAR 0xFC008018
+#define MCF_FBCS2_CSMR 0xFC00801C
+#define MCF_FBCS2_CSCR 0xFC008020
+#define MCF_FBCS3_CSAR 0xFC008024
+#define MCF_FBCS3_CSMR 0xFC008028
+#define MCF_FBCS3_CSCR 0xFC00802C
+#define MCF_FBCS4_CSAR 0xFC008030
+#define MCF_FBCS4_CSMR 0xFC008034
+#define MCF_FBCS4_CSCR 0xFC008038
+#define MCF_FBCS5_CSAR 0xFC00803C
+#define MCF_FBCS5_CSMR 0xFC008040
+#define MCF_FBCS5_CSCR 0xFC008044
 
 /* Bit definitions and macros for MCF_FBCS_CSAR */
 #define MCF_FBCS_CSAR_BA(x)((x)&0x)
@@ -1114,10 +1107,10 @@
  */
 
 /* Register read/write macros */
-#define MCF_PLL_PODR  MCF_REG08(0xFC0C)
-#define MCF_PLL_PLLCR MCF_REG08(0xFC0C0004)
-#define MCF_PLL_PMDR  MCF_REG08(0xFC0C0008)
-#define MCF_PLL_PFDR  MCF_REG08(0xFC0C000C)
+#define MCF_PLL_PODR  0xFC0C
+#define MCF_PLL_PLLCR 0xFC0C0004
+#define MCF_PLL_PMDR  0xFC0C0008
+#define MCF_PLL_PFDR  0xFC0C000C
 
 /* Bit definitions and macros for MCF_PLL_PODR */
 #define MCF_PLL_PODR_BUSDIV(x)(((x)&0x0F)<<0)
@@ -114

[uClinux-dev] [PATCH 09/11] m68knommu: fix multi-function pin setup for FEC module on ColdFire 523x

2012-09-20 Thread gerg 
From: Greg Ungerer 

The multi-function pin setup code for the FEC ethernet module is using just
plain wrong. Looks like it was cut-and-pasted from other init code. It has
hard coded register addresses that are incorrect for the 523x, and it is
manipulating bits that don't make sense.

Add proper register definitions for the Pin Assignment registers of the 532x,
and then use them to fix the setup code for the FEC hardware module.

Signed-off-by: Greg Ungerer 
---
 arch/m68k/include/asm/m523xsim.h|8 
 arch/m68k/platform/coldfire/m523x.c |8 +---
 2 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h
index 91d3abc..d1d4ec7 100644
--- a/arch/m68k/include/asm/m523xsim.h
+++ b/arch/m68k/include/asm/m523xsim.h
@@ -189,8 +189,16 @@
 /*
  * Pin Assignment
 */
+#defineMCFGPIO_PAR_AD  (MCF_IPSBAR + 0x100040)
+#defineMCFGPIO_PAR_BUSCTL  (MCF_IPSBAR + 0x100042)
+#defineMCFGPIO_PAR_BS  (MCF_IPSBAR + 0x100044)
+#defineMCFGPIO_PAR_CS  (MCF_IPSBAR + 0x100045)
+#defineMCFGPIO_PAR_SDRAM   (MCF_IPSBAR + 0x100046)
+#defineMCFGPIO_PAR_FECI2C  (MCF_IPSBAR + 0x100047)
+#defineMCFGPIO_PAR_UART(MCF_IPSBAR + 0x100048)
 #defineMCFGPIO_PAR_QSPI(MCF_IPSBAR + 0x10004A)
 #defineMCFGPIO_PAR_TIMER   (MCF_IPSBAR + 0x10004C)
+#defineMCFGPIO_PAR_ETPU(MCF_IPSBAR + 0x10004E)
 
 /*
  * DMA unit base addresses.
diff --git a/arch/m68k/platform/coldfire/m523x.c 
b/arch/m68k/platform/coldfire/m523x.c
index d47dfd8..ff37fe9 100644
--- a/arch/m68k/platform/coldfire/m523x.c
+++ b/arch/m68k/platform/coldfire/m523x.c
@@ -42,14 +42,8 @@ static void __init m523x_qspi_init(void)
 
 static void __init m523x_fec_init(void)
 {
-   u16 par;
-   u8 v;
-
/* Set multi-function pins to ethernet use */
-   par = readw(MCF_IPSBAR + 0x100082);
-   writew(par | 0xf00, MCF_IPSBAR + 0x100082);
-   v = readb(MCF_IPSBAR + 0x100078);
-   writeb(v | 0xc0, MCF_IPSBAR + 0x100078);
+   writeb(readb(MCFGPIO_PAR_FECI2C) | 0xf0, MCFGPIO_PAR_FECI2C);
 }
 
 /***/
-- 
1.7.0.4

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[uClinux-dev] [PATCH 08/11] m68knommu: move ColdFire slice timer address defiens to 54xx header

2012-09-20 Thread gerg 
From: Greg Ungerer 

Move the base address defines of the ColdFire 54xx CPU slice timers into the
54xx specific header (m54xxsim.h). They are CPU specific, and belong with the
CPU specific defines. Also make them relative to the MBAR peripheral region,
making the define the absolute address.

Signed-off-by: Greg Ungerer 
---
 arch/m68k/include/asm/m54xxsim.h   |6 ++
 arch/m68k/include/asm/mcfslt.h |7 ---
 arch/m68k/platform/coldfire/sltimers.c |4 ++--
 3 files changed, 8 insertions(+), 9 deletions(-)

diff --git a/arch/m68k/include/asm/m54xxsim.h b/arch/m68k/include/asm/m54xxsim.h
index d3c5e0d..d6a5079 100644
--- a/arch/m68k/include/asm/m54xxsim.h
+++ b/arch/m68k/include/asm/m54xxsim.h
@@ -47,6 +47,12 @@
 #define MCF_IRQ_UART3  (MCFINT_VECBASE + 32)
 
 /*
+ * Slice Timer support.
+ */
+#define MCFSLT_TIMER0  (MCF_MBAR + 0x900)  /* Base addr TIMER0 */
+#define MCFSLT_TIMER1  (MCF_MBAR + 0x910)  /* Base addr TIMER1 */
+
+/*
  * Generic GPIO support
  */
 #define MCFGPIO_PIN_MAX0   /* I am too lazy to count */
diff --git a/arch/m68k/include/asm/mcfslt.h b/arch/m68k/include/asm/mcfslt.h
index d0d0ecb..c2314b6 100644
--- a/arch/m68k/include/asm/mcfslt.h
+++ b/arch/m68k/include/asm/mcfslt.h
@@ -13,13 +13,6 @@
 //
 
 /*
- * Get address specific defines for the 547x.
- */
-#define MCFSLT_TIMER0  0x900   /* Base address of TIMER0 */
-#define MCFSLT_TIMER1  0x910   /* Base address of TIMER1 */
-
-
-/*
  * Define the SLT timer register set addresses.
  */
 #define MCFSLT_STCNT   0x00/* Terminal count */
diff --git a/arch/m68k/platform/coldfire/sltimers.c 
b/arch/m68k/platform/coldfire/sltimers.c
index 2027fc2..bb5a25a 100644
--- a/arch/m68k/platform/coldfire/sltimers.c
+++ b/arch/m68k/platform/coldfire/sltimers.c
@@ -32,7 +32,7 @@
 /*
  * By default use Slice Timer 1 as the profiler clock timer.
  */
-#definePA(a)   (MCF_MBAR + MCFSLT_TIMER1 + (a))
+#definePA(a)   (MCFSLT_TIMER1 + (a))
 
 /*
  * Choose a reasonably fast profile timer. Make it an odd value to
@@ -76,7 +76,7 @@ void mcfslt_profile_init(void)
 /*
  * By default use Slice Timer 0 as the system clock timer.
  */
-#defineTA(a)   (MCF_MBAR + MCFSLT_TIMER0 + (a))
+#defineTA(a)   (MCFSLT_TIMER0 + (a))
 
 static u32 mcfslt_cycles_per_jiffy;
 static u32 mcfslt_cnt;
-- 
1.7.0.4

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[uClinux-dev] [PATCH 01/11] m68knommu: fix wrong register offsets used for ColdFire 5272 multi-function pins

2012-09-20 Thread gerg 
From: Greg Ungerer 

The registers used to configure and set the multifunction pins on the 5272
ColdFire are defined as absolute addresses. So the use of them does not need
to be offset relative to the peripheral region address.

Fix two cases of incorrect usage of these addresses. Both affect UART
initialization, one in the common UART pin setup code, the other in the
NETtel board specific UART signal handling.

Signed-off-by: Greg Ungerer 
---
 arch/m68k/include/asm/nettel.h  |9 +++--
 arch/m68k/platform/coldfire/m5272.c |8 
 2 files changed, 7 insertions(+), 10 deletions(-)

diff --git a/arch/m68k/include/asm/nettel.h b/arch/m68k/include/asm/nettel.h
index 4dec2d9..2a7a766 100644
--- a/arch/m68k/include/asm/nettel.h
+++ b/arch/m68k/include/asm/nettel.h
@@ -21,6 +21,7 @@
 #ifdef CONFIG_COLDFIRE
 #include 
 #include 
+#include 
 #endif
 
 /*---*/
@@ -86,16 +87,12 @@ static __inline__ void mcf_setppdata(unsigned int mask, 
unsigned int bits)
  */
 static __inline__ unsigned int mcf_getppdata(void)
 {
-   volatile unsigned short *pp;
-   pp = (volatile unsigned short *) (MCF_MBAR + MCFSIM_PBDAT);
-   return((unsigned int) *pp);
+   return readw(MCFSIM_PBDAT);
 }
 
 static __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits)
 {
-   volatile unsigned short *pp;
-   pp = (volatile unsigned short *) (MCF_MBAR + MCFSIM_PBDAT);
-   *pp = (*pp & ~mask) | bits;
+   write((readw(MCFSIM_PBDAT) & ~mask) | bits, MCFSIM_PBDAT);
 }
 #endif
 
diff --git a/arch/m68k/platform/coldfire/m5272.c 
b/arch/m68k/platform/coldfire/m5272.c
index eae59f6..45b246d 100644
--- a/arch/m68k/platform/coldfire/m5272.c
+++ b/arch/m68k/platform/coldfire/m5272.c
@@ -35,13 +35,13 @@ static void __init m5272_uarts_init(void)
u32 v;
 
/* Enable the output lines for the serial ports */
-   v = readl(MCF_MBAR + MCFSIM_PBCNT);
+   v = readl(MCFSIM_PBCNT);
v = (v & ~0x00ff) | 0x0055;
-   writel(v, MCF_MBAR + MCFSIM_PBCNT);
+   writel(v, MCFSIM_PBCNT);
 
-   v = readl(MCF_MBAR + MCFSIM_PDCNT);
+   v = readl(MCFSIM_PDCNT);
v = (v & ~0x03fc) | 0x02a8;
-   writel(v, MCF_MBAR + MCFSIM_PDCNT);
+   writel(v, MCFSIM_PDCNT);
 }
 
 /***/
-- 
1.7.0.4

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[uClinux-dev] [PATCH 03/11] m68knommu: remove address offsets relative to IPSBAR for ColdFire 527x

2012-09-20 Thread gerg 
From: Greg Ungerer 

Remove the last address definitions relative to the IPSBAR peripheral region
for the ColdFire 527x family. This involved cleaning up some magic numbers
used in the code part, and making them proper register definitions in the 527x
specific header.

This is part of the process of cleaning up the ColdFire register definitions
to make them consistently use absolute addresses for the primary registers.
This will reduce the occasional bugs caused by inconsistent definition of
the register addresses.

Signed-off-by: Greg Ungerer 
---
 arch/m68k/include/asm/m527xsim.h|   52 +++
 arch/m68k/platform/coldfire/m527x.c |   24 
 2 files changed, 46 insertions(+), 30 deletions(-)

diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
index 71aa510..6335e42 100644
--- a/arch/m68k/include/asm/m527xsim.h
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -194,9 +194,23 @@
 #define MCFGPIO_IRQ_MAX8
 #define MCFGPIO_IRQ_VECBASEMCFINT_VECBASE
 
+/*
+ * Port Pin Assignment registers.
+ */
+#define MCFGPIO_PAR_AD (MCF_IPSBAR + 0x100040)
+#define MCFGPIO_PAR_BUSCTL (MCF_IPSBAR + 0x100042)
+#define MCFGPIO_PAR_BS (MCF_IPSBAR + 0x100044)
+#define MCFGPIO_PAR_CS (MCF_IPSBAR + 0x100045)
+#define MCFGPIO_PAR_SDRAM  (MCF_IPSBAR + 0x100046)
+#define MCFGPIO_PAR_FECI2C (MCF_IPSBAR + 0x100047)
+#define MCFGPIO_PAR_UART   (MCF_IPSBAR + 0x100048)
 #define MCFGPIO_PAR_QSPI   (MCF_IPSBAR + 0x10004A)
 #define MCFGPIO_PAR_TIMER  (MCF_IPSBAR + 0x10004C)
-#endif
+
+#define UART0_ENABLE_MASK  0x000f
+#define UART1_ENABLE_MASK  0x0ff0
+#define UART2_ENABLE_MASK  0x3000
+#endif /* CONFIG_M5271 */
 
 #ifdef CONFIG_M5275
 #define MCFGPIO_PODR_BUSCTL(MCF_IPSBAR + 0x14)
@@ -289,8 +303,26 @@
 #define MCFGPIO_IRQ_MAX8
 #define MCFGPIO_IRQ_VECBASEMCFINT_VECBASE
 
+/*
+ * Port Pin Assignment registers.
+ */
+#define MCFGPIO_PAR_AD (MCF_IPSBAR + 0x100070)
+#define MCFGPIO_PAR_CS (MCF_IPSBAR + 0x100071)
+#define MCFGPIO_PAR_BUSCTL (MCF_IPSBAR + 0x100072)
+#define MCFGPIO_PAR_USB(MCF_IPSBAR + 0x100076)
+#define MCFGPIO_PAR_FEC0HL (MCF_IPSBAR + 0x100078)
+#define MCFGPIO_PAR_FEC1HL (MCF_IPSBAR + 0x100079)
+#define MCFGPIO_PAR_TIMER  (MCF_IPSBAR + 0x10007A)
+#define MCFGPIO_PAR_UART   (MCF_IPSBAR + 0x10007C)
 #define MCFGPIO_PAR_QSPI   (MCF_IPSBAR + 0x10007E)
-#endif
+#define MCFGPIO_PAR_SDRAM  (MCF_IPSBAR + 0x100080)
+#define MCFGPIO_PAR_FECI2C (MCF_IPSBAR + 0x100082)
+#define MCFGPIO_PAR_BS (MCF_IPSBAR + 0x100084)
+
+#define UART0_ENABLE_MASK  0x000f
+#define UART1_ENABLE_MASK  0x00f0
+#define UART2_ENABLE_MASK  0x3f00
+#endif /* CONFIG_M5275 */
 
 /*
  * PIT timer base addresses.
@@ -311,22 +343,6 @@
 #define MCFEPORT_EPFR  (MCF_IPSBAR + 0x130006)
 
 /*
- * GPIO pins setups to enable the UARTs.
- */
-#ifdef CONFIG_M5271
-#define MCF_GPIO_PAR_UART  0x100048/* PAR UART address */
-#define UART0_ENABLE_MASK  0x000f
-#define UART1_ENABLE_MASK  0x0ff0
-#define UART2_ENABLE_MASK  0x3000
-#endif
-#ifdef CONFIG_M5275
-#define MCF_GPIO_PAR_UART  0x10007c/* PAR UART address */
-#define UART0_ENABLE_MASK  0x000f
-#define UART1_ENABLE_MASK  0x00f0
-#define UART2_ENABLE_MASK  0x3f00 
-#endif
-
-/*
  *  Reset Control Unit (relative to IPSBAR).
  */
 #defineMCF_RCR (MCF_IPSBAR + 0x11)
diff --git a/arch/m68k/platform/coldfire/m527x.c 
b/arch/m68k/platform/coldfire/m527x.c
index b3cb378..1431ba0 100644
--- a/arch/m68k/platform/coldfire/m527x.c
+++ b/arch/m68k/platform/coldfire/m527x.c
@@ -53,9 +53,9 @@ static void __init m527x_uarts_init(void)
/*
 * External Pin Mask Setting & Enable External Pin for Interface
 */
-   sepmask = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART);
+   sepmask = readw(MCFGPIO_PAR_UART);
sepmask |= UART0_ENABLE_MASK | UART1_ENABLE_MASK | UART2_ENABLE_MASK;
-   writew(sepmask, MCF_IPSBAR + MCF_GPIO_PAR_UART);
+   writew(sepmask, MCFGPIO_PAR_UART);
 }
 
 /***/
@@ -67,19 +67,19 @@ static void __init m527x_fec_init(void)
 
/* Set multi-function pins to ethernet mode for fec0 */
 #if defined(CONFIG_M5271)
-   v = readb(MCF_IPSBAR + 0x100047);
-   writeb(v | 0xf0, MCF_IPSBAR + 0x100047);
+   v = readb(MCFGPIO_PAR_FECI2C);
+   writeb(v | 0xf0, MCFGPIO_PAR_FECI2C);
 #else
-   par = readw(MCF_IPSBAR + 0x100082);
-   writew(par | 0xf00, MCF_IPSBAR + 0x100082);
-   v = readb(MCF_IPSBAR + 0x100078);
-   writeb(v | 0xc0, MCF_IPSBAR + 0x100078);
+   par = readw(MCFGPIO_PAR_FECI2C);
+   writew(par | 0xf00, MCFGPIO_PAR_FECI2C);
+   v = readb(MCFGPIO_PAR_FEC0HL);
+   writeb(v | 0xc0, MCFGPIO_PAR_FEC0HL);

[uClinux-dev] [PATCH 06/11] m68knommu: modify ColdFire 532x GPIO register definitions to be consistent

2012-09-20 Thread gerg 
From: Greg Ungerer 

The ColdFire 532x CPU register definitions for the multi-function setup
pins are inconsistently defined compared with other ColdFire parts. Modify
the register defintions to be just the addresses, not pointers. This also
fixes the erroneous use in one case of using these values in the UART setup
code for the 532x.

Signed-off-by: Greg Ungerer 
---
 arch/m68k/include/asm/m532xsim.h|   52 +-
 arch/m68k/platform/coldfire/m532x.c |   38 +++---
 2 files changed, 48 insertions(+), 42 deletions(-)

diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h
index 3833370..d4092fa 100644
--- a/arch/m68k/include/asm/m532xsim.h
+++ b/arch/m68k/include/asm/m532xsim.h
@@ -393,32 +393,32 @@
 #define MCFGPIO_PCLRR_LCDDATAL (0xFC0A404B)
 #define MCFGPIO_PCLRR_LCDCTLH  (0xFC0A404C)
 #define MCFGPIO_PCLRR_LCDCTLL  (0xFC0A404D)
-#define MCF_GPIO_PAR_FEC   MCF_REG08(0xFC0A4050)
-#define MCF_GPIO_PAR_PWM   MCF_REG08(0xFC0A4051)
-#define MCF_GPIO_PAR_BUSCTLMCF_REG08(0xFC0A4052)
-#define MCF_GPIO_PAR_FECI2CMCF_REG08(0xFC0A4053)
-#define MCF_GPIO_PAR_BEMCF_REG08(0xFC0A4054)
-#define MCF_GPIO_PAR_CSMCF_REG08(0xFC0A4055)
-#define MCF_GPIO_PAR_SSI   MCF_REG16(0xFC0A4056)
-#define MCF_GPIO_PAR_UART  MCF_REG16(0xFC0A4058)
-#define MCF_GPIO_PAR_QSPI  MCF_REG16(0xFC0A405A)
-#define MCF_GPIO_PAR_TIMER MCF_REG08(0xFC0A405C)
-#define MCF_GPIO_PAR_LCDDATA   MCF_REG08(0xFC0A405D)
-#define MCF_GPIO_PAR_LCDCTLMCF_REG16(0xFC0A405E)
-#define MCF_GPIO_PAR_IRQ   MCF_REG16(0xFC0A4060)
-#define MCF_GPIO_MSCR_FLEXBUS  MCF_REG08(0xFC0A4064)
-#define MCF_GPIO_MSCR_SDRAMMCF_REG08(0xFC0A4065)
-#define MCF_GPIO_DSCR_I2C  MCF_REG08(0xFC0A4068)
-#define MCF_GPIO_DSCR_PWM  MCF_REG08(0xFC0A4069)
-#define MCF_GPIO_DSCR_FEC  MCF_REG08(0xFC0A406A)
-#define MCF_GPIO_DSCR_UART MCF_REG08(0xFC0A406B)
-#define MCF_GPIO_DSCR_QSPI MCF_REG08(0xFC0A406C)
-#define MCF_GPIO_DSCR_TIMERMCF_REG08(0xFC0A406D)
-#define MCF_GPIO_DSCR_SSI  MCF_REG08(0xFC0A406E)
-#define MCF_GPIO_DSCR_LCD  MCF_REG08(0xFC0A406F)
-#define MCF_GPIO_DSCR_DEBUGMCF_REG08(0xFC0A4070)
-#define MCF_GPIO_DSCR_CLKRST   MCF_REG08(0xFC0A4071)
-#define MCF_GPIO_DSCR_IRQ  MCF_REG08(0xFC0A4072)
+#define MCFGPIO_PAR_FEC(0xFC0A4050)
+#define MCFGPIO_PAR_PWM(0xFC0A4051)
+#define MCFGPIO_PAR_BUSCTL (0xFC0A4052)
+#define MCFGPIO_PAR_FECI2C (0xFC0A4053)
+#define MCFGPIO_PAR_BE (0xFC0A4054)
+#define MCFGPIO_PAR_CS (0xFC0A4055)
+#define MCFGPIO_PAR_SSI(0xFC0A4056)
+#define MCFGPIO_PAR_UART   (0xFC0A4058)
+#define MCFGPIO_PAR_QSPI   (0xFC0A405A)
+#define MCFGPIO_PAR_TIMER  (0xFC0A405C)
+#define MCFGPIO_PAR_LCDDATA(0xFC0A405D)
+#define MCFGPIO_PAR_LCDCTL (0xFC0A405E)
+#define MCFGPIO_PAR_IRQ(0xFC0A4060)
+#define MCFGPIO_MSCR_FLEXBUS   (0xFC0A4064)
+#define MCFGPIO_MSCR_SDRAM (0xFC0A4065)
+#define MCFGPIO_DSCR_I2C   (0xFC0A4068)
+#define MCFGPIO_DSCR_PWM   (0xFC0A4069)
+#define MCFGPIO_DSCR_FEC   (0xFC0A406A)
+#define MCFGPIO_DSCR_UART  (0xFC0A406B)
+#define MCFGPIO_DSCR_QSPI  (0xFC0A406C)
+#define MCFGPIO_DSCR_TIMER (0xFC0A406D)
+#define MCFGPIO_DSCR_SSI   (0xFC0A406E)
+#define MCFGPIO_DSCR_LCD   (0xFC0A406F)
+#define MCFGPIO_DSCR_DEBUG (0xFC0A4070)
+#define MCFGPIO_DSCR_CLKRST(0xFC0A4071)
+#define MCFGPIO_DSCR_IRQ   (0xFC0A4072)
 
 /* Bit definitions and macros for MCF_GPIO_PODR_FECH */
 #define MCF_GPIO_PODR_FECH_PODR_FECH0  (0x01)
diff --git a/arch/m68k/platform/coldfire/m532x.c 
b/arch/m68k/platform/coldfire/m532x.c
index 4819a44..0adeef1 100644
--- a/arch/m68k/platform/coldfire/m532x.c
+++ b/arch/m68k/platform/coldfire/m532x.c
@@ -172,7 +172,7 @@ static void __init m532x_clk_init(void)
 static void __init m532x_qspi_init(void)
 {
/* setup QSPS pins for QSPI with gpio CS control */
-   writew(0x01f0, MCF_GPIO_PAR_QSPI);
+   writew(0x01f0, MCFGPIO_PAR_QSPI);
 }
 
 #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
@@ -182,18 +182,24 @@ static void __init m532x_qspi_init(void)
 static void __init m532x_uarts_init(void)
 {
/* UART GPIO initialization */
-   MCF_GPIO_PAR_UART |= 0x0FFF;
+   writew(readw(MCFGPIO_PAR_UART) | 0x0FFF, MCFGPIO_PAR_UART);
 }
 
 /***/
 
 static void __init m532x_fec_init(void)
 {
+

[uClinux-dev] [PATCH 05/11] m68knommu: remove a lot of unsed definitions for 532x ColdFire

2012-09-20 Thread gerg 
From: Greg Ungerer 

There are a lot of unused and uneccessary definitions in the header to
support the ColdFire 532x CPU family. Remove the junk.

Signed-off-by: Greg Ungerer 
---
 arch/m68k/include/asm/m532xsim.h | 1033 +-
 1 files changed, 1 insertions(+), 1032 deletions(-)

diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h
index 5ca7b29..3833370 100644
--- a/arch/m68k/include/asm/m532xsim.h
+++ b/arch/m68k/include/asm/m532xsim.h
@@ -152,42 +152,6 @@
 #define MCFPM_PPMHR1   0xfc040038
 #define MCFPM_LPCR 0xec090007
 
-/*
- *
- * Inter-IC (I2C) Module
- *
- */
-
-/* Read/Write access macros for general use */
-#define MCF532x_I2C_I2ADR   (volatile u8 *) (0xFC058000) // Address 
-#define MCF532x_I2C_I2FDR   (volatile u8 *) (0xFC058004) // Freq Divider
-#define MCF532x_I2C_I2CR(volatile u8 *) (0xFC058008) // Control
-#define MCF532x_I2C_I2SR(volatile u8 *) (0xFC05800C) // Status
-#define MCF532x_I2C_I2DR(volatile u8 *) (0xFC058010) // Data I/O
-
-/* Bit level definitions and macros */
-#define MCF532x_I2C_I2ADR_ADDR(x)   (((x)&0x7F)<<0x01)
-
-#define MCF532x_I2C_I2FDR_IC(x) (((x)&0x3F))
-
-#define MCF532x_I2C_I2CR_IEN(0x80) // I2C enable
-#define MCF532x_I2C_I2CR_IIEN   (0x40)  // interrupt enable
-#define MCF532x_I2C_I2CR_MSTA   (0x20)  // master/slave mode
-#define MCF532x_I2C_I2CR_MTX(0x10)  // transmit/receive mode
-#define MCF532x_I2C_I2CR_TXAK   (0x08)  // transmit acknowledge enable
-#define MCF532x_I2C_I2CR_RSTA   (0x04)  // repeat start
-
-#define MCF532x_I2C_I2SR_ICF(0x80)  // data transfer bit
-#define MCF532x_I2C_I2SR_IAAS   (0x40)  // I2C addressed as a slave
-#define MCF532x_I2C_I2SR_IBB(0x20)  // I2C bus busy
-#define MCF532x_I2C_I2SR_IAL(0x10)  // aribitration lost
-#define MCF532x_I2C_I2SR_SRW(0x04)  // slave read/write
-#define MCF532x_I2C_I2SR_IIF(0x02)  // I2C interrupt
-#define MCF532x_I2C_I2SR_RXAK   (0x01)  // received acknowledge
-
-#define MCF532x_PAR_FECI2C (volatile u8 *) (0xFC0A4053)
-
-
 /*
  * The M5329EVB board needs a help getting its devices initialized 
  * at kernel start time if dBUG doesn't set it up (for example 
@@ -287,78 +251,6 @@
 
 /*
  *
- * DMA Timers (DTIM)
- *
- */
-
-/* Register read/write macros */
-#define MCF_DTIM0_DTMR   MCF_REG16(0xFC07)
-#define MCF_DTIM0_DTXMR  MCF_REG08(0xFC070002)
-#define MCF_DTIM0_DTER   MCF_REG08(0xFC070003)
-#define MCF_DTIM0_DTRR   MCF_REG32(0xFC070004)
-#define MCF_DTIM0_DTCR   MCF_REG32(0xFC070008)
-#define MCF_DTIM0_DTCN   MCF_REG32(0xFC07000C)
-#define MCF_DTIM1_DTMR   MCF_REG16(0xFC074000)
-#define MCF_DTIM1_DTXMR  MCF_REG08(0xFC074002)
-#define MCF_DTIM1_DTER   MCF_REG08(0xFC074003)
-#define MCF_DTIM1_DTRR   MCF_REG32(0xFC074004)
-#define MCF_DTIM1_DTCR   MCF_REG32(0xFC074008)
-#define MCF_DTIM1_DTCN   MCF_REG32(0xFC07400C)
-#define MCF_DTIM2_DTMR   MCF_REG16(0xFC078000)
-#define MCF_DTIM2_DTXMR  MCF_REG08(0xFC078002)
-#define MCF_DTIM2_DTER   MCF_REG08(0xFC078003)
-#define MCF_DTIM2_DTRR   MCF_REG32(0xFC078004)
-#define MCF_DTIM2_DTCR   MCF_REG32(0xFC078008)
-#define MCF_DTIM2_DTCN   MCF_REG32(0xFC07800C)
-#define MCF_DTIM3_DTMR   MCF_REG16(0xFC07C000)
-#define MCF_DTIM3_DTXMR  MCF_REG08(0xFC07C002)
-#define MCF_DTIM3_DTER   MCF_REG08(0xFC07C003)
-#define MCF_DTIM3_DTRR   MCF_REG32(0xFC07C004)
-#define MCF_DTIM3_DTCR   MCF_REG32(0xFC07C008)
-#define MCF_DTIM3_DTCN   MCF_REG32(0xFC07C00C)
-#define MCF_DTIM_DTMR(x) MCF_REG16(0xFC07+((x)*0x4000))
-#define MCF_DTIM_DTXMR(x)MCF_REG08(0xFC070002+((x)*0x4000))
-#define MCF_DTIM_DTER(x) MCF_REG08(0xFC070003+((x)*0x4000))
-#define MCF_DTIM_DTRR(x) MCF_REG32(0xFC070004+((x)*0x4000))
-#define MCF_DTIM_DTCR(x) MCF_REG32(0xFC070008+((x)*0x4000))
-#define MCF_DTIM_DTCN(x) MCF_REG32(0xFC07000C+((x)*0x4000))
-
-/* Bit definitions and macros for MCF_DTIM_DTMR */
-#define MCF_DTIM_DTMR_RST(0x0001)
-#define MCF_DTIM_DTMR_CLK(x) (((x)&0x0003)<<1)
-#define MCF_DTIM_DTMR_FRR(0x0008)
-#define MCF_DTIM_DTMR_ORRI   (0x0010)
-#define MCF_DTIM_DTMR_OM (0x0020)
-#define MCF_DTIM_DTMR_CE(x)  (((x)&0x0003)<<6)
-#define MCF_DTIM_DTMR_PS(x)  (((x)&0x00FF)<<8)
-#define MCF_DTIM_DTMR_CE_ANY (0x00C0)
-#define MCF_DTIM_DTMR_CE_FALL(0x0080)
-#define MCF_DTIM_DTMR_CE_RISE(0x0040)
-#define MCF_DTIM_DTMR_CE_NONE(0x)
-#define MCF_DTIM_DTMR_CLK_

[uClinux-dev] [PATCH 04/11] m68knommu: use definitions for the ColdFire 528x FEC multi-function pins

2012-09-20 Thread gerg 
From: Greg Ungerer 

Currently the setup code for the FEC multi-function pins on the ColdFire 528x
has the addresses hard coded in the code. Use the register defines that
already exist for this.

Signed-off-by: Greg Ungerer 
---
 arch/m68k/platform/coldfire/m528x.c |6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/m68k/platform/coldfire/m528x.c 
b/arch/m68k/platform/coldfire/m528x.c
index f1319e5..f9f7e6a 100644
--- a/arch/m68k/platform/coldfire/m528x.c
+++ b/arch/m68k/platform/coldfire/m528x.c
@@ -53,9 +53,9 @@ static void __init m528x_fec_init(void)
u16 v16;
 
/* Set multi-function pins to ethernet mode for fec0 */
-   v16 = readw(MCF_IPSBAR + 0x100056);
-   writew(v16 | 0xf00, MCF_IPSBAR + 0x100056);
-   writeb(0xc0, MCF_IPSBAR + 0x100058);
+   v16 = readw(MCFGPIO_PASPAR);
+   writew(v16 | 0xf00, MCFGPIO_PASPAR);
+   writeb(0xc0, MCFGPIO_PEHLPAR);
 }
 
 /***/
-- 
1.7.0.4

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[uClinux-dev] [PATCH 02/11] m68knommu: remove unused ColdFire 5282 register definitions

2012-09-20 Thread gerg 
From: Greg Ungerer 

There is a bunch of old unused and ugly register definitions in the ColdFire
5282 header. Remove them.

Signed-off-by: Greg Ungerer 
---
 arch/m68k/include/asm/m528xsim.h |   51 +-
 1 files changed, 1 insertions(+), 50 deletions(-)

diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h
index 4acb3c0..cf68ca0 100644
--- a/arch/m68k/include/asm/m528xsim.h
+++ b/arch/m68k/include/asm/m528xsim.h
@@ -233,23 +233,6 @@
 #define MCFGPIO_IRQ_VECBASEMCFINT_VECBASE
 #define MCFGPIO_PIN_MAX180
 
-
-/*
- * Derek Cheung - 6 Feb 2005
- * add I2C and QSPI register definition using Freescale's MCF5282
- */
-/* set Port AS pin for I2C or UART */
-#define MCF5282_GPIO_PASPAR (volatile u16 *) (MCF_IPSBAR + 0x00100056)
-
-/* Port UA Pin Assignment Register (8 Bit) */
-#define MCF5282_GPIO_PUAPAR0x10005C
-
-/* Interrupt Mask Register Register Low */ 
-#define MCF5282_INTC0_IMRL  (volatile u32 *) (MCF_IPSBAR + 0x0C0C)
-/* Interrupt Control Register 7 */
-#define MCF5282_INTC0_ICR17 (volatile u8 *) (MCF_IPSBAR + 0x0C51)
-
-
 /*
  *  Reset Control Unit (relative to IPSBAR).
  */
@@ -259,37 +242,5 @@
 #defineMCF_RCR_SWRESET 0x80/* Software reset bit */
 #defineMCF_RCR_FRCSTOUT0x40/* Force external reset 
*/
 
-/*
-*
-* Inter-IC (I2C) Module
-*
-*/
-/* Read/Write access macros for general use */
-#define MCF5282_I2C_I2ADR   (volatile u8 *) (MCF_IPSBAR + 0x0300) // 
Address 
-#define MCF5282_I2C_I2FDR   (volatile u8 *) (MCF_IPSBAR + 0x0304) // Freq 
Divider
-#define MCF5282_I2C_I2CR(volatile u8 *) (MCF_IPSBAR + 0x0308) // 
Control
-#define MCF5282_I2C_I2SR(volatile u8 *) (MCF_IPSBAR + 0x030C) // Status
-#define MCF5282_I2C_I2DR(volatile u8 *) (MCF_IPSBAR + 0x0310) // Data 
I/O
-
-/* Bit level definitions and macros */
-#define MCF5282_I2C_I2ADR_ADDR(x)   (((x)&0x7F)<<0x01)
-
-#define MCF5282_I2C_I2FDR_IC(x) (((x)&0x3F))
-
-#define MCF5282_I2C_I2CR_IEN(0x80) // I2C enable
-#define MCF5282_I2C_I2CR_IIEN   (0x40)  // interrupt enable
-#define MCF5282_I2C_I2CR_MSTA   (0x20)  // master/slave mode
-#define MCF5282_I2C_I2CR_MTX(0x10)  // transmit/receive mode
-#define MCF5282_I2C_I2CR_TXAK   (0x08)  // transmit acknowledge enable
-#define MCF5282_I2C_I2CR_RSTA   (0x04)  // repeat start
-
-#define MCF5282_I2C_I2SR_ICF(0x80)  // data transfer bit
-#define MCF5282_I2C_I2SR_IAAS   (0x40)  // I2C addressed as a slave
-#define MCF5282_I2C_I2SR_IBB(0x20)  // I2C bus busy
-#define MCF5282_I2C_I2SR_IAL(0x10)  // aribitration lost
-#define MCF5282_I2C_I2SR_SRW(0x04)  // slave read/write
-#define MCF5282_I2C_I2SR_IIF(0x02)  // I2C interrupt
-#define MCF5282_I2C_I2SR_RXAK   (0x01)  // received acknowledge
-
-
+//
 #endif /* m528xsim_h */
-- 
1.7.0.4

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[uClinux-dev] [PATCH 00/11] m68knommu: clean up ColdFire Peripheral headers

2012-09-20 Thread gerg 

This patch series is a bunch of cleanups and fixes across the ColdFire
periperhal header files. Primarily they are:

. fix mixed up uses of relative and absolute address
. convert hard coded addresses into proper definitions
. use consistent names for definitions across different ColdFire types
. remove unused definitions

This follows on from (and is meant to be applied on top of) the recent
series I sent that converts most base peripheral address definitions to be
absolute. The aim is to reduce the occurance of bugs that are mixing up
relative and absolute address definitions.

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Re: [uClinux-dev] finding the root device

2012-09-20 Thread Greg Ungerer 

Hi Richard,

On 20/09/12 20:38, Richard Cochran wrote:

I am running mainline Linux on the Freescale/Axiom M5234BCC with uboot
2011.09-0-g0562219 and have been carrying along a patch from the
uClinux-dist, like shown below for v3.2.9.

I create a image by concatenating the kernel with a romfs, and I boot
it by loading over tftp and jumping to the image with the uboot 'go'
command.

My question: Is there a way to pass the kernel command line from uboot
to specify the root device, instead of using this patch?


I haven't used uboot on ColdFire, so I am not sure if there is a
standard way to pass kernel parameters.

But you can always build command line options into your kernel config.
Look in the "Kernel Hacking" -> "Compiled-in Kernel Boot Parameter".
I always do this with stock kernels, setting the command line to
"root=/dev/mtdblock0" in the config.

Regards
Greg





diff --git a/drivers/mtd/maps/uclinux.c b/drivers/mtd/maps/uclinux.c
index 6793074..9cf7df5 100644
--- a/drivers/mtd/maps/uclinux.c
+++ b/drivers/mtd/maps/uclinux.c
@@ -15,6 +15,7 @@
  #include 
  #include 
  #include 
+#include 
  #include 
  #include 
  #include 
@@ -89,6 +90,7 @@ static int __init uclinux_mtd_init(void)
mtd->priv = mapp;

uclinux_ram_mtdinfo = mtd;
+   ROOT_DEV = MKDEV(MTD_BLOCK_MAJOR, 0);
mtd_device_register(mtd, uclinux_romfs, NUM_PARTITIONS);

return(0);
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--

Greg Ungerer  --  Principal EngineerEMAIL: g...@snapgear.com
SnapGear Group, McAfee  PHONE:   +61 7 3435 2888
8 Gardner Close FAX: +61 7 3217 5323
Milton, QLD, 4064, AustraliaWEB: http://www.SnapGear.com
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Re: [uClinux-dev] framebuffer/console question

2012-09-20 Thread Geert Uytterhoeven 
Hi Angelo,

On Mon, Sep 17, 2012 at 2:29 PM, angelo  wrote:
> i have a working coldfire board, running uClinux. I connected a 128x64
> monochrome lcd on gpio, and written a framebuffer driver.

On gpio, so it's not memory mapped?

> From userspace i can now write on "/dev/fb0" and see some images properly.

Good.

> My question now is about console. Just for playing, i am trying to see the
> console output on the LCD. Even if very small, this should be possible, as i
> enabled the "console framebuffer" driver and some fonts.

OK.

> Once i booted linux, i try an echo "test" > /dev/console, something seems to
> happen on the screen, some pixels are cleared, but i don't see nothing
> similar to font chars.

Strange.

> I read fb and fbcon docs, but i couldn't find any document that explain if
> console fb driver (fbcon) can be used with some fb drivers only (like
> vesfb), or with any fb driver. So my question is: is it possible or i should
> add/create some additional driver ?

The console should work, assumed you provided the proper drawing operations
in your struct fb_ops. E.g. for simple packed monochrome:

.fb_fillrect= cfb_fillrect,
.fb_copyarea= cfb_copyarea,
.fb_imageblit   = cfb_imageblit,

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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Re: [uClinux-dev] finding the root device

2012-09-20 Thread Erwin Authried 
Hi,

you can use something like "root=31:00" in the kernel cmdline.

Regards,
Erwin 

Am Thursday, den 20.09.2012, 12:38 +0200 schrieb Richard Cochran:
> I am running mainline Linux on the Freescale/Axiom M5234BCC with uboot
> 2011.09-0-g0562219 and have been carrying along a patch from the
> uClinux-dist, like shown below for v3.2.9.
> 
> I create a image by concatenating the kernel with a romfs, and I boot
> it by loading over tftp and jumping to the image with the uboot 'go'
> command.
> 
> My question: Is there a way to pass the kernel command line from uboot
> to specify the root device, instead of using this patch?
> 
> Thanks,
> Richard
> 
> 
> diff --git a/drivers/mtd/maps/uclinux.c b/drivers/mtd/maps/uclinux.c
> index 6793074..9cf7df5 100644
> --- a/drivers/mtd/maps/uclinux.c
> +++ b/drivers/mtd/maps/uclinux.c
> @@ -15,6 +15,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -89,6 +90,7 @@ static int __init uclinux_mtd_init(void)
>   mtd->priv = mapp;
>  
>   uclinux_ram_mtdinfo = mtd;
> + ROOT_DEV = MKDEV(MTD_BLOCK_MAJOR, 0);
>   mtd_device_register(mtd, uclinux_romfs, NUM_PARTITIONS);
>  
>   return(0);
> ___
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-- 
Dipl.-Ing. Erwin Authried
Softwareentwicklung und Systemdesign

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[uClinux-dev] finding the root device

2012-09-20 Thread Richard Cochran 
I am running mainline Linux on the Freescale/Axiom M5234BCC with uboot
2011.09-0-g0562219 and have been carrying along a patch from the
uClinux-dist, like shown below for v3.2.9.

I create a image by concatenating the kernel with a romfs, and I boot
it by loading over tftp and jumping to the image with the uboot 'go'
command.

My question: Is there a way to pass the kernel command line from uboot
to specify the root device, instead of using this patch?

Thanks,
Richard


diff --git a/drivers/mtd/maps/uclinux.c b/drivers/mtd/maps/uclinux.c
index 6793074..9cf7df5 100644
--- a/drivers/mtd/maps/uclinux.c
+++ b/drivers/mtd/maps/uclinux.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -89,6 +90,7 @@ static int __init uclinux_mtd_init(void)
mtd->priv = mapp;
 
uclinux_ram_mtdinfo = mtd;
+   ROOT_DEV = MKDEV(MTD_BLOCK_MAJOR, 0);
mtd_device_register(mtd, uclinux_romfs, NUM_PARTITIONS);
 
return(0);
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