Thanks Joel and Kinsey,
I agree that QEMU is a good option to get familiar with the OS, but while
learning, I am also doing some benchmarks and comparing performance on a number
of boards I have around. I have a Hercules Cortex-R5 board but this is not
supported and I don't think any other current BSP supports R5, or for that
matter, any newer design like R8 or R52. I wonder why I don't see more traction
on Cortex-R in general in the scientific or real-time community. Perhaps it is
used more broadly on custom designs and there are not so many off-the-shelf
boards.
There is a BSP for a TI Hercules R4 but I was expecting not to diverge too much
as I am not very familiar with the Cortex-R family and it would take me quite
some time to adapt it to Cortex-R5. After all I am doing this in my spare time
and I was hoping to get familiar with the system and get a feeling on how the
HW performs without going deep in integrating a new board.
The Trenz board looks quite good, I will have a look. On the other hand, I hear
that the Avnet board is used for research / prototyping by some groups in ESA.
Regards,
Juan.
On Sat, 20 Feb 2021, at 12:05 AM, Kinsey Moore wrote:
> On Fri, Feb 19, 2021 at 4:43 PM Joel Sherrill wrote:
>
> I've cc'ed Kinsey Moore and asked him to subscribe to this list so he can
> reply.
>
> On Fri, Feb 19, 2021 at 11:46 AM Juan Solano wrote:
>> Hi all,
>>
>> I was looking for a bsp that supports a Cortex-R5 board and it seems the
>> only one available is the Xilinx Zynq bsp, is that correct? It was not clear
>> to me if this bsp is working on the Cortex-R5 processors of the board.
>
> Kinsey did an R5 for a custom SOC that never saw silicon. He can tell you
> what is in RTEMS and give you an idea what needs to be done.
>
> It was actually a Cortex-R52, but the work was never finished or polished for
> submission. It’s publicly available here:
> https://github.com/ISI-apex/rtems/tree/hpsc-1.3/bsps/arm/gen-r52/
>
> It was a relatively complicated custom board (and QEMU environment), so while
> the peripherals and core CPU support may be useful the remainder is unlikely
> to be.
>
> The Cortex-R5 CPUs on the Zynq Ultrasacle+ MPSoC do not currently have a BSP,
> but I imagine a basic BSP could be brought up relatively quickly. The
> arm/xilinx_zynqmp BSP actually targets the A53 cores in 32bit/ARMv7 mode.
>
> I think as part of the aarch64 port Kinsey has submitted, we looked at this
> board and decided not to get it because it didn't have wired Ethernet.
> Someone has told me there is an add-on shield to add it, But I don't know for
> sure or have a link to that.
>
> Kinsey has been using another Avnet board and a board from Trenz. Both have
> wired networking.
>
> If you haven’t yet purchased a board, I’d highly recommend the Trenz board
> for cost reasons. It also has a PHY that’s already supported in LibBSD.
> https://shop.trenz-electronic.de/en/TE0802-02-2AEU2-A-MPSoC-Development-Board-with-Xilinx-Zynq-UltraScale-ZU2-and-LPDDR4
>
>>
>> Is the Avnet Ultra96-V2 a good recommendation to experiment with? I am
>> currently just learning RTEMS, which makes other boards too expensive for my
>> needs.
>
> If you are just learning RTEMS, the first step we always recommend is a
> simulator since they are free. Qemu has a Zynq simulation which I think all
> the core developers use from time to time. Kinsey has spent a lot of time on
> Qemu for the aarch64 and there are BSPs in the tree for that. He is close to
> another round of submissions which he should talk about.
>
> The user manual has been updated with information on how to start QEMU for
> both the generic Cortex-A53 BSP and also for the zynqmp BSP. There are some
> more details for network on QEMU, but that will also be getting posted when
> the rest of the patches go up.
>
> Simulators are great for getting familiar with things. The same cross
> toolchain can be used and it is just a matter of switching BSPs. It works as
> long as the simulator has enough IO for your initial steps.
>
> Let me know if you have any questions about any of this.
>
> Kinsey
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