Re: RTEMS on the Zynq Ultrascale+ R5
Yes. Side processor only. I wasn't sure how to ask that. I thought it would. Thanks. I figured I could write drivers to use either shared memory or Xilinx's mailbox IP as a serial device for inter processor IO. Does RTEMS already support OpenAMP? I'm running Linux on the A53 side. There are no mailbox drivers in the Linux mainline, but OpenAMP is supported. I'm hoping that if I can implement a serial device using OpenAMP / LibMetal, add it to the Linux device tree, then the other end of the device will just magically appear on the Linux side. For now, I'm using a dedicated UART for the console. I might go virtual later. On Mon, Aug 9, 2021 at 1:27 PM Joel Sherrill wrote: > > > On Mon, Aug 9, 2021 at 12:53 PM Mathew Benson > wrote: > >> I might take that on. When I took the RTEMS training a couple years ago, >> the repository was still in the middle of a restructuring and build system >> upgrade so it was a little confusing. I just looked at it and the new >> documentation and it looks a lot less daunting. >> > > That's good feedback. > > Hopefully this is mostly a BSP with possibly a few tweaks to the ARM > specific code if the CPU model has differences not yet accounted for. > > If used as a side processor only, it might not have many peripheral > drivers which would make things simpler. The timer for the clock and > interrupt controller are quite likely already supported. > > One thing that does need to be addressed in the BSP and software stack is > how to communicate with it as a side processor. There are standard open > source packages out there for that and whatever one is used here would need > to be ported. > > I'm guessing here but the console may be virtual through that > communications bridge to the main cores. > > --joel > >> >> >> On Mon, Aug 9, 2021 at 12:35 PM Joel Sherrill wrote: >> >>> On Mon, Aug 9, 2021 at 11:49 AM Gedare Bloom wrote: >>> > >>> > Hi Mathew, >>> > >>> > Not that I'm aware of, so probably not. There is ongoing work that is >>> > improving the Zynq Ultrascale+ support, and there is also work ongoing >>> > for the Xilinx Versal, which shares some features including R5F >>> > co-processors. OAR has been pushing on Ultrascale, but I couldn't tell >>> > you what their scope is, and I have been working with Chris Johns on >>> > the Versal but the R5F is not yet in scope for me. >>> >>> Gedare's right. OAR did the aarch64 bit port but we haven't touched the >>> R5 yet. Everytime someone (you?) ask, I always think of the R52 FVP and >>> tms570 BSPs but those aren't what you need. >>> >>> This is certainly something we'd like to see for RTEMS. It just needs a >>> sponsor. :) >>> >>> --joel >>> > >>> > Gedare >>> > >>> > On Sat, Aug 7, 2021 at 2:22 PM Mathew Benson < >>> mben...@windhoverlabs.com> wrote: >>> > > >>> > > Has anybody started or completed porting RTEMS to the R5? >>> > > >>> > > Sent from my iPad >>> > > ___ >>> > > users mailing list >>> > > users@rtems.org >>> > > http://lists.rtems.org/mailman/listinfo/users >>> > ___ >>> > users mailing list >>> > users@rtems.org >>> > http://lists.rtems.org/mailman/listinfo/users >>> >> >> >> -- >> *Mathew Benson* >> CEO | Chief Engineer >> Windhover Labs, LLC >> 832-640-4018 >> >> >> www.windhoverlabs.com >> >> -- *Mathew Benson* CEO | Chief Engineer Windhover Labs, LLC 832-640-4018 www.windhoverlabs.com ___ users mailing list users@rtems.org http://lists.rtems.org/mailman/listinfo/users
Re: RTEMS on the Zynq Ultrascale+ R5
On Mon, Aug 9, 2021 at 12:53 PM Mathew Benson wrote: > I might take that on. When I took the RTEMS training a couple years ago, > the repository was still in the middle of a restructuring and build system > upgrade so it was a little confusing. I just looked at it and the new > documentation and it looks a lot less daunting. > That's good feedback. Hopefully this is mostly a BSP with possibly a few tweaks to the ARM specific code if the CPU model has differences not yet accounted for. If used as a side processor only, it might not have many peripheral drivers which would make things simpler. The timer for the clock and interrupt controller are quite likely already supported. One thing that does need to be addressed in the BSP and software stack is how to communicate with it as a side processor. There are standard open source packages out there for that and whatever one is used here would need to be ported. I'm guessing here but the console may be virtual through that communications bridge to the main cores. --joel > > > On Mon, Aug 9, 2021 at 12:35 PM Joel Sherrill wrote: > >> On Mon, Aug 9, 2021 at 11:49 AM Gedare Bloom wrote: >> > >> > Hi Mathew, >> > >> > Not that I'm aware of, so probably not. There is ongoing work that is >> > improving the Zynq Ultrascale+ support, and there is also work ongoing >> > for the Xilinx Versal, which shares some features including R5F >> > co-processors. OAR has been pushing on Ultrascale, but I couldn't tell >> > you what their scope is, and I have been working with Chris Johns on >> > the Versal but the R5F is not yet in scope for me. >> >> Gedare's right. OAR did the aarch64 bit port but we haven't touched the >> R5 yet. Everytime someone (you?) ask, I always think of the R52 FVP and >> tms570 BSPs but those aren't what you need. >> >> This is certainly something we'd like to see for RTEMS. It just needs a >> sponsor. :) >> >> --joel >> > >> > Gedare >> > >> > On Sat, Aug 7, 2021 at 2:22 PM Mathew Benson >> wrote: >> > > >> > > Has anybody started or completed porting RTEMS to the R5? >> > > >> > > Sent from my iPad >> > > ___ >> > > users mailing list >> > > users@rtems.org >> > > http://lists.rtems.org/mailman/listinfo/users >> > ___ >> > users mailing list >> > users@rtems.org >> > http://lists.rtems.org/mailman/listinfo/users >> > > > -- > *Mathew Benson* > CEO | Chief Engineer > Windhover Labs, LLC > 832-640-4018 > > > www.windhoverlabs.com > > ___ users mailing list users@rtems.org http://lists.rtems.org/mailman/listinfo/users
Re: RTEMS on the Zynq Ultrascale+ R5
I might take that on. When I took the RTEMS training a couple years ago, the repository was still in the middle of a restructuring and build system upgrade so it was a little confusing. I just looked at it and the new documentation and it looks a lot less daunting. On Mon, Aug 9, 2021 at 12:35 PM Joel Sherrill wrote: > On Mon, Aug 9, 2021 at 11:49 AM Gedare Bloom wrote: > > > > Hi Mathew, > > > > Not that I'm aware of, so probably not. There is ongoing work that is > > improving the Zynq Ultrascale+ support, and there is also work ongoing > > for the Xilinx Versal, which shares some features including R5F > > co-processors. OAR has been pushing on Ultrascale, but I couldn't tell > > you what their scope is, and I have been working with Chris Johns on > > the Versal but the R5F is not yet in scope for me. > > Gedare's right. OAR did the aarch64 bit port but we haven't touched the > R5 yet. Everytime someone (you?) ask, I always think of the R52 FVP and > tms570 BSPs but those aren't what you need. > > This is certainly something we'd like to see for RTEMS. It just needs a > sponsor. :) > > --joel > > > > Gedare > > > > On Sat, Aug 7, 2021 at 2:22 PM Mathew Benson > wrote: > > > > > > Has anybody started or completed porting RTEMS to the R5? > > > > > > Sent from my iPad > > > ___ > > > users mailing list > > > users@rtems.org > > > http://lists.rtems.org/mailman/listinfo/users > > ___ > > users mailing list > > users@rtems.org > > http://lists.rtems.org/mailman/listinfo/users > -- *Mathew Benson* CEO | Chief Engineer Windhover Labs, LLC 832-640-4018 www.windhoverlabs.com ___ users mailing list users@rtems.org http://lists.rtems.org/mailman/listinfo/users
Re: RTEMS on the Zynq Ultrascale+ R5
On Mon, Aug 9, 2021 at 11:49 AM Gedare Bloom wrote: > > Hi Mathew, > > Not that I'm aware of, so probably not. There is ongoing work that is > improving the Zynq Ultrascale+ support, and there is also work ongoing > for the Xilinx Versal, which shares some features including R5F > co-processors. OAR has been pushing on Ultrascale, but I couldn't tell > you what their scope is, and I have been working with Chris Johns on > the Versal but the R5F is not yet in scope for me. Gedare's right. OAR did the aarch64 bit port but we haven't touched the R5 yet. Everytime someone (you?) ask, I always think of the R52 FVP and tms570 BSPs but those aren't what you need. This is certainly something we'd like to see for RTEMS. It just needs a sponsor. :) --joel > > Gedare > > On Sat, Aug 7, 2021 at 2:22 PM Mathew Benson > wrote: > > > > Has anybody started or completed porting RTEMS to the R5? > > > > Sent from my iPad > > ___ > > users mailing list > > users@rtems.org > > http://lists.rtems.org/mailman/listinfo/users > ___ > users mailing list > users@rtems.org > http://lists.rtems.org/mailman/listinfo/users ___ users mailing list users@rtems.org http://lists.rtems.org/mailman/listinfo/users
Re: RTEMS on the Zynq Ultrascale+ R5
Hi Mathew, Not that I'm aware of, so probably not. There is ongoing work that is improving the Zynq Ultrascale+ support, and there is also work ongoing for the Xilinx Versal, which shares some features including R5F co-processors. OAR has been pushing on Ultrascale, but I couldn't tell you what their scope is, and I have been working with Chris Johns on the Versal but the R5F is not yet in scope for me. Gedare On Sat, Aug 7, 2021 at 2:22 PM Mathew Benson wrote: > > Has anybody started or completed porting RTEMS to the R5? > > Sent from my iPad > ___ > users mailing list > users@rtems.org > http://lists.rtems.org/mailman/listinfo/users ___ users mailing list users@rtems.org http://lists.rtems.org/mailman/listinfo/users
RTEMS on the Zynq Ultrascale+ R5
Has anybody started or completed porting RTEMS to the R5? Sent from my iPad ___ users mailing list users@rtems.org http://lists.rtems.org/mailman/listinfo/users
