[USRP-users] E310: 2x2 Rx RFNoC Attenuating Tx output, 1x1 RX RFNoC: Full Tx output
I have a generic RFNoC block that I created and it receives only, and it can be configured as a 2x2 or 1x1 I/O mode. In GnuRadio I have also paired this 2x2 or 1x1 RX block with a TX block, the gr-ettus RFNOC Siggen, which just outputs a sine tone. When I have my RX block configured as 1x1, the TX signal power is well above -20 dBm, but if I configure my RX block as 2x2, the TX signal is greatly attenuated, about -60dBm max. Why is this happening and is the E310 the limiting factor? Is 2 Rx streams plus the Tx out too much for the Zynq 7020 Artix FPGA? Thanks, Andrew ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] Current state of GNURadio on the E320
Any tips for getting GNU Radio on the E320? I see a zeus branch. Anyone built that? Philip ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] Issues generating and loading bitstreams with RFNoC blocks (UHD-3.15.LTS)
so, the problem is that uhd_image_builder.py still can't find your OOT noc block (error: module not found)? This file looks for several methods for including your OOT block. I think it first looks for a Makefile.inc if it exists in your OOT 'rfnoc' folder. If it doesn't find that, it looks for perhaps the same file in your 'rfnoc/fpga-src' folder. And, if not that looks for the file Makefile.srcs in that folder. I'm sure I don't have it exactly right, but perhaps just look at uhd_image_builder.py to see the logic in the "create_oot_include" function. Somehow, it seems it is not finding your block. If you have no luck with Makefile.srcs, you could try adding Makefile.inc to various folders. Rob On Tue, Jul 28, 2020 at 11:25 AM Jorge Arroyo Giganto wrote: > Hi Rob, > > Thanks a lot for your patch file, but unfortunately I'm still getting the > same errors when trying to use custom RFNoC blocks with > uhd_image_builder.py. > > Any other help would be greatly appreciated, > > Jorge > > El mar., 28 jul. 2020 a las 15:56, Rob Kossler () > escribió: > >> Try this patch file. I received from Ettus a long time ago (Oct 2019?) >> but it appears that it is still not fixed. >> Rob >> >> On Tue, Jul 28, 2020 at 6:27 AM Jorge Arroyo Giganto via USRP-users < >> usrp-users@lists.ettus.com> wrote: >> >>> Hi, >>> >>> >>> I’m working on getting a solid workflow to build and use RFNoC blocks. >>> I’m using branches UHD-3.15.LTS and GNU Radio’s maint-3.7 (also, packet >>> gr-ettus from the master branch and uhd-fpga from the UHD-3.15.LTS branch). >>> I’m using an E310 (SG1), with the SD image I get with >>> ‘uhd_images_downloader -t e310 -t sdimg’ (usrp_e310_fs.sdimg). Also, I’m >>> running Ubuntu 18.04 and I’ve got Vivado 2018.3 installed. >>> >>> A couple of weeks ago I started trying to follow the ‘Getting Started >>> with RFNoC Development’ guide, and tried using rfnoc-devel and master >>> branches, but it seems like this UHD-3.15.LTS is the one working the best >>> for me, but I still have some issues. >>> >>> Following the guide, I built a custom block (gain), which I was able to >>> get through the testbench (after quite a bit of attempts), but when trying >>> to generate a bitstream (.bit file) with my gain block I got the following >>> errors: >>> >>> >>> ~/rfnoc_UHD315/src/uhd-fpga/usrp3/tools/scripts$ >>> ./uhd_image_builder.py gain fft -I ~/rfnoc_UHD315/src/rfnoc-tutorial/ -d >>> e31x -t E310_RFNOC -m 4 –fill-with-fifos >>> >>> . >>> >>> . >>> >>> . >>> >>> ERROR: [Synth 8-439] module 'noc_block_gain' not found >>> [/home/jarroyo/rfnoc_UHD315/ >>> src/uhd-fpga/usrp3/top/e31x/rfnoc_ce_auto_inst_e31x.v:20] >>> >>> ERROR: [Synth 8-6156] failed synthesizing module 'e31x_core' >>> [/home/jarroyo/rfnoc_UHD315/src/uhd-fpga/usrp3/top/e31x/e31x_core.v:17] >>> >>> ERROR: [Synth 8-6156] failed synthesizing module 'e31x' >>> [/home/jarroyo/rfnoc_UHD315/src/uhd-fpga/usrp3/top/e31x/e31x.v:13] >>> >>> [00:01:46] Current task: Synthesis +++ Current Phase: Starting >>> >>> ERROR: [Common 17-69] Command failed: Synthesis failed - please see >>> the console or run log file for details >>> >>> [00:01:46] Current task: Synthesis +++ Current Phase: Finished >>> >>> [00:01:46] Process terminated. Status: Failure >>> >>> >>> If it is useful information, I was able to successfully generate a >>> bitstream with existing RFNoC blocks (‘./uhd_image_builder.py window fft -d >>> e31x -t E310_RFNOC -m 3 –fill-with-fifos’ for example, is working), so >>> that’s why I guess my main issue is with the gain custom block. >>> >>> >>> Also, another issue I’m having is using uhd_image_loader on the E310 >>> terminal when loading my own bitstreams: >>> >>> >>> root@ni-e31x:~# uhd_image_loader >>> --args="type=e3xx,addr=192.168.10.2" --fpga-path >>> /usr/share/uhd/images/e31x.bit >>> >>> [INFO] [UHD] linux; GNU C++ version 8.2.0; Boost_106800; >>> UHD_3.15.0.0-0-gaea0e2de >>> >>> No applicable UHD devices found >>> >>> >>> Is there anything I might be doing wrong? Or is this workflow with these >>> branches and tool versions not the most appropiate currently? >>> >>> >>> Thanks in advance, >>> >>> >>> Jorge >>> ___ >>> USRP-users mailing list >>> USRP-users@lists.ettus.com >>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >>> >> > ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] Issues generating and loading bitstreams with RFNoC blocks (UHD-3.15.LTS)
Hi Rob, Thanks a lot for your patch file, but unfortunately I'm still getting the same errors when trying to use custom RFNoC blocks with uhd_image_builder.py. Any other help would be greatly appreciated, Jorge El mar., 28 jul. 2020 a las 15:56, Rob Kossler () escribió: > Try this patch file. I received from Ettus a long time ago (Oct 2019?) > but it appears that it is still not fixed. > Rob > > On Tue, Jul 28, 2020 at 6:27 AM Jorge Arroyo Giganto via USRP-users < > usrp-users@lists.ettus.com> wrote: > >> Hi, >> >> >> I’m working on getting a solid workflow to build and use RFNoC blocks. >> I’m using branches UHD-3.15.LTS and GNU Radio’s maint-3.7 (also, packet >> gr-ettus from the master branch and uhd-fpga from the UHD-3.15.LTS branch). >> I’m using an E310 (SG1), with the SD image I get with >> ‘uhd_images_downloader -t e310 -t sdimg’ (usrp_e310_fs.sdimg). Also, I’m >> running Ubuntu 18.04 and I’ve got Vivado 2018.3 installed. >> >> A couple of weeks ago I started trying to follow the ‘Getting Started >> with RFNoC Development’ guide, and tried using rfnoc-devel and master >> branches, but it seems like this UHD-3.15.LTS is the one working the best >> for me, but I still have some issues. >> >> Following the guide, I built a custom block (gain), which I was able to >> get through the testbench (after quite a bit of attempts), but when trying >> to generate a bitstream (.bit file) with my gain block I got the following >> errors: >> >> >> ~/rfnoc_UHD315/src/uhd-fpga/usrp3/tools/scripts$ >> ./uhd_image_builder.py gain fft -I ~/rfnoc_UHD315/src/rfnoc-tutorial/ -d >> e31x -t E310_RFNOC -m 4 –fill-with-fifos >> >> . >> >> . >> >> . >> >> ERROR: [Synth 8-439] module 'noc_block_gain' not found >> [/home/jarroyo/rfnoc_UHD315/ >> src/uhd-fpga/usrp3/top/e31x/rfnoc_ce_auto_inst_e31x.v:20] >> >> ERROR: [Synth 8-6156] failed synthesizing module 'e31x_core' >> [/home/jarroyo/rfnoc_UHD315/src/uhd-fpga/usrp3/top/e31x/e31x_core.v:17] >> >> ERROR: [Synth 8-6156] failed synthesizing module 'e31x' >> [/home/jarroyo/rfnoc_UHD315/src/uhd-fpga/usrp3/top/e31x/e31x.v:13] >> >> [00:01:46] Current task: Synthesis +++ Current Phase: Starting >> >> ERROR: [Common 17-69] Command failed: Synthesis failed - please see >> the console or run log file for details >> >> [00:01:46] Current task: Synthesis +++ Current Phase: Finished >> >> [00:01:46] Process terminated. Status: Failure >> >> >> If it is useful information, I was able to successfully generate a >> bitstream with existing RFNoC blocks (‘./uhd_image_builder.py window fft -d >> e31x -t E310_RFNOC -m 3 –fill-with-fifos’ for example, is working), so >> that’s why I guess my main issue is with the gain custom block. >> >> >> Also, another issue I’m having is using uhd_image_loader on the E310 >> terminal when loading my own bitstreams: >> >> >> root@ni-e31x:~# uhd_image_loader >> --args="type=e3xx,addr=192.168.10.2" --fpga-path >> /usr/share/uhd/images/e31x.bit >> >> [INFO] [UHD] linux; GNU C++ version 8.2.0; Boost_106800; >> UHD_3.15.0.0-0-gaea0e2de >> >> No applicable UHD devices found >> >> >> Is there anything I might be doing wrong? Or is this workflow with these >> branches and tool versions not the most appropiate currently? >> >> >> Thanks in advance, >> >> >> Jorge >> ___ >> USRP-users mailing list >> USRP-users@lists.ettus.com >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> > ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] Issues generating and loading bitstreams with RFNoC blocks (UHD-3.15.LTS)
Try this patch file. I received from Ettus a long time ago (Oct 2019?) but
it appears that it is still not fixed.
Rob
On Tue, Jul 28, 2020 at 6:27 AM Jorge Arroyo Giganto via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Hi,
>
>
> I’m working on getting a solid workflow to build and use RFNoC blocks. I’m
> using branches UHD-3.15.LTS and GNU Radio’s maint-3.7 (also, packet
> gr-ettus from the master branch and uhd-fpga from the UHD-3.15.LTS branch).
> I’m using an E310 (SG1), with the SD image I get with
> ‘uhd_images_downloader -t e310 -t sdimg’ (usrp_e310_fs.sdimg). Also, I’m
> running Ubuntu 18.04 and I’ve got Vivado 2018.3 installed.
>
> A couple of weeks ago I started trying to follow the ‘Getting Started with
> RFNoC Development’ guide, and tried using rfnoc-devel and master branches,
> but it seems like this UHD-3.15.LTS is the one working the best for me, but
> I still have some issues.
>
> Following the guide, I built a custom block (gain), which I was able to
> get through the testbench (after quite a bit of attempts), but when trying
> to generate a bitstream (.bit file) with my gain block I got the following
> errors:
>
>
> ~/rfnoc_UHD315/src/uhd-fpga/usrp3/tools/scripts$
> ./uhd_image_builder.py gain fft -I ~/rfnoc_UHD315/src/rfnoc-tutorial/ -d
> e31x -t E310_RFNOC -m 4 –fill-with-fifos
>
> .
>
> .
>
> .
>
> ERROR: [Synth 8-439] module 'noc_block_gain' not found
> [/home/jarroyo/rfnoc_UHD315/
> src/uhd-fpga/usrp3/top/e31x/rfnoc_ce_auto_inst_e31x.v:20]
>
> ERROR: [Synth 8-6156] failed synthesizing module 'e31x_core'
> [/home/jarroyo/rfnoc_UHD315/src/uhd-fpga/usrp3/top/e31x/e31x_core.v:17]
>
> ERROR: [Synth 8-6156] failed synthesizing module 'e31x'
> [/home/jarroyo/rfnoc_UHD315/src/uhd-fpga/usrp3/top/e31x/e31x.v:13]
>
> [00:01:46] Current task: Synthesis +++ Current Phase: Starting
>
> ERROR: [Common 17-69] Command failed: Synthesis failed - please see
> the console or run log file for details
>
> [00:01:46] Current task: Synthesis +++ Current Phase: Finished
>
> [00:01:46] Process terminated. Status: Failure
>
>
> If it is useful information, I was able to successfully generate a
> bitstream with existing RFNoC blocks (‘./uhd_image_builder.py window fft -d
> e31x -t E310_RFNOC -m 3 –fill-with-fifos’ for example, is working), so
> that’s why I guess my main issue is with the gain custom block.
>
>
> Also, another issue I’m having is using uhd_image_loader on the E310
> terminal when loading my own bitstreams:
>
>
> root@ni-e31x:~# uhd_image_loader
> --args="type=e3xx,addr=192.168.10.2" --fpga-path
> /usr/share/uhd/images/e31x.bit
>
> [INFO] [UHD] linux; GNU C++ version 8.2.0; Boost_106800;
> UHD_3.15.0.0-0-gaea0e2de
>
> No applicable UHD devices found
>
>
> Is there anything I might be doing wrong? Or is this workflow with these
> branches and tool versions not the most appropiate currently?
>
>
> Thanks in advance,
>
>
> Jorge
> ___
> USRP-users mailing list
> USRP-users@lists.ettus.com
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
diff --git a/usrp3/tools/scripts/uhd_image_builder.py b/usrp3/tools/scripts/uhd_image_builder.py
index 23bfa2d9..1587dd25 100755
--- a/usrp3/tools/scripts/uhd_image_builder.py
+++ b/usrp3/tools/scripts/uhd_image_builder.py
@@ -303,24 +303,18 @@ def create_oot_include(device, include_dirs):
currpath = os.path.abspath(str(dirs))
if os.path.isdir(currpath) & (os.path.basename(currpath) == "rfnoc"):
# Case 1: Pointed directly to rfnoc directory
-oot_path = currpath
+oot_path = os.path.dirname(currpath)
elif os.path.isdir(os.path.join(currpath, 'rfnoc')):
# Case 2: Pointed to top level rfnoc module directory
-oot_path = os.path.join(currpath, 'rfnoc')
-elif os.path.isfile(os.path.join(currpath, 'Makefile.inc')):
-# Case 3: Pointed to a random directory with a Makefile.inc
oot_path = currpath
else:
print('No RFNoC module found at ' + os.path.abspath(currpath))
continue
if oot_path not in oot_dir_list:
oot_dir_list.append(oot_path)
-named_path = os.path.join('$(BASE_DIR)', get_relative_path(get_basedir(), oot_path))
+named_path = os.path.join('$(BASE_DIR)', get_relative_path(get_basedir(), oot_path), 'rfnoc')
incfile.write(OOT_DIR_TMPL.format(oot_dir=named_path))
-if os.path.isfile(os.path.join(oot_path, 'Makefile.inc')):
-# Check for Makefile.inc
-incfile.write(OOT_INC_TMPL)
-elif os.path.isfile(os.path.join(oot_path, 'rfnoc', 'Makefile.inc')):
+if os.path.isfile(os.path.join(oot_path, 'rfnoc', 'Makefile.inc')):
# Check for Makefile.inc
Re: [USRP-users] B200 cannot output a sine wave
What you're trying to do is pretty straight forward. I do this here in my lab all the tiem. Can you show us your flowgraph? How are you running tx_waveforms? Are you using a USB 3 port? How's the B200 connected to the oscilloscope? On Mon, 27 Jul 2020 at 21:58, Aaron Smith via USRP-users < usrp-users@lists.ettus.com> wrote: > Marcus, > > I have tried frequencies ranging from 75-450 MHz. My scope is good to 500 > MHz. I have tried gain settings betweeb 30 and 60. I am using RG-174, which > is good to 1000 MHz. > > In my custom code I generate tones by sending repeating samples with a > value of 0.8. In the past this caused tones to appear at B200's center > frequency. This should work regardless of the clock rate or sample rate, > but in this case I'm using a 48 MHz master clock rate and a sample rate of > 8 MHz. > > I also followed a gnuradio companion tutorial to generate a tone and it > produced something ugly too. > > The only thing in my setup that changed is the host laptop. I switched to > a new laptop and had to build UHD from scratch. However, gnuradio companion > appears to use a different UHD version, so I'm skeptical that is the > problem. > > Thanks for your help. > > On Mon, Jul 27, 2020, 7:45 PM Marcus D. Leech via USRP-users < > usrp-users@lists.ettus.com> wrote: > >> On 07/27/2020 09:05 PM, Aaron Smith via USRP-users wrote: >> >> Hello all, >> >> I am trying to output a sine wave from a B200 using custom code, or the >> UHD tx_waveform example. In either case, when I view the output on an >> o-scope, there is not a pure sine wave. The output looks more triangular >> wave. I have used this scope with other B200s and the same code to get a >> pure sine. Is the radio damaged? Is there some sort of calibration >> required? I am using UHD 3.15.0. >> >> Thanks >> >> >> >> ___ >> USRP-users mailing >> listUSRP-users@lists.ettus.comhttp://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> >> What frequency? What gain settings? What is your baseband bandwidth? Is >> your coax cable known to be "good" at the frequency of interest? >> What sample rate? Is the baseband signal well within the Nyquist >> limits? >> >> >> ___ >> USRP-users mailing list >> USRP-users@lists.ettus.com >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> > ___ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > -- Sincerely, Alex-M-Humberstone PhD Student Klipsch School of Electrical Engineering New Mexico State University Las Cruces, New Mexico ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] Issues generating and loading bitstreams with RFNoC blocks (UHD-3.15.LTS)
Hi, I’m working on getting a solid workflow to build and use RFNoC blocks. I’m using branches UHD-3.15.LTS and GNU Radio’s maint-3.7 (also, packet gr-ettus from the master branch and uhd-fpga from the UHD-3.15.LTS branch). I’m using an E310 (SG1), with the SD image I get with ‘uhd_images_downloader -t e310 -t sdimg’ (usrp_e310_fs.sdimg). Also, I’m running Ubuntu 18.04 and I’ve got Vivado 2018.3 installed. A couple of weeks ago I started trying to follow the ‘Getting Started with RFNoC Development’ guide, and tried using rfnoc-devel and master branches, but it seems like this UHD-3.15.LTS is the one working the best for me, but I still have some issues. Following the guide, I built a custom block (gain), which I was able to get through the testbench (after quite a bit of attempts), but when trying to generate a bitstream (.bit file) with my gain block I got the following errors: ~/rfnoc_UHD315/src/uhd-fpga/usrp3/tools/scripts$ ./uhd_image_builder.py gain fft -I ~/rfnoc_UHD315/src/rfnoc-tutorial/ -d e31x -t E310_RFNOC -m 4 –fill-with-fifos . . . ERROR: [Synth 8-439] module 'noc_block_gain' not found [/home/jarroyo/rfnoc_UHD315/ src/uhd-fpga/usrp3/top/e31x/rfnoc_ce_auto_inst_e31x.v:20] ERROR: [Synth 8-6156] failed synthesizing module 'e31x_core' [/home/jarroyo/rfnoc_UHD315/src/uhd-fpga/usrp3/top/e31x/e31x_core.v:17] ERROR: [Synth 8-6156] failed synthesizing module 'e31x' [/home/jarroyo/rfnoc_UHD315/src/uhd-fpga/usrp3/top/e31x/e31x.v:13] [00:01:46] Current task: Synthesis +++ Current Phase: Starting ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details [00:01:46] Current task: Synthesis +++ Current Phase: Finished [00:01:46] Process terminated. Status: Failure If it is useful information, I was able to successfully generate a bitstream with existing RFNoC blocks (‘./uhd_image_builder.py window fft -d e31x -t E310_RFNOC -m 3 –fill-with-fifos’ for example, is working), so that’s why I guess my main issue is with the gain custom block. Also, another issue I’m having is using uhd_image_loader on the E310 terminal when loading my own bitstreams: root@ni-e31x:~# uhd_image_loader --args="type=e3xx,addr=192.168.10.2" --fpga-path /usr/share/uhd/images/e31x.bit [INFO] [UHD] linux; GNU C++ version 8.2.0; Boost_106800; UHD_3.15.0.0-0-gaea0e2de No applicable UHD devices found Is there anything I might be doing wrong? Or is this workflow with these branches and tool versions not the most appropiate currently? Thanks in advance, Jorge ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] How to suppress the overflow indicator "O"
Hi Xavier,
I could suppress the message of overflow "O" after set
UHD_LOG_FASTPATH_DISABLE enviroment variable.
but I could not supress the message on your way.
- OK
$ export UHD_LOG_FASTPATH_DISABLE=1
$ ./rx_samples_to_file --rate 100e6
- NG
setenv in source code
setenv("UHD_LOG_FASTPATH_DISABLE", "1", 0);
Thank you.
___
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