Re: [USRP-users] [UHD] Announcing 4.0.0.0 Release Candidate 1

[Michael Dickens via USRP-users]

Thanks for the UHD 4.0rc1 update, Michael. This UHD version will be the
most robust and compatible version yet!

For macOS users of UHD and GNU Radio, a brief update:

UHD 3.15 and UHD 4.0rc1 build and run on many macOS versions -- at
least 10.11 " El Capitan" through 10.15 "Catalina", and probably further
back with a modern enough compiler. I've built UHD 3.15 back to 10.8
"Mountain Lion", but unfortunately UHD applications do not execute ...
maybe others know what the issue is here? I have yet to try UHD 4.0rc1 on
these older macOS systems.

GNU Radio 3.7.14.0 and 3.8.2.0 -- with a patch to cover the commits since
this release was tagged on the "maint-3.8" branch -- also work with these
same macOS versions.

All of these projects / versions are available in MacPorts right now, via
the ports "uhd" (3.15), "uhd-devel" (4.0rc1), "gnuradio37" (3.7.14.0), and
"gnuradio" (3.8.2.0 + patches).

I have tested out GR 3.8.2.0 + UHD 4.0rc1 and they play nicely (enough)
together; I'm confident that the combinations GR 3.8.2.0 + UHD 3.15 and GR
3.7.14.0 + UHD 3.15 also work. MP allows GR 3.7.14.0 + UHD 4.0rc1, though I
don't know if this will even build.

I value any feedback on macOS building and/or use of UHD and GR (and Volk,
but that's pretty separate by now); MacPorts or some other install means;
any macOS version: 10.4-5 PPC 32/64, 10.4-16 Intel 32/64; even 10.16 ARM64
... if that's where you are (you're ahead of me then, though I'm catching
up ;)  !!!

Cheers! - MLD
---
Michael Dickens
Ettus Research Technical Support
Email: supp...@ettus.com
Web: https://ettus.com/


On Tue, Aug 25, 2020 at 8:46 PM Michael West via USRP-users <
usrp-users@lists.ettus.com> wrote:

> The release candidate of the long awaited UHD version 4.0.0.0 has been
> tagged and is available for testing.  This major release introduces a new
> RFNoC framework, a new streaming infrastructure, a power calibration
> utility and API, and many other features and bug fixes.  The new
> infrastructure provides improved performance, more flexibility, and the
> foundation for future demands of higher throughput and lower latencies.
>
> The tag for this release candidate:
> https://github.com/EttusResearch/uhd/releases/tag/v4.0.0.0-rc1
>
> There have been 831 commits since the last release (3.15.0.0) which can
> be viewed here:
> https://github.com/EttusResearch/uhd/compare/v3.15.0.0...v4.0.0.0-rc1
>
> Please report any bugs found on the UHD issue tracker:
> http://github.com/EttusResearch/uhd/issues
> * Please do not use the issue tracker for help or support.
>
> Pull requests for direct code changes may be submitted to the UHD or FPGA
> repositories:
> http://github.com/EttusResearch/uhd/pulls
> http://github.com/EttusResearch/fpga/pulls
>
> CHANGELOG:
> ## 004.000.000.000
> * b200:
>   - Enable power calibration API
>   - Add a prop tree node usb_version
> * cal:
>   - Add utility to update all .fbs files, or check the generated ones
>   - Add pwr_cal container
> * cmake:
>   - Add ability to pass CXXFLAGS to CMake environment
> * docs:
>   - Update PCIe xport instructions for NI Repos
>   - n3xx: Include WX in table of N320 images
>   - Add stream and transport args documentation
>   - Update Basic/LF dboard references to use new operating mode
>   - e3xx/n3xx: Add sections on FP-GPIOs and how to drive them
>   - n3xx: Document eeprom flags
>   - Add note about DPDK needing to be built as shared libraries
>   - Change DPDK version to 18.11 and make args use underscores
>   - Clarifying which devices support DPDK
> * dpdk:
>   - Add new DPDK stack to integrate with I/O services
> * e31x:
>   - Change RFNoC Ctrl clock to 40 MHz
>   - Fix timeout for timekeeper registers
>   - Fix filter bank and antenna switching for channel 0
>   - Swap out liberio for internal Ethernet
> * e320:
>   - Fix timeout for timekeeper registers
>   - Swap out liberio for internal Ethernet
> * examples:
>   - Add usrp_power_meter example
>   - Update test_messages example
>   - Update gpio example
>   - Add options to benchmark_rate
>   - Add example out-of-tree module for RFNoC modules
>   - Remove thread priority elevation
> * fpga:
>   - Replaced RFNoC architecture with new 4.0 version
>   - Added modelsim make simulation target
>   - Upgrade to Vivade 2019.1
>   - Removed unused coregen files and modules
>   - Removed fpga submodule and merged into uhd repo
>   - lib: Change max FFT size to 1024
>   - lib: add Intel MAX10 architecture for 2clk FIFO
>   - rfnoc: Port RFNoC Keep One in N block to new RFNoC architecture
>   - rfnoc: Port RFNoC Replay block to new RFNoC architecture
>   - rfnoc: Port Signal Generator RFNoC block to new RFNoC architecture
>   - Add Switchboard RFNoC block
>   - Remove liberio
>   - rfnoc: Port RFNoC Moving Average block to new RFNoC architecture
>   - rfnoc: Port Log-Power block to new RFNoC architecture
>   - rfnoc: Port RFNoC Window block to new RFNoC architecture
>   - lib: Add synthesizable AXI4-Stream SV components
>   - lib: Add interf

[USRP-users] Sporadic N310 kernel panics when under load

[Peter Langer via USRP-users]

Hi,

on two different computers, that both have identical hardware specs we
encountered stability issues with the N310 receiver. Here are the hardware
specs for the computers, though we strongly suspect that the issue is with
the software(kernel/drivers) present on the N310.

The issue is that basically everything runs perfectly well until at some
point it does not anymore and the device runs into a kernel panic and
reboots. From our understanding of the linux kernel it must be inside some
interrupt, because the kernel panic is not written to any logfile (we made
logs permanent on the device to ensure that fact). It is _sometimes_ issued
over SSH if we monitor with tail -f /var/log/messages (yes, we see it
there, but it is not written to disk). This only happens if the N310 runs
for a longer period of time - in our case between 1 to 3 days. We
encountered that issue several times now and we verified it with the
standard FPGA image.

Our problem seems to be related (though with another device) to the issue
that was mentioned in January in this thread:
http://ettus.80997.x6.nabble.com/USRP-users-Kernel-Panic-with-v3-15-0-0-on-E320-td14098.html

Aside from the snippet below there are no other messages printed to the
messages log file.

--Snippet from /var/log/messages--
Aug 25 07:44:31 ni-n3xx-31AFFD1 kern.alert kernel: [82689.450921] Unable to
handle kernel paging request at virtual address fffe
Aug 25 07:44:31 ni-n3xx-31AFFD1 kern.alert kernel: [82689.458127] pgd =
d3d33249
Aug 25 07:44:31 ni-n3xx-31AFFD1 kern.alert kernel: [82689.460785]
[fffe] *pgd=2fffd861, *pte=, *ppte=
Aug 25 07:44:31 ni-n3xx-31AFFD1 kern.emerg kernel: [82689.467121] Internal
error: Oops: 8007 [#1] PREEMPT SMP ARM

--Specs--
Processor: AMD Ryzen Threadripper 3970X 32-Core Processor
RAM: 256 GB RAM
Network device: Intel X710-DA2 10GbE with SFP+ direct attach cables
Direct attach cables: Cisco H10GB-10GB-CU3M

The N310 device has the latest stable firmware/fpga image for UHD 3.15-LTS
as of today:
Mender: n3xx/meta-ettus-v3.15.0.0/n3xx_common_mender_default-v3.15.0.0.zip
FPGA: n3xx/fpga-9ba275de0b/n3xx_n310_fpga_default-g9ba275de.zip

we use the XG FPGA image present in the zipfile.

Our test flowgraph with the standard FPGA image only features two radio
blocks that stream at a master_clock_rate of 122.88 Mhz and are each
connected to a DDC that decimates by a factor of 2 (though a factor of 3
and 4 lead to the same issue) and then both connect to a null sink in
gnuradio.

We would appreciate anyone looking into reproducing that or any ideas how
to resolve the issue.

Kind regards,
Peter
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Re: [USRP-users] List of filters and where they are located

[Julian Arnold via USRP-users]

David,

unfortunately not. The filter API does only export the filters internal 
to the AD9361 on B2xx series devices.
However, if you let MCR = sample rate you should basically only have 
filters inside the AD9361 active.


Cheers,
Julian

On 8/26/20 6:16 AM, David Carsenat wrote:

Ok thanks a lotJulian, this is very helpful.
Does your example allow to list FPGA filters also ?

Le mar. 25 août 2020 à 21:57, Julian Arnold > a écrit :


David,

take a look at the ad9361 user guide [1]. It has all the information
you
are looking for.

If you want to know which filters you can configure and how, take a
look
at [2]. It's a simple example I wrote quite a while back but it should
still be good to get you started.

Hope that helps!

Cheers,
Julian

[1]

https://form.analog.com/Form_Pages/Catalina/CatalinaDesign.aspx?prodid=AD9361
[2] https://github.com/jarn0ld/uhd-filter-tool

On 8/25/20 9:09 PM, David Carsenat via USRP-users wrote:
 > Hi, I am using a B205 and I'd just like to know what are the
 > difference filter stages (analog and digital) seen by the signal
(both
 > Tx and Rx), in the AD936x and in the FPGA.
 > Another way to help me, should be to have a description of the
filter
 > that I can address with the filter.hpp functions : Can I address and
 > change filters behaviours that are part only on FPGA or also the
AD9361
 > filters ?
 >
 > Many thanks
 >
 > David
 >
 >
 >
 >
 > ___
 > USRP-users mailing list
 > USRP-users@lists.ettus.com 
 > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
 >



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Re: [USRP-users] List of filters and where they are located

[David Carsenat via USRP-users]

Ok understood.
Many thanks again.
David

Le mer. 26 août 2020 à 22:15, Julian Arnold  a
écrit :

> David,
>
> unfortunately not. The filter API does only export the filters internal
> to the AD9361 on B2xx series devices.
> However, if you let MCR = sample rate you should basically only have
> filters inside the AD9361 active.
>
> Cheers,
> Julian
>
> On 8/26/20 6:16 AM, David Carsenat wrote:
> > Ok thanks a lotJulian, this is very helpful.
> > Does your example allow to list FPGA filters also ?
> >
> > Le mar. 25 août 2020 à 21:57, Julian Arnold  > > a écrit :
> >
> > David,
> >
> > take a look at the ad9361 user guide [1]. It has all the information
> > you
> > are looking for.
> >
> > If you want to know which filters you can configure and how, take a
> > look
> > at [2]. It's a simple example I wrote quite a while back but it
> should
> > still be good to get you started.
> >
> > Hope that helps!
> >
> > Cheers,
> > Julian
> >
> > [1]
> >
> https://form.analog.com/Form_Pages/Catalina/CatalinaDesign.aspx?prodid=AD9361
> > [2] https://github.com/jarn0ld/uhd-filter-tool
> >
> > On 8/25/20 9:09 PM, David Carsenat via USRP-users wrote:
> >  > Hi, I am using a B205 and I'd just like to know what are the
> >  > difference filter stages (analog and digital) seen by the signal
> > (both
> >  > Tx and Rx), in the AD936x and in the FPGA.
> >  > Another way to help me, should be to have a description of the
> > filter
> >  > that I can address with the filter.hpp functions : Can I
> address and
> >  > change filters behaviours that are part only on FPGA or also the
> > AD9361
> >  > filters ?
> >  >
> >  > Many thanks
> >  >
> >  > David
> >  >
> >  >
> >  >
> >  >
> >  > ___
> >  > USRP-users mailing list
> >  > USRP-users@lists.ettus.com 
> >  >
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
> >  >
> >
>
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