Re: [USRP-users] B205 External Reference issue
Hm, there's beauty to that, but also there's beauty in not letting the oscillator drift of indefinitely after you've locked once. So, the classical fastlock at startup/loss of reference lock, and then increasingly reduced loop filter bandwidth would probably be even better. But that means relatively intrusive changes; you'd make `PFD_PERIOD_*` adaptive, you adapt the `err` clip boundaries, `lock_margin` and so on; the values used in b205_ref_pll are pretty certainly results of physical-reality-based verification¹. That's the point where you'd spend serious point characterizing the long-time behaviour of something that probably depends a lot on the characteristics of your clock source (unless that clock source is way superior to anything on the USRP). Also, that'd probably be the point where one would have to think about replacing the well-understood rational ratio PFD control loop with something more complex (and thus harder to make meet timing at acceptable resource usage and quantization loss) like an extended Kalman that can take the nonlinearities of the system into account. To be perfectly honest, I don't see either happen very soon. So, something like extending the state machine in b205_ref_pll to another state that has a larger threshold until it drops back into an adjusting state and adding a settings register to manually fiddle with the state would be the quick and potentially hazardous solution here, I'd guess. Best regards, Marcus ¹ a.k.a. experimentation On Sun, 2018-09-30 at 11:34 +0200, Sylvain Munaut via USRP-users wrote: > Hi, > > I didn't see the screenshots (not posted to the list ?) > > But if absolute precision of the clock doesn't matter, you might be > better off disabling the servo loop once it's "close enough". That > will require fpga modifications to expose the refpll control though. > Actually I think this would be a nice improvement in general for the > b205 to have the DAC value exposed in UHD and allow to enable/disable > the servo loop, just a thought :p > > Cheers, > > Sylvain Munaut > ___ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] B205 External Reference issue
Hi, I didn't see the screenshots (not posted to the list ?) But if absolute precision of the clock doesn't matter, you might be better off disabling the servo loop once it's "close enough". That will require fpga modifications to expose the refpll control though. Actually I think this would be a nice improvement in general for the b205 to have the DAC value exposed in UHD and allow to enable/disable the servo loop, just a thought :p Cheers, Sylvain Munaut ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] B205 External Reference issue
On 09/30/2018 03:55 AM, Arun kumar Verma wrote:
I have tried that but it increases when i reduce amplitude , in fact
for DC coupled ref i am getting best result.
I have checked the schematic and in that if i remove R37 and R38 then
my internal clock will disconnected but i am not sure whether board
will work with only external clock or not. Can you verify this. I want
to disconnect internal clock and want only external clock as there I
am not getting any drift.
DO NOT DO THIS.
Arun
*From:* Marcus D. Leech
*To:* Arun kumar Verma ;
"usrp-users@lists.ettus.com"
*Sent:* Sunday, 30 September 2018 2:19 AM
*Subject:* Re: [USRP-users] B205 External Reference issue
On 09/29/2018 02:20 PM, Arun kumar Verma wrote:
Hi
Please find the screenshots as you have asked. One image is when we
are setting ref to internal but external not connected that time it
is clean and other images is when we are connecting external ref .
Regards,
arun verma
Does the magnitude of this small spur diminish if you reduce the
amplitude of your external reference?
*From:* Marcus D. Leech <mailto:mle...@ripnet.com>
*To:* Arun kumar Verma
<mailto:arun.ve...@eiwave.com>; "usrp-users@lists.ettus.com"
<mailto:usrp-users@lists.ettus.com>
<mailto:usrp-users@lists.ettus.com>
*Sent:* Wednesday, 26 September 2018 11:56 PM
*Subject:* Re: [USRP-users] B205 External Reference issue
On 09/26/2018 02:24 PM, Arun kumar Verma wrote:
Hi Marcus
well I am connecting external ref of 10MHz on Ref Input SMA
connector and once I connect this and set my clock source for
external source then we are getting spurios, these spurs are low
but for AM,FM audio demodulation even Hz suprs can create probelem
and that is what we are facing. Right now what we using a VCXO of
50ppb satbility and what we noticed that with the internal clock
there was a shift in frequency of about 5KHz at 3GHz input while
with external Ref shift was around 300Hz. Is it possible to switch
off supply manually for internal oscillator and board still works?
Regards,
Arun Verma
Could you please post an image of the situation, showing the spur
levels?
*From:* Marcus D. Leech via USRP-users
<mailto:usrp-users@lists.ettus.com>
*To:* usrp-users@lists.ettus.com <mailto:usrp-users@lists.ettus.com>
*Sent:* Wednesday, 26 September 2018 9:15 PM
*Subject:* Re: [USRP-users] B205 External Reference issue
On 09/26/2018 02:42 AM, Arun kumar Verma via USRP-users wrote:
Hi
We are using B205i-mini and we found that when I am sleclecting
external Ref using set_clock_source("ëxternal"); I am getting
intermodulation components in Hz.
I think supply for the internal oscillator is still on and it is
not compeletly shutting down. Is there any options to switch off
the suppy of ineternal oscillator through some API.
Regards,
Arun Verma
There is only one clock on the B205 -- a 40MHz VCXO. When you
switch to "external", the FPGA implements a clock-steering
"servo" that phase-locks that 40MHz clock to the external reference.
You're probably seeing very low-level clock spurs that appear as a
result of the servo algorithm.
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Re: [USRP-users] B205 External Reference issue
I have tried that but it increases when i reduce amplitude , in fact for DC
coupled ref i am getting best result.
I have checked the schematic and in that if i remove R37 and R38 then my
internal clock will disconnected but i am not sure whether board will work with
only external clock or not. Can you verify this. I want to disconnect internal
clock and want only external clock as there I am not getting any drift.
Arun
From: Marcus D. Leech
To: Arun kumar Verma ; "usrp-users@lists.ettus.com"
Sent: Sunday, 30 September 2018 2:19 AM
Subject: Re: [USRP-users] B205 External Reference issue
On 09/29/2018 02:20 PM, Arun kumar Verma wrote:
Hi
Please find the screenshots as you have asked. One image is when we are
setting ref to internal but external not connected that time it is clean and
other images is when we are connecting external ref .
Regards, arun verma
Does the magnitude of this small spur diminish if you reduce the amplitude of
your external reference?
From: Marcus D. Leech
To: Arun kumar Verma ; "usrp-users@lists.ettus.com"
Sent: Wednesday, 26 September 2018 11:56 PM
Subject: Re: [USRP-users] B205 External Reference issue
On 09/26/2018 02:24 PM, Arun kumar Verma wrote:
Hi Marcus
well I am connecting external ref of 10MHz on Ref Input SMA connector and
once I connect this and set my clock source for external source then we are
getting spurios, these spurs are low but for AM,FM audio demodulation even Hz
suprs can create probelem and that is what we are facing. Right now what we
using a VCXO of 50ppb satbility and what we noticed that with the internal
clock there was a shift in frequency of about 5KHz at 3GHz input while with
external Ref shift was around 300Hz. Is it possible to switch off supply
manually for internal oscillator and board still works?
Regards, Arun Verma
Could you please post an image of the situation, showing the spur levels?
From: Marcus D. Leech via USRP-users
To: usrp-users@lists.ettus.com
Sent: Wednesday, 26 September 2018 9:15 PM
Subject: Re: [USRP-users] B205 External Reference issue
On 09/26/2018 02:42 AM, Arun kumar Verma via USRP-users wrote:
Hi
We are using B205i-mini and we found that when I am sleclecting external Ref
using set_clock_source("ëxternal"); I am getting intermodulation components
in Hz. I think supply for the internal oscillator is still on and it is not
compeletly shutting down. Is there any options to switch off the suppy of
ineternal oscillator through some API.
Regards, Arun Verma
There is only one clock on the B205 -- a 40MHz VCXO. When you switch to
"external", the FPGA implements a clock-steering
"servo" that phase-locks that 40MHz clock to the external reference.
You're probably seeing very low-level clock spurs that appear as a result of
the servo algorithm.
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Re: [USRP-users] B205 External Reference issue
On 09/29/2018 02:20 PM, Arun kumar Verma wrote:
Hi
Please find the screenshots as you have asked. One image is when we
are setting ref to internal but external not connected that time it is
clean and other images is when we are connecting external ref .
Regards,
arun verma
Does the magnitude of this small spur diminish if you reduce the
amplitude of your external reference?
*From:* Marcus D. Leech
*To:* Arun kumar Verma ;
"usrp-users@lists.ettus.com"
*Sent:* Wednesday, 26 September 2018 11:56 PM
*Subject:* Re: [USRP-users] B205 External Reference issue
On 09/26/2018 02:24 PM, Arun kumar Verma wrote:
Hi Marcus
well I am connecting external ref of 10MHz on Ref Input SMA
connector and once I connect this and set my clock source for
external source then we are getting spurios, these spurs are low but
for AM,FM audio demodulation even Hz suprs can create probelem and
that is what we are facing. Right now what we using a VCXO of 50ppb
satbility and what we noticed that with the internal clock there was
a shift in frequency of about 5KHz at 3GHz input while with external
Ref shift was around 300Hz. Is it possible to switch off supply
manually for internal oscillator and board still works?
Regards,
Arun Verma
Could you please post an image of the situation, showing the spur levels?
*From:* Marcus D. Leech via USRP-users
<mailto:usrp-users@lists.ettus.com>
*To:* usrp-users@lists.ettus.com <mailto:usrp-users@lists.ettus.com>
*Sent:* Wednesday, 26 September 2018 9:15 PM
*Subject:* Re: [USRP-users] B205 External Reference issue
On 09/26/2018 02:42 AM, Arun kumar Verma via USRP-users wrote:
Hi
We are using B205i-mini and we found that when I am sleclecting
external Ref using set_clock_source("ëxternal"); I am getting
intermodulation components in Hz.
I think supply for the internal oscillator is still on and it is not
compeletly shutting down. Is there any options to switch off the
suppy of ineternal oscillator through some API.
Regards,
Arun Verma
There is only one clock on the B205 -- a 40MHz VCXO. When you
switch to "external", the FPGA implements a clock-steering
"servo" that phase-locks that 40MHz clock to the external reference.
You're probably seeing very low-level clock spurs that appear as a
result of the servo algorithm.
___
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Re: [USRP-users] B205 External Reference issue
On 09/26/2018 02:24 PM, Arun kumar Verma wrote:
Hi Marcus
well I am connecting external ref of 10MHz on Ref Input SMA connector
and once I connect this and set my clock source for external source
then we are getting spurios, these spurs are low but for AM,FM audio
demodulation even Hz suprs can create probelem and that is what we
are facing. Right now what we using a VCXO of 50ppb satbility and
what we noticed that with the internal clock there was a shift in
frequency of about 5KHz at 3GHz input while with external Ref shift
was around 300Hz. Is it possible to switch off supply manually for
internal oscillator and board still works?
Regards,
Arun Verma
Could you please post an image of the situation, showing the spur levels?
*From:* Marcus D. Leech via USRP-users
*To:* usrp-users@lists.ettus.com
*Sent:* Wednesday, 26 September 2018 9:15 PM
*Subject:* Re: [USRP-users] B205 External Reference issue
On 09/26/2018 02:42 AM, Arun kumar Verma via USRP-users wrote:
Hi
We are using B205i-mini and we found that when I am sleclecting
external Ref using set_clock_source("ëxternal"); I am getting
intermodulation components in Hz.
I think supply for the internal oscillator is still on and it is not
compeletly shutting down. Is there any options to switch off the
suppy of ineternal oscillator through some API.
Regards,
Arun Verma
There is only one clock on the B205 -- a 40MHz VCXO. When you switch
to "external", the FPGA implements a clock-steering
"servo" that phase-locks that 40MHz clock to the external reference.
You're probably seeing very low-level clock spurs that appear as a
result of the servo algorithm.
___
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http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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Re: [USRP-users] B205 External Reference issue
Hi Marcus
well I am connecting external ref of 10MHz on Ref Input SMA connector and once
I connect this and set my clock source for external source then we are getting
spurios, these spurs are low but for AM,FM audio demodulation even Hz suprs can
create probelem and that is what we are facing. Right now what we using a VCXO
of 50ppb satbility and what we noticed that with the internal clock there was a
shift in frequency of about 5KHz at 3GHz input while with external Ref shift
was around 300Hz. Is it possible to switch off supply manually for internal
oscillator and board still works?
Regards,Arun Verma
From: Marcus D. Leech via USRP-users
To: usrp-users@lists.ettus.com
Sent: Wednesday, 26 September 2018 9:15 PM
Subject: Re: [USRP-users] B205 External Reference issue
On 09/26/2018 02:42 AM, Arun kumar Verma via USRP-users wrote:
Hi
We are using B205i-mini and we found that when I am sleclecting external Ref
using set_clock_source("ëxternal"); I am getting intermodulation components in
Hz. I think supply for the internal oscillator is still on and it is not
compeletly shutting down. Is there any options to switch off the suppy of
ineternal oscillator through some API.
Regards, Arun Verma
There is only one clock on the B205 -- a 40MHz VCXO. When you switch to
"external", the FPGA implements a clock-steering
"servo" that phase-locks that 40MHz clock to the external reference.
You're probably seeing very low-level clock spurs that appear as a result of
the servo algorithm.
___
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USRP-users@lists.ettus.com
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Re: [USRP-users] B205 External Reference issue
On 09/26/2018 02:42 AM, Arun kumar Verma via USRP-users wrote:
Hi
We are using B205i-mini and we found that when I am sleclecting
external Ref using set_clock_source("ëxternal"); I am getting
intermodulation components in Hz.
I think supply for the internal oscillator is still on and it is not
compeletly shutting down. Is there any options to switch off the suppy
of ineternal oscillator through some API.
Regards,
Arun Verma
There is only one clock on the B205 -- a 40MHz VCXO. When you switch
to "external", the FPGA implements a clock-steering
"servo" that phase-locks that 40MHz clock to the external reference.
You're probably seeing very low-level clock spurs that appear as a
result of the servo algorithm.
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[USRP-users] B205 External Reference issue
Hi
We are using B205i-mini and we found that when I am sleclecting external Ref
using set_clock_source("ëxternal"); I am getting intermodulation components in
Hz.I think supply for the internal oscillator is still on and it is not
compeletly shutting down. Is there any options to switch off the suppy of
ineternal oscillator through some API.
Regards,Arun Verma
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