Hi all,
I try to build a RFNOC FPGA image for the USRP X310 according to the
"Getting Started with RFNoC Development" web page
(https://kb.ettus.com/Getting_Started_with_RFNoC_Development).
Command:
$ ./uhd_image_builder.py window fft -d x310 -t X310_RFNOC_HG -m 5
--fill-with-fifos
The build process is successful with several critical warnings (see the
attachment with the output of the build process).
When I try to load to new image, the error message "The specified FPGA
image is too large" aborts the process.
My command to load the FPGA image:
$ uhd_image_loader --args "type=x300,addr=192.168.40.2" --fpga-path
~/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/build/usrp_x310_fpga_RFNOC_HG.bit
[INFO] [UHD] linux; GNU C++ version 5.4.0 20160609; Boost_105800;
UHD_4.0.0.rfnoc-devel-788-g1f8463cc
Error: RuntimeError: The specified FPGA image is too large: 15878040 vs.
15878032
Do you have any idea what is going wrong? And do I have to worry about
the critical warnings?
Versions:
FPGA (https://github.com/EttusResearch/fpga.git): branch: rfnoc-devel,
last tag: v3.12.0.0, commit 1b40696a7ede5c2593f36276071460f08bbf24b2,
Author: Martin Braun , Date: Thu Jun 14
18:45:39 2018 -0700
Vivado: v2017.4_AR70455
Python 2.7.12
Thank you for your help,
andreas
palindrome@palindrome1001:~/workarea-rfnoc/uhd/fpga-src/usrp3/tools/scripts$
./uhd_image_builder.py window fft -d x310 -t X310_RFNOC_HG -m 5
--fill-with-fifos
--Using the following blocks to generate image:
* window
* fft
Adding CE instantiation file for 'X310_RFNOC_HG'
changing temporarily working directory to
/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/tools/scripts/../../top/x300
Setting up a 64-bit FPGA build environment for the USRP-X3x0...
- Vivado: Found (/opt/Xilinx/Vivado/2017.4/bin)
Environment successfully initialized.
make -f Makefile.x300.inc bin NAME=X310_RFNOC_HG ARCH=kintex7
PART_ID=xc7k410t/ffg900/-2 BUILD_1G=1 BUILD_10G=1 SFP0_1GBE=1 SFP1_10GBE=1
RFNOC=1 X310=1 TOP_MODULE=x300 EXTRA_DEFS="BUILD_1G=1 BUILD_10G=1 SFP0_1GBE=1
SFP1_10GBE=1 RFNOC=1 X310=1 "
make[1]: Entering directory
'/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300'
BUILDER: Checking tools...
* GNU bash, version 4.3.48(1)-release (x86_64-pc-linux-gnu)
* Python 2.7.12
* Vivado v2017.4_AR70455 (64-bit)
Using parser configuration from:
/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/dev_config.json
[00:00:00] Executing command: vivado -mode batch -source
/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/build_x300.tcl -log
build.log -journal x300.jou
CRITICAL WARNING: [filemgmt 20-1440] File
'/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ddr3_32bit/ddr3_32bit/user_design/rtl/clocking/mig_7series_v4_0_tempmon.v'
already exists in the project as a part of sub-design file
'/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ddr3_32bit/ddr3_32bit.xci'.
Explicitly adding the file outside the scope of the sub-design can lead to
unintended behaviors and is not recommended.
[00:00:12] Current task: Initialization +++ Current Phase: Starting
[00:00:12] Current task: Initialization +++ Current Phase: Finished
[00:00:12] Executing Tcl: synth_design -top x300 -part xc7k410tffg900-2
-verilog_define BUILD_1G=1 -verilog_define BUILD_10G=1 -verilog_define
SFP0_1GBE=1 -verilog_define SFP1_10GBE=1 -verilog_define RFNOC=1
-verilog_define X310=1 -verilog_define GIT_HASH=32'hf1b40696
[00:00:12] Starting Synthesis Command
CRITICAL WARNING: [Constraints 18-1056] Clock 'FPGA_CLK' completely overrides
clock 'FPGA_CLK_p'.
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found
for '-group [get_clocks bus_clk]'.
[/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/timing.xdc:72]
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found
for '-group [get_clocks ioport2_clk]'.
[/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/timing.xdc:72]
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found
for '-group [get_clocks ioport2_clk]'.
[/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/timing.xdc:73]
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found
for '-group [get_clocks rio40_clk]'.
[/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/timing.xdc:73]
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found
for '-group [get_clocks bus_clk]'.
[/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/timing.xdc:74]
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found
for '-group [get_clocks radio_clk]'.
[/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/timing.xdc:74]
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found
for '-group [get_clocks bus_clk_div2]'.
[/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/timing.xdc:75]
