Re: [USRP-users] build uhd rfnoc for e310 get some errors
Hi, I'm seeing the same errors on the master branch not using RFNoC. Probably there is some error in the idle image where the peek is looking at. Printing the sts value results in having some other hex value. Until the idle image is loaded everything is fine though. Nevertheless this error shouldn't impact your operation since it will only occur at the end. Still it would be nice if the error could be fixed. Cheers, Andrej On Tue, Dec 12, 2017 at 08:51:01AM -0500, EJ Kreinar via USRP-users wrote: > Hi Carry, > > This looks like a repeat of an issue from March of this year: > http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2017-March/023950.html > > It doesnt look like it measurably impacts E310 performance. I havent tried > recent builds of rfnoc, so I cannot personally confirm if it's fixed or > not, but I'm not aware of any updates to this issue (I've also seen this on > the mailing list a few times since March). > > Cheers, > EJ > > On Tue, Dec 12, 2017 at 6:46 AM, carry chen via USRP-users < > usrp-users@lists.ettus.com> wrote: > > > Hi,list, > > > > I complie uhd rfnoc version for e310 follow the link: > > > > > > https://kb.ettus.com/Software_Development_on_the_E3xx_USRP_- > > _Building_RFNoC_UHD_/_GNU_Radio_/_gr-ettus_from_Source > > > > > > > > but when run on e310, I get some error: > > > > [INFO] [UHDlinux; GNU C++ version 4.9.2; Boost_105700; > > UHD_4.0.0.rfnoc-devel-409-gec9138eb] > > [INFO] [E300] Loading FPGA image: /home/root/newinstall/usr/ > > share/uhd/images/usrp_e310_fpga_sg3.bit... > > [INFO] [E300] FPGA image loaded > > [INFO] [E300] Initializing core control (global registers)... > > > > [INFO] [E300] Performing register loopback test... > > [INFO] [E300] Register loopback test passed > > [INFO] [RFNOC RADIO] Register loopback test passed > > [INFO] [RFNOC RADIO] Register loopback test passed > > [WARNING] [RFNOC] [0/fosphor_0] defines 2 input buffer sizes, but 1 input > > ports > > [INFO] [AD936X] Performing CODEC loopback test... > > [INFO] [AD936X] CODEC loopback test passed > > [INFO] [AD936X] Performing CODEC loopback test... > > [INFO] [AD936X] CODEC loopback test passed > > [INFO] [CORES] Performing timer loopback test... > > [INFO] [CORES] Timer loopback test passed > > _ > > / > > | Device: E-Series Device > > | _ > > |/ > > | | Mboard: E3XX > > | | product: 30675 > > | | revision: 6 > > | | serial: F65F2F > > | | mac-addr: 00:80:2f:16:0b:fd > > | | FPGA Version: 255.0 > > | | FPGA git hash: f764326-dirty > > | | RFNoC capable: Yes > > | | > > | | Time sources: none, internal, external > > | | Clock sources: internal > > | | Sensors: temp, ref_locked > > | | _ > > | |/ > > | | | RX DSP: 0 > > | | | > > | | | Freq range: 0.000 to 0.000 MHz > > | | _ > > | |/ > > | | | RX DSP: 1 > > | | | > > | | | Freq range: 0.000 to 0.000 MHz > > | | _ > > | |/ > > | | | RX Dboard: A > > | | | ID: E310 MIMO XCVR (0x0110) > > | | | Serial: 3102B9F > > | | | _ > > | | |/ > > | | | | RX Frontend: A > > | | | | Name: FE-RX2 > > | | | | Antennas: TX/RX, RX2 > > | | | | Sensors: temp, rssi, lo_locked > > | | | | Freq range: 50.000 to 6000.000 MHz > > | | | | Gain range PGA: 0.0 to 76.0 step 1.0 dB > > | | | | Bandwidth range: 20.0 to 5600.0 step 0.0 Hz > > | | | | Connection Type: IQ > > | | | | Uses LO offset: No > > | | | _ > > | | |/ > > | | | | RX Frontend: B > > | | | | Name: FE-RX1 > > | | | | Antennas: TX/RX, RX2 > > | | | | Sensors: temp, rssi, lo_locked > > | | | | Freq range: 50.000 to 6000.000 MHz > > | | | | Gain range PGA: 0.0 to 76.0 step 1.0 dB > > | | | | Bandwidth range: 20.0 to 5600.0 step 0.0 Hz > > | | | | Connection Type: IQ > > | | | | Uses LO offset: No > > | | | _ > > | | |/ > > | | | | RX Codec: A > > | | | | Name: E3x0 RX dual ADC > > | | | | Gain Elements: None > > | | _ > > | |/ > > | | | TX DSP: 0 > > | | | > > | | | Freq range: 0.000 to 0.000 MHz > > | | _ > > | |/ > > | | | TX DSP: 1 > > | | | > > | | | Freq range: 0.000 to 0.000 MHz > > | |
Re: [USRP-users] build uhd rfnoc for e310 get some errors
Hi Carry, This looks like a repeat of an issue from March of this year: http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2017-March/023950.html It doesnt look like it measurably impacts E310 performance. I havent tried recent builds of rfnoc, so I cannot personally confirm if it's fixed or not, but I'm not aware of any updates to this issue (I've also seen this on the mailing list a few times since March). Cheers, EJ On Tue, Dec 12, 2017 at 6:46 AM, carry chen via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi,list, > > I complie uhd rfnoc version for e310 follow the link: > > > https://kb.ettus.com/Software_Development_on_the_E3xx_USRP_- > _Building_RFNoC_UHD_/_GNU_Radio_/_gr-ettus_from_Source > > > > but when run on e310, I get some error: > > [INFO] [UHDlinux; GNU C++ version 4.9.2; Boost_105700; > UHD_4.0.0.rfnoc-devel-409-gec9138eb] > [INFO] [E300] Loading FPGA image: /home/root/newinstall/usr/ > share/uhd/images/usrp_e310_fpga_sg3.bit... > [INFO] [E300] FPGA image loaded > [INFO] [E300] Initializing core control (global registers)... > > [INFO] [E300] Performing register loopback test... > [INFO] [E300] Register loopback test passed > [INFO] [RFNOC RADIO] Register loopback test passed > [INFO] [RFNOC RADIO] Register loopback test passed > [WARNING] [RFNOC] [0/fosphor_0] defines 2 input buffer sizes, but 1 input > ports > [INFO] [AD936X] Performing CODEC loopback test... > [INFO] [AD936X] CODEC loopback test passed > [INFO] [AD936X] Performing CODEC loopback test... > [INFO] [AD936X] CODEC loopback test passed > [INFO] [CORES] Performing timer loopback test... > [INFO] [CORES] Timer loopback test passed > _ > / > | Device: E-Series Device > | _ > |/ > | | Mboard: E3XX > | | product: 30675 > | | revision: 6 > | | serial: F65F2F > | | mac-addr: 00:80:2f:16:0b:fd > | | FPGA Version: 255.0 > | | FPGA git hash: f764326-dirty > | | RFNoC capable: Yes > | | > | | Time sources: none, internal, external > | | Clock sources: internal > | | Sensors: temp, ref_locked > | | _ > | |/ > | | | RX DSP: 0 > | | | > | | | Freq range: 0.000 to 0.000 MHz > | | _ > | |/ > | | | RX DSP: 1 > | | | > | | | Freq range: 0.000 to 0.000 MHz > | | _ > | |/ > | | | RX Dboard: A > | | | ID: E310 MIMO XCVR (0x0110) > | | | Serial: 3102B9F > | | | _ > | | |/ > | | | | RX Frontend: A > | | | | Name: FE-RX2 > | | | | Antennas: TX/RX, RX2 > | | | | Sensors: temp, rssi, lo_locked > | | | | Freq range: 50.000 to 6000.000 MHz > | | | | Gain range PGA: 0.0 to 76.0 step 1.0 dB > | | | | Bandwidth range: 20.0 to 5600.0 step 0.0 Hz > | | | | Connection Type: IQ > | | | | Uses LO offset: No > | | | _ > | | |/ > | | | | RX Frontend: B > | | | | Name: FE-RX1 > | | | | Antennas: TX/RX, RX2 > | | | | Sensors: temp, rssi, lo_locked > | | | | Freq range: 50.000 to 6000.000 MHz > | | | | Gain range PGA: 0.0 to 76.0 step 1.0 dB > | | | | Bandwidth range: 20.0 to 5600.0 step 0.0 Hz > | | | | Connection Type: IQ > | | | | Uses LO offset: No > | | | _ > | | |/ > | | | | RX Codec: A > | | | | Name: E3x0 RX dual ADC > | | | | Gain Elements: None > | | _ > | |/ > | | | TX DSP: 0 > | | | > | | | Freq range: 0.000 to 0.000 MHz > | | _ > | |/ > | | | TX DSP: 1 > | | | > | | | Freq range: 0.000 to 0.000 MHz > | | _ > | |/ > | | | TX Dboard: A > | | | ID: E310 MIMO XCVR (0x0110) > | | | Serial: 3102B9F > | | | _ > | | |/ > | | | | TX Frontend: A > | | | | Name: FE-TX2 > | | | | Antennas: TX/RX > | | | | Sensors: temp, lo_locked > | | | | Freq range: 50.000 to 6000.000 MHz > | | | | Gain range PGA: 0.0 to 89.8 step 0.2 dB > | | | | Bandwidth range: 20.0 to 5600.0 step 0.0 Hz > | | | | Connection Type: IQ > | | | | Uses LO offset: No > | | | _ > | | |/ > | | | |
[USRP-users] build uhd rfnoc for e310 get some errors
Hi,list, I complie uhd rfnoc version for e310 follow the link: https://kb.ettus.com/Software_Development_on_the_E3xx_USRP_-_Building_RFNoC_UHD_/_GNU_Radio_/_gr-ettus_from_Source but when run on e310, I get some error: [INFO] [UHDlinux; GNU C++ version 4.9.2; Boost_105700; UHD_4.0.0.rfnoc-devel-409-gec9138eb] [INFO] [E300] Loading FPGA image: /home/root/newinstall/usr/share/uhd/images/usrp_e310_fpga_sg3.bit... [INFO] [E300] FPGA image loaded [INFO] [E300] Initializing core control (global registers)... [INFO] [E300] Performing register loopback test... [INFO] [E300] Register loopback test passed [INFO] [RFNOC RADIO] Register loopback test passed [INFO] [RFNOC RADIO] Register loopback test passed [WARNING] [RFNOC] [0/fosphor_0] defines 2 input buffer sizes, but 1 input ports [INFO] [AD936X] Performing CODEC loopback test... [INFO] [AD936X] CODEC loopback test passed [INFO] [AD936X] Performing CODEC loopback test... [INFO] [AD936X] CODEC loopback test passed [INFO] [CORES] Performing timer loopback test... [INFO] [CORES] Timer loopback test passed _ / | Device: E-Series Device | _ |/ | | Mboard: E3XX | | product: 30675 | | revision: 6 | | serial: F65F2F | | mac-addr: 00:80:2f:16:0b:fd | | FPGA Version: 255.0 | | FPGA git hash: f764326-dirty | | RFNoC capable: Yes | | | | Time sources: none, internal, external | | Clock sources: internal | | Sensors: temp, ref_locked | | _ | |/ | | | RX DSP: 0 | | | | | | Freq range: 0.000 to 0.000 MHz | | _ | |/ | | | RX DSP: 1 | | | | | | Freq range: 0.000 to 0.000 MHz | | _ | |/ | | | RX Dboard: A | | | ID: E310 MIMO XCVR (0x0110) | | | Serial: 3102B9F | | | _ | | |/ | | | | RX Frontend: A | | | | Name: FE-RX2 | | | | Antennas: TX/RX, RX2 | | | | Sensors: temp, rssi, lo_locked | | | | Freq range: 50.000 to 6000.000 MHz | | | | Gain range PGA: 0.0 to 76.0 step 1.0 dB | | | | Bandwidth range: 20.0 to 5600.0 step 0.0 Hz | | | | Connection Type: IQ | | | | Uses LO offset: No | | | _ | | |/ | | | | RX Frontend: B | | | | Name: FE-RX1 | | | | Antennas: TX/RX, RX2 | | | | Sensors: temp, rssi, lo_locked | | | | Freq range: 50.000 to 6000.000 MHz | | | | Gain range PGA: 0.0 to 76.0 step 1.0 dB | | | | Bandwidth range: 20.0 to 5600.0 step 0.0 Hz | | | | Connection Type: IQ | | | | Uses LO offset: No | | | _ | | |/ | | | | RX Codec: A | | | | Name: E3x0 RX dual ADC | | | | Gain Elements: None | | _ | |/ | | | TX DSP: 0 | | | | | | Freq range: 0.000 to 0.000 MHz | | _ | |/ | | | TX DSP: 1 | | | | | | Freq range: 0.000 to 0.000 MHz | | _ | |/ | | | TX Dboard: A | | | ID: E310 MIMO XCVR (0x0110) | | | Serial: 3102B9F | | | _ | | |/ | | | | TX Frontend: A | | | | Name: FE-TX2 | | | | Antennas: TX/RX | | | | Sensors: temp, lo_locked | | | | Freq range: 50.000 to 6000.000 MHz | | | | Gain range PGA: 0.0 to 89.8 step 0.2 dB | | | | Bandwidth range: 20.0 to 5600.0 step 0.0 Hz | | | | Connection Type: IQ | | | | Uses LO offset: No | | | _ | | |/ | | | | TX Frontend: B | | | | Name: FE-TX1 | | | | Antennas: TX/RX | | | | Sensors: temp, lo_locked | | | | Freq range: 50.000 to 6000.000 MHz | | | | Gain range PGA: 0.0 to 89.8 step 0.2 dB | | | | Bandwidth range: 20.0 to 5600.0 step 0.0 Hz | | | | Connection Type: IQ | | | | Uses LO offset: No | | | _ | | |/ | | | | TX Codec: A | | | | Name: E3x0 TX dual DAC | | | | Gain Elements: None | | _ | |/ | | | RFNoC blocks on this device: | | | | | | * Radio_0 | | | * FIFO_0 | | | * Window_0 | | |
