The Virtio SPI (Serial Peripheral Interface) device is a virtual
SPI controller that allows the driver to operate and use the SPI
controller under the control of the host.
This patch adds the specification for virtio-spi.
Signed-off-by: Haixu Cui
Reviewed-by: Viresh Kumar
---
device-types/spi/description.tex| 281
device-types/spi/device-conformance.tex | 7 +
device-types/spi/driver-conformance.tex | 7 +
3 files changed, 295 insertions(+)
create mode 100644 device-types/spi/description.tex
create mode 100644 device-types/spi/device-conformance.tex
create mode 100644 device-types/spi/driver-conformance.tex
diff --git a/device-types/spi/description.tex b/device-types/spi/description.tex
new file mode 100644
index 000..b76258c
--- /dev/null
+++ b/device-types/spi/description.tex
@@ -0,0 +1,281 @@
+\section{SPI Controller Device}\label{sec:Device Types / SPI Controller Device}
+
+The Virtio SPI (Serial Peripheral Interface) device is a virtual SPI
controller that
+allows the driver to operate and use the SPI controller under the control of
the host,
+either a physical SPI controller, or an emulated one.
+
+The Virtio SPI device has a single virtqueue. SPI transfer requests are placed
into
+the virtqueue by the driver, and are serviced by the device.
+
+In a typical host and guest architecture with the Virtio SPI device, the
Virtio SPI driver
+is the front-end running in the guest, and the Virtio SPI device is the
back-end
+in the host.
+
+\subsection{Device ID}\label{sec:Device Types / SPI Controller Device / Device
ID}
+45
+
+\subsection{Virtqueues}\label{sec:Device Types / SPI Controller Device /
Virtqueues}
+
+\begin{description}
+\item[0] requestq
+\end{description}
+
+\subsection{Feature bits}\label{sec:Device Types / SPI Controller Device /
Feature bits}
+
+None
+
+\subsection{Device configuration layout}\label{sec:Device Types / SPI
Controller Device / Device configuration layout}
+
+All fields of this configuration are mandatory and read-only for the driver.
+The config space shows the features and settings supported by the device.
+
+\begin{lstlisting}
+struct virtio_spi_config {
+ u8 cs_max_number;
+ u8 cs_change_supported;
+ u8 tx_nbits_supported;
+ u8 rx_nbits_supported;
+ le32 bits_per_word_mask;
+ le32 mode_func_supported;
+ le32 max_freq_hz;
+ le32 max_word_delay_ns;
+ le32 max_cs_setup_ns;
+ le32 max_cs_hold_ns;
+ le32 max_cs_inactive_ns;
+};
+\end{lstlisting}
+
+\field{cs_max_number} is the maximum number of chipselect the device supports.
+
+Note: chipselect is an electrical signal, which is used to select the SPI
peripherals connected
+to the controller.
+
+\field{cs_change_supported} indicates if the device supports to toggle
chipselect
+after each transfer in one message:
+0: unsupported, chipselect will be kept in active state throughout the
message transaction;
+1: supported.
+
+Note: Message here contains a sequence of SPI transfers.
+
+\field{tx_nbits_supported} and \field{rx_nbits_supported} indicate the
different n-bit transfer
+modes supported by the device, for writing and reading respectively. SINGLE is
always supported.
+A set bit here indicates that the corresponding n-bit transfer is supported,
otherwise not:
+bit 0: DUAL;
+bit 1: QUAD;
+bit 2: OCTAL;
+other bits are reserved and must be set as 0 by the device.
+
+Note: The commonly used SPI n-bit transfer options are:
+\begin{itemize}
+\item SINGLE: 1-bit transfer
+\item DUAL: 2-bit transfer
+\item QUAD: 4-bit transfer
+\item OCTAL: 8-bit transfer
+\end{itemize}
+
+\field{bits_per_word_mask} is a mask indicating which values of bits_per_word
are supported.
+If bit n of \field{bits_per_word_mask} is set, the bits_per_word with value
(n+1) is supported.
+If all bits are not set, bits_per_word can be any value from 1 to 32.
+
+Note: bits_per_word corresponds to \field{bits_per_word} in \field{struct
virtio_spi_transfer_head}.
+
+\field{mode_func_supported} indicates whether the following features are
supported or not:
+bit 0-1: CPHA feature,
+0b00: invalid, must support as least one CPHA setting.
+0b01: supports CPHA=0 only;
+0b10: supports CPHA=1 only;
+0b11: supports CPHA=0 and CPHA=1;
+
+bit 2-3: CPOL feature,
+0b00: invalid, must support as least one CPOL setting.
+0b01: supports CPOL=0 only;
+0b10: supports CPOL=1 only;
+0b11: supports CPOL=0 and CPOL=1;
+
+bit 4: chipselect active high feature, 0 for unsupported and 1 for
supported,
+chipselect active low must always be supported.
+
+bit 5: LSB first feature, 0 for unsupported and 1 for supported, MSB
first must always be
+supported.
+
+bit 6: loopback mode feature, 0 for unsupported and 1 for supported,
normal mode
+mus
