[Xen-devel] [GIT PULL] xen: fix for 4.10 rc4

[Juergen Gross]

Linus,

Please git pull the following tag:

 git://git.kernel.org/pub/scm/linux/kernel/git/xen/tip.git 
for-linus-4.10-rc4-tag

It contains a fix for Xen running in nested virtualization environment.

Thanks.

Juergen

 drivers/xen/platform-pci.c | 71 ++
 1 file changed, 71 insertions(+)

Stefano Stabellini (1):
  partially revert "xen: Remove event channel notification through Xen PCI 
platform device"

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Re: [Xen-devel] [PATCH v2 3/3] xen: optimize xenbus driver for multiple concurrent xenstore accesses

[Juergen Gross]

On 18/01/17 21:14, Boris Ostrovsky wrote:
> On 01/16/2017 09:15 AM, Juergen Gross wrote:
>> +
>> +static uint32_t xs_request_enter(struct xb_req_data *req)
>> +{
>> +uint32_t rq_id;
>> +
>> +req->type = req->msg.type;
>> +
>> +spin_lock(_state_lock);
>> +for (;;) {
>> +if (req->msg.tx_id != 0)
>> +break;
>> +if (xs_suspend_active) {
>> +spin_unlock(_state_lock);
>> +wait_event(xs_state_enter_wq, xs_suspend_active == 0);
>> +spin_lock(_state_lock);
>> +continue;
>> +}
>> +if (req->type == XS_TRANSACTION_START)
>> +xs_state_users++;
>> +break;
>> +}
>> +xs_state_users++;
>> +rq_id = xs_request_id++;
>> +spin_unlock(_state_lock);
>> +
>> +return rq_id;
>> +}
> 
> I should have noticed this last time but I've been looking at this code
> again and I don't think I understand why you are incrementing count for
> XS_TRANSACTION_START inside the loop.
> 
> In fact, why not just 'while(xs_suspend_active) {}' loop?

That's a valid question.

I'll change it. The reason to have the larger loop body isn't existing
any longer.


Juergen


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[Xen-devel] [PATCH v2] tools/tests: add xenstore testing framework

[Juergen Gross]

Add tools/tests/xenstore for a framework to do tests of xenstore.
The aim is to test for correctness and performance.

Add a test program containing some tests meant to be run against any
xenstore implementation (xenstored, oxenstored, xenstore-stubdom).

It is using libxenstore for access to xenstore and supports multiple
tests to be either selected all or individually. All tests are using
/local/domain//xenstore-test/ as base for doing the
tests. This allows multiple instances of the program to run in
parallel.

Signed-off-by: Juergen Gross 
---
V2: corrected read/write 3000 test table entries
coding style
remove xenstore-test node if empty at exit
---
 .gitignore |   1 +
 tools/tests/Makefile   |   1 +
 tools/tests/xenstore/Makefile  |  27 +++
 tools/tests/xenstore/xs-test.c | 536 +
 4 files changed, 565 insertions(+)
 create mode 100644 tools/tests/xenstore/Makefile
 create mode 100644 tools/tests/xenstore/xs-test.c

diff --git a/.gitignore b/.gitignore
index 7689596..d9982f6 100644
--- a/.gitignore
+++ b/.gitignore
@@ -212,6 +212,7 @@ tools/tests/x86_emulator/blowfish.h
 tools/tests/x86_emulator/test_x86_emulator
 tools/tests/x86_emulator/x86_emulate
 tools/tests/xen-access/xen-access
+tools/tests/xenstore/xs-test
 tools/tests/regression/installed/*
 tools/tests/regression/build/*
 tools/tests/regression/downloads/*
diff --git a/tools/tests/Makefile b/tools/tests/Makefile
index adeb120..6397761 100644
--- a/tools/tests/Makefile
+++ b/tools/tests/Makefile
@@ -12,6 +12,7 @@ SUBDIRS-y += regression
 endif
 SUBDIRS-$(CONFIG_X86) += x86_emulator
 SUBDIRS-y += xen-access
+SUBDIRS-y += xenstore
 
 .PHONY: all clean install distclean
 all clean distclean: %: subdirs-%
diff --git a/tools/tests/xenstore/Makefile b/tools/tests/xenstore/Makefile
new file mode 100644
index 000..6c85f98
--- /dev/null
+++ b/tools/tests/xenstore/Makefile
@@ -0,0 +1,27 @@
+XEN_ROOT=$(CURDIR)/../../..
+include $(XEN_ROOT)/tools/Rules.mk
+
+CFLAGS += -Werror
+
+CFLAGS += $(CFLAGS_libxenstore)
+
+TARGETS-y := xs-test
+TARGETS := $(TARGETS-y)
+
+.PHONY: all
+all: build
+
+.PHONY: build
+build: $(TARGETS)
+
+.PHONY: clean
+clean:
+   $(RM) *.o $(TARGETS) *~ $(DEPS)
+
+.PHONY: distclean
+distclean: clean
+
+xs-test: xs-test.o Makefile
+   $(CC) -o $@ $< $(LDFLAGS) $(LDLIBS_libxenstore)
+
+-include $(DEPS)
diff --git a/tools/tests/xenstore/xs-test.c b/tools/tests/xenstore/xs-test.c
new file mode 100644
index 000..eb5fe55
--- /dev/null
+++ b/tools/tests/xenstore/xs-test.c
@@ -0,0 +1,536 @@
+/*
+ * xs-test.c
+ *
+ * Do Xenstore tests.
+ *
+ * Copyright (C) 2016  Juergen Gross ,
+ * SUSE Linux GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms and conditions of the GNU General Public
+ * License, version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this program; If not, see .
+ */
+
+#define _GNU_SOURCE
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define TEST_PATH "xenstore-test"
+#define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0]))
+#define WRITE_BUFFERS_N10
+#define WRITE_BUFFERS_SIZE 4000
+#define MAX_TA_LOOPS   100
+
+struct test {
+char *name;
+int (*func_init)(uintptr_t par);
+int (*func)(uintptr_t par);
+int (*func_deinit)(uintptr_t par);
+uintptr_t par;
+char *descr;
+};
+
+static struct xs_handle *xsh;
+static char *path;
+static char *paths[WRITE_BUFFERS_N];
+static char write_buffers[WRITE_BUFFERS_N][WRITE_BUFFERS_SIZE];
+static int ta_loops;
+
+static struct option options[] = {
+{ "list-tests", 0, NULL, 'l' },
+{ "test", 1, NULL, 't' },
+{ "random", 1, NULL, 'r' },
+{ "help", 0, NULL, 'h' },
+{ "iterations", 1, NULL, 'i' },
+{ NULL, 0, NULL, 0 }
+};
+
+static int call_test(struct test *tst, int iters, bool no_clock)
+{
+char *stage = "?";
+struct timespec tp1, tp2;
+uint64_t nsec, nsec_min, nsec_max, nsec_sum;
+int i, ret;
+
+nsec_min = -1;
+nsec_max = 0;
+nsec_sum = 0;
+
+for ( i = 0; i < iters; i++ )
+{
+stage = "pre-init";
+xs_rm(xsh, XBT_NULL, path);
+if ( !xs_write(xsh, XBT_NULL, path, "", 0) )
+{
+ret = errno;
+break;
+}
+stage = "init";
+ret = tst->func_init(tst->par);
+if ( ret )
+break;
+if ( clock_gettime(CLOCK_REALTIME, ) )
+no_clock = true;
+stage = "run";
+ret = 

Re: [Xen-devel] [PATCH v5 01/24] docs: create L2 Cache Allocation Technology (CAT) feature document

[Yi Sun]

On 17-01-18 10:11:15, Dario Faggioli wrote:
> On Wed, 2017-01-18 at 10:02 +0800, Yi Sun wrote:
> > This patch creates L2 CAT feature document in doc/features/.
> > It describes details of L2 CAT.
> > 
> > Signed-off-by: Yi Sun 
> > ---
> >
> Hey,
> 
> it is very very useful to put _RIGHT_HERE_ a summary of what changed,
> within, this patch, wrt the previous version.
> 
> That helps reviewers quite a bit, especially in making sure that you
> hav considered and addressed comments made during the previous
> iterations.
> 
I have resend the patches with summary of what changed. Please check.
Thanks!

Your comments for these patches will be recorded.

> >  docs/features/intel_psr_l2_cat.pandoc | 347
> > ++
> >  1 file changed, 347 insertions(+)
> >  create mode 100644 docs/features/intel_psr_l2_cat.pandoc
> 
> > --- /dev/null
> > +++ b/docs/features/intel_psr_l2_cat.pandoc
> > +
> > +# User details
> > +
> > +* Feature Enabling:
> > +
> > +  Add "psr=cat" to boot line parameter to enable all supported level
> > CAT
> > +  features.
> > +
> > +* xl interfaces:
> > +
> > +  1. `psr-cat-show [OPTIONS] domain-id`:
> > +
> > + Show domain L2 or L3 CAT CBM.
> > +
> > + New option `-l` is added.
> > + `-l2`: Show cbm for L2 cache.
> > + `-l3`: Show cbm for L3 cache.
> > +
> > + If neither `-l2` nor `-l3` is given, show both of them. If any
> > one
> > + is not supported, will print error info.
> > +
> I actually think the best behavior would be:
>  - if -lX is specified, and LX is not supported ==> print error;

Will return error for this case. But the error log is not accurate so far.
Will refine this. Thanks!

>  - if no -l is specified ==> print info about the supported levels.
> 
That is my bad. In fact, the l3 info will be shown if no -l is specified.

> (See comment on patch 21.)
> 
> > +## The relationship between L2 CAT and L3 CAT/CDP
> > +
> > +L2 CAT is independent of L3 CAT/CDP, which means L2 CAT would be
> > enabled
> > +while L3 CAT/CDP is disabled, or L2 CAT and L3 CAT/CDP are all
> > enabled.
> > +
> 
> I find 'would be enabled' and 'are all enabled' a bit confusing.
> 
> Maybe: "which means L2 cat can be enabled while L3 CAT/CDP is disabled,
> or L2 CAT and L3 CAT/CDP can be all enabled"
> 
> ?
Agree, thank you!

> 
> Regards,
> Dario
> -- 
> <> (Raistlin Majere)
> -
> Dario Faggioli, Ph.D, http://about.me/dario.faggioli
> Senior Software Engineer, Citrix Systems R Ltd., Cambridge (UK)



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[Xen-devel] [PATCH RESEND v5 20/24] x86: L2 CAT: implement set value flow.

[Yi Sun]

This patch implements L2 CAT set value related callback functions
and domctl interface.

Signed-off-by: Yi Sun 
---
v5:
- remove type check in callback function.
- modify return value of callback functions because we do not need them
  to return number of entries the feature uses. In caller, we call
  'get_cos_num' to get the number of entries the feature uses.
- remove 'l2_cat_get_cos_max_from_type'.
- rename 'l2_cat_exceeds_cos_max' to 'l2_cat_fits_cos_max'.
---
 xen/arch/x86/domctl.c   |  6 +++
 xen/arch/x86/psr.c  | 92 +
 xen/include/asm-x86/msr-index.h |  1 +
 xen/include/public/domctl.h |  1 +
 4 files changed, 100 insertions(+)

diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c
index af6153d..2767c6a 100644
--- a/xen/arch/x86/domctl.c
+++ b/xen/arch/x86/domctl.c
@@ -1382,6 +1382,12 @@ long arch_do_domctl(
   PSR_CBM_TYPE_L3_DATA);
 break;
 
+case XEN_DOMCTL_PSR_CAT_OP_SET_L2_CBM:
+ret = psr_set_val(d, domctl->u.psr_cat_op.target,
+  domctl->u.psr_cat_op.data,
+  PSR_CBM_TYPE_L2);
+break;
+
 case XEN_DOMCTL_PSR_CAT_OP_GET_L3_CBM:
 ret = psr_get_val(d, domctl->u.psr_cat_op.target,
   >u.psr_cat_op.data,
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index 1fad540..13d85e0 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -741,10 +741,102 @@ static bool l2_cat_get_val(const struct feat_node *feat, 
unsigned int cos,
 return true;
 }
 
+static unsigned int l2_cat_get_cos_num(const struct feat_node *feat)
+{
+/* L2 CAT uses one COS. */
+return 1;
+}
+
+static int l2_cat_get_old_val(uint64_t val[],
+  const struct feat_node *feat,
+  unsigned int old_cos)
+{
+if ( old_cos > feat->info.l2_cat_info.cos_max )
+/* Use default value. */
+old_cos = 0;
+
+val[0] = feat->cos_reg_val[old_cos];
+
+return 0;
+}
+
+static int l2_cat_set_new_val(uint64_t val[],
+  const struct feat_node *feat,
+  enum cbm_type type,
+  uint64_t m)
+{
+if ( !psr_check_cbm(feat->info.l2_cat_info.cbm_len, m) )
+return -EINVAL;
+
+val[0] = m;
+
+return 0;
+}
+
+static int l2_cat_compare_val(const uint64_t val[],
+  const struct feat_node *feat,
+  unsigned int cos, bool *found)
+{
+uint64_t l2_def_cbm;
+
+l2_def_cbm = (1ull << feat->info.l2_cat_info.cbm_len) - 1;
+
+if ( cos > feat->info.l2_cat_info.cos_max )
+{
+if ( val[0] != l2_def_cbm )
+{
+*found = false;
+return -ENOENT;
+}
+*found = true;
+}
+else
+*found = (val[0] == feat->cos_reg_val[cos]);
+
+return 0;
+}
+
+static bool l2_cat_fits_cos_max(const uint64_t val[],
+const struct feat_node *feat,
+unsigned int cos)
+{
+uint64_t l2_def_cbm;
+
+l2_def_cbm = (1ull << feat->info.l2_cat_info.cbm_len) - 1;
+
+if ( cos > feat->info.l2_cat_info.cos_max &&
+ val[0] != l2_def_cbm )
+/*
+ * Exceed cos_max and value to set is not default,
+ * return error.
+ */
+return false;
+
+return true;
+}
+
+static int l2_cat_write_msr(unsigned int cos, const uint64_t val[],
+struct feat_node *feat)
+{
+if ( cos > feat->info.l2_cat_info.cos_max )
+return -EINVAL;
+
+feat->cos_reg_val[cos] = val[0];
+wrmsrl(MSR_IA32_PSR_L2_MASK(cos), val[0]);
+
+return 0;
+}
+
 struct feat_ops l2_cat_ops = {
 .get_cos_max = l2_cat_get_cos_max,
 .get_feat_info = l2_cat_get_feat_info,
 .get_val = l2_cat_get_val,
+.get_cos_num = l2_cat_get_cos_num,
+.get_old_val = l2_cat_get_old_val,
+.set_new_val = l2_cat_set_new_val,
+.compare_val = l2_cat_compare_val,
+.fits_cos_max = l2_cat_fits_cos_max,
+.write_msr = l2_cat_write_msr,
 };
 
 static void __init parse_psr_bool(char *s, char *value, char *feature,
diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index 98dbff1..a41e63a 100644
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -343,6 +343,7 @@
 #define MSR_IA32_PSR_L3_MASK(n)(0x0c90 + (n))
 #define MSR_IA32_PSR_L3_MASK_CODE(n)   (0x0c90 + (n) * 2 + 1)
 #define MSR_IA32_PSR_L3_MASK_DATA(n)   (0x0c90 + (n) * 2)
+#define MSR_IA32_PSR_L2_MASK(n)(0x0d10 + (n))
 
 /* Intel Model 6 */
 #define MSR_P6_PERFCTR(n)  (0x00c1 + (n))
diff --git a/xen/include/public/domctl.h b/xen/include/public/domctl.h
index 8c183ba..523a2cd 100644
--- 

[Xen-devel] [PATCH RESEND v5 23/24] tools: L2 CAT: support set cbm for L2 CAT.

[Yi Sun]

This patch implements the xl/xc changes to support set CBM
for L2 CAT.

The new level option is introduced to original CAT setting
command in order to set CBM for specified level CAT.
- 'xl psr-cat-cbm-set' is updated to set cache capacity
  bitmasks(CBM) for a domain according to input cache level.

root@:~$ xl psr-cat-cbm-set -l2 1 0x7f

root@:~$ xl psr-cat-show -l2 1
Socket ID   : 0
Default CBM : 0xff
   ID NAME CBM
1 ubuntu140x7f

Signed-off-by: He Chen 
Signed-off-by: Yi Sun 
---
 tools/libxc/xc_psr.c  |  3 +++
 tools/libxl/xl_cmdimpl.c  | 31 ---
 tools/libxl/xl_cmdtable.c |  1 +
 3 files changed, 24 insertions(+), 11 deletions(-)

diff --git a/tools/libxc/xc_psr.c b/tools/libxc/xc_psr.c
index f0aed2d..67556bb 100644
--- a/tools/libxc/xc_psr.c
+++ b/tools/libxc/xc_psr.c
@@ -266,6 +266,9 @@ int xc_psr_cat_set_domain_data(xc_interface *xch, uint32_t 
domid,
 case XC_PSR_CAT_L3_CBM_DATA:
 cmd = XEN_DOMCTL_PSR_CAT_OP_SET_L3_DATA;
 break;
+case XC_PSR_CAT_L2_CBM:
+cmd = XEN_DOMCTL_PSR_CAT_OP_SET_L2_CBM;
+break;
 default:
 errno = EINVAL;
 return -1;
diff --git a/tools/libxl/xl_cmdimpl.c b/tools/libxl/xl_cmdimpl.c
index cdcee5f..a32438c 100644
--- a/tools/libxl/xl_cmdimpl.c
+++ b/tools/libxl/xl_cmdimpl.c
@@ -9523,19 +9523,21 @@ int main_psr_cat_cbm_set(int argc, char **argv)
 char *value;
 libxl_string_list socket_list;
 unsigned long start, end;
-int i, j, len;
+unsigned int i, j, len;
+unsigned int lvl = 3;
 
 static struct option opts[] = {
 {"socket", 1, 0, 's'},
 {"data", 0, 0, 'd'},
 {"code", 0, 0, 'c'},
+{"level", 1, 0, 'l'},
 COMMON_LONG_OPTS
 };
 
 libxl_socket_bitmap_alloc(ctx, _map, 0);
 libxl_bitmap_set_none(_map);
 
-SWITCH_FOREACH_OPT(opt, "s:cd", opts, "psr-cat-cbm-set", 2) {
+SWITCH_FOREACH_OPT(opt, "s:l:cd", opts, "psr-cat-cbm-set", 2) {
 case 's':
 trim(isspace, optarg, );
 split_string_into_string_list(value, ",", _list);
@@ -9555,17 +9557,24 @@ int main_psr_cat_cbm_set(int argc, char **argv)
 case 'c':
 opt_code = 1;
 break;
+case 'l':
+lvl = atoi(optarg);
+break;
 }
 
-if (opt_data && opt_code) {
-fprintf(stderr, "Cannot handle -c and -d at the same time\n");
-return -1;
-} else if (opt_data) {
-type = LIBXL_PSR_CBM_TYPE_L3_CBM_DATA;
-} else if (opt_code) {
-type = LIBXL_PSR_CBM_TYPE_L3_CBM_CODE;
-} else {
-type = LIBXL_PSR_CBM_TYPE_L3_CBM;
+if (lvl == 2)
+type = LIBXL_PSR_CBM_TYPE_L2_CBM;
+else if (lvl == 3) {
+if (opt_data && opt_code) {
+fprintf(stderr, "Cannot handle -c and -d at the same time\n");
+return ERROR_FAIL;
+} else if (opt_data) {
+type = LIBXL_PSR_CBM_TYPE_L3_CBM_DATA;
+} else if (opt_code) {
+type = LIBXL_PSR_CBM_TYPE_L3_CBM_CODE;
+} else {
+type = LIBXL_PSR_CBM_TYPE_L3_CBM;
+}
 }
 
 if (libxl_bitmap_is_empty(_map))
diff --git a/tools/libxl/xl_cmdtable.c b/tools/libxl/xl_cmdtable.c
index c5fbad4..32c3ee5 100644
--- a/tools/libxl/xl_cmdtable.c
+++ b/tools/libxl/xl_cmdtable.c
@@ -550,6 +550,7 @@ struct cmd_spec cmd_table[] = {
   "Set cache capacity bitmasks(CBM) for a domain",
   "[options]  ",
   "-sSpecify the socket to process, otherwise all sockets 
are processed\n"
+  "-l Specify the cache level to process, otherwise L3 
cache is processed\n"
   "-cSet code CBM if CDP is supported\n"
   "-dSet data CBM if CDP is supported\n"
 },
-- 
1.9.1


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[Xen-devel] [PATCH RESEND v5 14/24] x86: refactor psr: implement get hw info flow for CDP.

[Yi Sun]

This patch implements get HW info flow for CDP including L3 CDP callback
function.

It also changes sysctl function to make it work for CDP.

With this patch, 'psr-hwinfo' can work for L3 CDP.

Signed-off-by: Yi Sun 
---
v5:
- rename 'dat[]' to 'data[]'
- remove type check in callback function.
---
 xen/arch/x86/psr.c| 18 ++
 xen/arch/x86/sysctl.c | 24 +---
 2 files changed, 39 insertions(+), 3 deletions(-)

diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index a979128..b856761 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -262,6 +262,10 @@ static enum psr_feat_type psr_cbm_type_to_feat_type(enum 
cbm_type type)
 case PSR_CBM_TYPE_L3:
 feat_type = PSR_SOCKET_L3_CAT;
 break;
+case PSR_CBM_TYPE_L3_DATA:
+case PSR_CBM_TYPE_L3_CODE:
+feat_type = PSR_SOCKET_L3_CDP;
+break;
 default:
 feat_type = 0x;
 break;
@@ -516,8 +520,22 @@ static unsigned int l3_cdp_get_cos_max(const struct 
feat_node *feat)
 return feat->info.l3_cdp_info.cos_max;
 }
 
+static bool l3_cdp_get_feat_info(const struct feat_node *feat,
+ uint32_t data[], uint32_t array_len)
+{
+if ( !data || 3 > array_len )
+return false;
+
+data[CBM_LEN] = feat->info.l3_cdp_info.cbm_len;
+data[COS_MAX] = feat->info.l3_cdp_info.cos_max;
+data[PSR_FLAG] |= XEN_SYSCTL_PSR_CAT_L3_CDP;
+
+return true;
+}
+
 struct feat_ops l3_cdp_ops = {
 .get_cos_max = l3_cdp_get_cos_max,
+.get_feat_info = l3_cdp_get_feat_info,
 };
 
 static void __init parse_psr_bool(char *s, char *value, char *feature,
diff --git a/xen/arch/x86/sysctl.c b/xen/arch/x86/sysctl.c
index d90db78..a4c8cfe 100644
--- a/xen/arch/x86/sysctl.c
+++ b/xen/arch/x86/sysctl.c
@@ -181,9 +181,27 @@ long arch_do_sysctl(
 ret = psr_get_info(sysctl->u.psr_cat_op.target,
PSR_CBM_TYPE_L3, data, 3);
 
-sysctl->u.psr_cat_op.u.l3_info.cbm_len = data[CBM_LEN];
-sysctl->u.psr_cat_op.u.l3_info.cos_max = data[COS_MAX];
-sysctl->u.psr_cat_op.u.l3_info.flags   = data[PSR_FLAG];
+if ( !ret )
+{
+sysctl->u.psr_cat_op.u.l3_info.cbm_len = data[CBM_LEN];
+sysctl->u.psr_cat_op.u.l3_info.cos_max = data[COS_MAX];
+sysctl->u.psr_cat_op.u.l3_info.flags   = data[PSR_FLAG];
+} else {
+/*
+ * Check if CDP is enabled.
+ *
+ * Per spec, L3 CAT and CDP cannot co-exist. So, we need 
replace
+ * output values to CDP's if it is enabled.
+ */
+ret = psr_get_info(sysctl->u.psr_cat_op.target,
+   PSR_CBM_TYPE_L3_CODE, data, 3);
+if ( !ret )
+{
+sysctl->u.psr_cat_op.u.l3_info.cbm_len = data[CBM_LEN];
+sysctl->u.psr_cat_op.u.l3_info.cos_max = data[COS_MAX];
+sysctl->u.psr_cat_op.u.l3_info.flags   = data[PSR_FLAG];
+}
+}
 
 if ( !ret && __copy_field_to_guest(u_sysctl, sysctl, u.psr_cat_op) 
)
 ret = -EFAULT;
-- 
1.9.1


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[Xen-devel] [PATCH RESEND v5 08/24] x86: refactor psr: set value: implement framework.

[Yi Sun]

As set value flow is the most complicated one in psr, it will be
divided to some patches to make things clearer. This patch
implements the set value framework to show a whole picture firstly.

It also changes domctl interface to make it more general.

To make the set value flow be general and can support multiple features
at same time, it includes below steps:
1. Get COS ID of current domain using.
2. Assemble a value array to store all features current value
   in it and replace the current value of the feature which is
   being set to the new input value.
3. Find if there is already a COS ID on which all features'
   values are same as the array. Then, we can reuse this COS
   ID.
4. If fail to find, we need pick an available COS ID. Only COS ID which ref
   is 0 or 1 can be picked.
5. Write all features MSRs according to the COS ID.
6. Update ref according to COS ID.
7. Save the COS ID into current domain's psr_cos_ids[socket] so that we
   can know which COS the domain is using on the socket.

So, some functions are abstracted and the callback functions will be
implemented in next patches.

Here is an example to understand the process. The CPU supports
two featuers, e.g. L3 CAT and L2 CAT. user wants to set L3 CAT
of Dom1 to 0x1ff.
1. Get the old_cos of Dom1 which is 0. L3 CAT is the first
element of feature list. The COS registers values are below at
this time.
---
| COS 0 | COS 1 | COS 2 | ... |
---
L3 CAT  | 0x7ff | ...   | ...   | ... |
---
L2 CAT  | 0xff  | ...   | ...   | ... |
---

2. Assemble The value array to be:
val[0]: 0x1ff
val[1]: 0xff

3. It cannot find a matching COS.

4. Allocate COS 1 to store the value set.

5. Write the COS 1 registers. The COS registers values are
changed to below now.
---
| COS 0 | COS 1 | COS 2 | ... |
---
L3 CAT  | 0x7ff | 0x1ff | ...   | ... |
---
L2 CAT  | 0xff  | 0xff  | ...   | ... |
---

6. The ref[1] is increased to 1 because Dom1 is using it now.

7. Save 1 to Dom1's psr_cos_ids[socket].

Then, user wants to set L3 CAT of Dom2 to 0x1ff too. The old_cos
of Dom2 is 0 too. Repeat above flow.

The val array assembled is:
val[0]: 0x1ff
val[1]: 0xff

So, it can find a matching COS, COS 1. Then, it can reuse COS 1
for Dom2.

The ref[1] is increased to 2 now because both Dom1 and Dom2 are
using this COS ID. Set 1 to Dom2's psr_cos_ids[socket].

Signed-off-by: Yi Sun 
---
v5:
- modify commit message because of function name change.
- change 'alloc_new_cos' to 'pick_avail_cos' to make name accurate.
- divide 'get_old_set_new' to two functions, 'assemble_val_array' and
  'set_new_val_to_array'.
- check feature type when entering 'psr_set_val'.
- remove cast.
- use ASSERT to check ref.
- rename 'dat[]' to 'data[]'
---
 xen/arch/x86/domctl.c |  18 ++---
 xen/arch/x86/psr.c| 202 +-
 xen/include/asm-x86/psr.h |   4 +-
 3 files changed, 210 insertions(+), 14 deletions(-)

diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c
index 11d2127..db56500 100644
--- a/xen/arch/x86/domctl.c
+++ b/xen/arch/x86/domctl.c
@@ -1365,21 +1365,21 @@ long arch_do_domctl(
 switch ( domctl->u.psr_cat_op.cmd )
 {
 case XEN_DOMCTL_PSR_CAT_OP_SET_L3_CBM:
-ret = psr_set_l3_cbm(d, domctl->u.psr_cat_op.target,
- domctl->u.psr_cat_op.data,
- PSR_CBM_TYPE_L3);
+ret = psr_set_val(d, domctl->u.psr_cat_op.target,
+  domctl->u.psr_cat_op.data,
+  PSR_CBM_TYPE_L3);
 break;
 
 case XEN_DOMCTL_PSR_CAT_OP_SET_L3_CODE:
-ret = psr_set_l3_cbm(d, domctl->u.psr_cat_op.target,
- domctl->u.psr_cat_op.data,
- PSR_CBM_TYPE_L3_CODE);
+ret = psr_set_val(d, domctl->u.psr_cat_op.target,
+  domctl->u.psr_cat_op.data,
+  PSR_CBM_TYPE_L3_CODE);
 break;
 
 case XEN_DOMCTL_PSR_CAT_OP_SET_L3_DATA:
-ret = psr_set_l3_cbm(d, domctl->u.psr_cat_op.target,
- domctl->u.psr_cat_op.data,
- PSR_CBM_TYPE_L3_DATA);
+ret = psr_set_val(d, domctl->u.psr_cat_op.target,
+  domctl->u.psr_cat_op.data,
+  PSR_CBM_TYPE_L3_DATA);
 break;
 
 case XEN_DOMCTL_PSR_CAT_OP_GET_L3_CBM:
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index 3cbb60c..050b0df 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -539,18 

[Xen-devel] [PATCH RESEND v5 22/24] tools: L2 CAT: support show cbm for L2 CAT.

[Yi Sun]

This patch implements changes in xl/xc changes to support
showing CBM of L2 CAT.

The new level option is introduced to original CAT showing
command in order to show CBM for specified level CAT.
- 'xl psr-cat-show' is updated to show CBM of a domain
  according to input cache level.

Examples:
root@:~$ xl psr-cat-show -l2 1
Socket ID   : 0
Default CBM : 0xff
   ID NAME CBM
1 ubuntu140x7f

Signed-off-by: He Chen 
Signed-off-by: Yi Sun 
---
v5:
- remove 'L2_CBM' in idl because it has been moved to patch 21.
---
 tools/libxc/include/xenctrl.h |  1 +
 tools/libxc/xc_psr.c  |  3 ++
 tools/libxl/xl_cmdimpl.c  | 81 ---
 tools/libxl/xl_cmdtable.c |  3 +-
 4 files changed, 59 insertions(+), 29 deletions(-)

diff --git a/tools/libxc/include/xenctrl.h b/tools/libxc/include/xenctrl.h
index 7ea0c92..a009625 100644
--- a/tools/libxc/include/xenctrl.h
+++ b/tools/libxc/include/xenctrl.h
@@ -2602,6 +2602,7 @@ enum xc_psr_cat_type {
 XC_PSR_CAT_L3_CBM  = 1,
 XC_PSR_CAT_L3_CBM_CODE = 2,
 XC_PSR_CAT_L3_CBM_DATA = 3,
+XC_PSR_CAT_L2_CBM  = 4,
 };
 typedef enum xc_psr_cat_type xc_psr_cat_type;
 
diff --git a/tools/libxc/xc_psr.c b/tools/libxc/xc_psr.c
index 6c61aa5..f0aed2d 100644
--- a/tools/libxc/xc_psr.c
+++ b/tools/libxc/xc_psr.c
@@ -299,6 +299,9 @@ int xc_psr_cat_get_domain_data(xc_interface *xch, uint32_t 
domid,
 case XC_PSR_CAT_L3_CBM_DATA:
 cmd = XEN_DOMCTL_PSR_CAT_OP_GET_L3_DATA;
 break;
+case XC_PSR_CAT_L2_CBM:
+cmd = XEN_DOMCTL_PSR_CAT_OP_GET_L2_CBM;
+break;
 default:
 errno = EINVAL;
 return -1;
diff --git a/tools/libxl/xl_cmdimpl.c b/tools/libxl/xl_cmdimpl.c
index 42d6827..cdcee5f 100644
--- a/tools/libxl/xl_cmdimpl.c
+++ b/tools/libxl/xl_cmdimpl.c
@@ -9379,7 +9379,7 @@ static void psr_cat_print_one_domain_cbm_type(uint32_t 
domid, uint32_t socketid,
 }
 
 static void psr_cat_print_one_domain_cbm(uint32_t domid, uint32_t socketid,
- bool cdp_enabled)
+ bool cdp_enabled, unsigned int lvl)
 {
 char *domain_name;
 
@@ -9387,27 +9387,38 @@ static void psr_cat_print_one_domain_cbm(uint32_t 
domid, uint32_t socketid,
 printf("%5d%25s", domid, domain_name);
 free(domain_name);
 
-if (!cdp_enabled) {
-psr_cat_print_one_domain_cbm_type(domid, socketid,
-  LIBXL_PSR_CBM_TYPE_L3_CBM);
-} else {
-psr_cat_print_one_domain_cbm_type(domid, socketid,
-  LIBXL_PSR_CBM_TYPE_L3_CBM_CODE);
+switch (lvl) {
+case 3:
+if (!cdp_enabled) {
+psr_cat_print_one_domain_cbm_type(domid, socketid,
+  LIBXL_PSR_CBM_TYPE_L3_CBM);
+} else {
+psr_cat_print_one_domain_cbm_type(domid, socketid,
+  LIBXL_PSR_CBM_TYPE_L3_CBM_CODE);
+psr_cat_print_one_domain_cbm_type(domid, socketid,
+  LIBXL_PSR_CBM_TYPE_L3_CBM_DATA);
+}
+break;
+case 2:
 psr_cat_print_one_domain_cbm_type(domid, socketid,
-  LIBXL_PSR_CBM_TYPE_L3_CBM_DATA);
+  LIBXL_PSR_CBM_TYPE_L2_CBM);
+break;
+default:
+printf("Input lvl %d is wrong!", lvl);
+break;
 }
 
 printf("\n");
 }
 
 static int psr_cat_print_domain_cbm(uint32_t domid, uint32_t socketid,
-bool cdp_enabled)
+bool cdp_enabled, unsigned int lvl)
 {
 int i, nr_domains;
 libxl_dominfo *list;
 
 if (domid != INVALID_DOMID) {
-psr_cat_print_one_domain_cbm(domid, socketid, cdp_enabled);
+psr_cat_print_one_domain_cbm(domid, socketid, cdp_enabled, lvl);
 return 0;
 }
 
@@ -9417,49 +9428,55 @@ static int psr_cat_print_domain_cbm(uint32_t domid, 
uint32_t socketid,
 }
 
 for (i = 0; i < nr_domains; i++)
-psr_cat_print_one_domain_cbm(list[i].domid, socketid, cdp_enabled);
+psr_cat_print_one_domain_cbm(list[i].domid, socketid, cdp_enabled, 
lvl);
 libxl_dominfo_list_free(list, nr_domains);
 
 return 0;
 }
 
-static int psr_cat_print_socket(uint32_t domid, libxl_psr_cat_info *info)
+static int psr_cat_print_socket(uint32_t domid, libxl_psr_cat_info *info,
+unsigned int lvl)
 {
 int rc;
 uint32_t l3_cache_size;
 
-rc = libxl_psr_cmt_get_l3_cache_size(ctx, info->id, _cache_size);
-if (rc) {
-fprintf(stderr, "Failed to get l3 cache size for socket:%d\n",
-info->id);
-return -1;
+printf("%-16s: %u\n", "Socket ID", info->id);
+
+/* So 

[Xen-devel] [PATCH RESEND v5 18/24] x86: L2 CAT: implement get hw info flow.

[Yi Sun]

This patch implements get HW info flow for L2 CAT including L2 CAT callback
function.

Signed-off-by: Yi Sun 
---
v5:
- rename 'dat[]' to 'data[]'
- remove type check in callback function.
---
 xen/arch/x86/psr.c  | 16 
 xen/arch/x86/sysctl.c   | 15 +++
 xen/include/asm-x86/psr.h   |  1 +
 xen/include/public/sysctl.h |  6 ++
 4 files changed, 38 insertions(+)

diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index 5320ae6..b630c48 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -268,6 +268,9 @@ static enum psr_feat_type psr_cbm_type_to_feat_type(enum 
cbm_type type)
 case PSR_CBM_TYPE_L3_CODE:
 feat_type = PSR_SOCKET_L3_CDP;
 break;
+case PSR_CBM_TYPE_L2:
+feat_type = PSR_SOCKET_L2_CAT;
+break;
 default:
 feat_type = 0x;
 break;
@@ -715,8 +718,21 @@ static unsigned int l2_cat_get_cos_max(const struct 
feat_node *feat)
 return feat->info.l2_cat_info.cos_max;
 }
 
+static bool l2_cat_get_feat_info(const struct feat_node *feat,
+ uint32_t data[], uint32_t array_len)
+{
+if ( !data || 2 > array_len )
+return false;
+
+data[CBM_LEN] = feat->info.l2_cat_info.cbm_len;
+data[COS_MAX] = feat->info.l2_cat_info.cos_max;
+
+return true;
+}
+
 struct feat_ops l2_cat_ops = {
 .get_cos_max = l2_cat_get_cos_max,
+.get_feat_info = l2_cat_get_feat_info,
 };
 
 static void __init parse_psr_bool(char *s, char *value, char *feature,
diff --git a/xen/arch/x86/sysctl.c b/xen/arch/x86/sysctl.c
index a4c8cfe..ae3600a 100644
--- a/xen/arch/x86/sysctl.c
+++ b/xen/arch/x86/sysctl.c
@@ -207,6 +207,21 @@ long arch_do_sysctl(
 ret = -EFAULT;
 break;
 }
+case XEN_SYSCTL_PSR_CAT_get_l2_info:
+{
+uint32_t dat[2];
+ret = psr_get_info(sysctl->u.psr_cat_op.target,
+   PSR_CBM_TYPE_L2, dat, 2);
+if ( ret )
+break;
+
+sysctl->u.psr_cat_op.u.l2_info.cbm_len = dat[CBM_LEN];
+sysctl->u.psr_cat_op.u.l2_info.cos_max = dat[COS_MAX];
+
+if ( !ret && __copy_field_to_guest(u_sysctl, sysctl, u.psr_cat_op) 
)
+ret = -EFAULT;
+break;
+}
 default:
 ret = -EOPNOTSUPP;
 break;
diff --git a/xen/include/asm-x86/psr.h b/xen/include/asm-x86/psr.h
index d2c7a13..31aa332 100644
--- a/xen/include/asm-x86/psr.h
+++ b/xen/include/asm-x86/psr.h
@@ -56,6 +56,7 @@ enum cbm_type {
 PSR_CBM_TYPE_L3,
 PSR_CBM_TYPE_L3_CODE,
 PSR_CBM_TYPE_L3_DATA,
+PSR_CBM_TYPE_L2,
 };
 
 extern struct psr_cmt *psr_cmt;
diff --git a/xen/include/public/sysctl.h b/xen/include/public/sysctl.h
index 00f5e77..cbf5372 100644
--- a/xen/include/public/sysctl.h
+++ b/xen/include/public/sysctl.h
@@ -744,6 +744,7 @@ typedef struct xen_sysctl_pcitopoinfo 
xen_sysctl_pcitopoinfo_t;
 DEFINE_XEN_GUEST_HANDLE(xen_sysctl_pcitopoinfo_t);
 
 #define XEN_SYSCTL_PSR_CAT_get_l3_info   0
+#define XEN_SYSCTL_PSR_CAT_get_l2_info   1
 struct xen_sysctl_psr_cat_op {
 uint32_t cmd;   /* IN: XEN_SYSCTL_PSR_CAT_* */
 uint32_t target;/* IN */
@@ -754,6 +755,11 @@ struct xen_sysctl_psr_cat_op {
 #define XEN_SYSCTL_PSR_CAT_L3_CDP   (1u << 0)
 uint32_t flags; /* OUT: CAT flags */
 } l3_info;
+
+struct {
+uint32_t cbm_len;   /* OUT: CBM length */
+uint32_t cos_max;   /* OUT: Maximum COS */
+} l2_info;
 } u;
 };
 typedef struct xen_sysctl_psr_cat_op xen_sysctl_psr_cat_op_t;
-- 
1.9.1


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[Xen-devel] [PATCH RESEND v5 16/24] x86: refactor psr: implement set value callback functions for CDP.

[Yi Sun]

This patch implements L3 CDP set value related callback functions.

With this patch, 'psr-cat-cbm-set' command can work for L3 CDP.

Signed-off-by: Yi Sun 
---
v5:
- remove type check in callback function.
- modify return value of callback functions because we do not need them
  to return number of entries the feature uses. In caller, we call
  'get_cos_num' to get the number of entries the feature uses.
- remove 'l3_cdp_get_cos_max_from_type'.
- rename 'l3_cdp_exceeds_cos_max' to 'l3_cdp_fits_cos_max'.
---
 xen/arch/x86/psr.c | 118 +
 1 file changed, 118 insertions(+)

diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index dc062ff..596e5b1 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -548,10 +548,128 @@ static bool l3_cdp_get_val(const struct feat_node *feat, 
unsigned int cos,
 return true;
 }
 
+static unsigned int l3_cdp_get_cos_num(const struct feat_node *feat)
+{
+return 2;
+}
+
+static int l3_cdp_get_old_val(uint64_t val[],
+  const struct feat_node *feat,
+  unsigned int old_cos)
+{
+if ( old_cos > feat->info.l3_cdp_info.cos_max )
+/* Use default value. */
+old_cos = 0;
+
+/* Data */
+val[0] = get_cdp_data(feat, old_cos);
+/* Code */
+val[1] = get_cdp_code(feat, old_cos);
+
+return 0;
+}
+
+static int l3_cdp_set_new_val(uint64_t val[],
+  const struct feat_node *feat,
+  enum cbm_type type,
+  uint64_t m)
+{
+if ( !psr_check_cbm(feat->info.l3_cdp_info.cbm_len, m) )
+return -EINVAL;
+
+if ( type == PSR_CBM_TYPE_L3_DATA )
+val[0] = m;
+else
+val[1] = m;
+
+return 0;
+}
+
+static int l3_cdp_compare_val(const uint64_t val[],
+  const struct feat_node *feat,
+  unsigned int cos, bool *found)
+{
+uint64_t l3_def_cbm;
+
+l3_def_cbm = (1ull << feat->info.l3_cdp_info.cbm_len) - 1;
+
+/*
+ * Different features' cos_max are different. If cos id of the feature
+ * being set exceeds other feature's cos_max, the val of other feature
+ * must be default value. HW supports such case.
+ */
+if ( cos > feat->info.l3_cdp_info.cos_max )
+{
+if ( val[0] != l3_def_cbm ||
+ val[1] != l3_def_cbm )
+{
+*found = false;
+return -ENOENT;
+}
+*found = true;
+}
+else
+*found = (val[0] == get_cdp_data(feat, cos) &&
+  val[1] == get_cdp_code(feat, cos));
+
+return 0;
+}
+
+static bool l3_cdp_fits_cos_max(const uint64_t val[],
+const struct feat_node *feat,
+unsigned int cos)
+{
+uint64_t l3_def_cbm;
+
+l3_def_cbm = (1ull << feat->info.l3_cdp_info.cbm_len) - 1;
+
+if ( cos > feat->info.l3_cdp_info.cos_max &&
+ (val[0] != l3_def_cbm || val[1] != l3_def_cbm) )
+/*
+ * Exceed cos_max and value to set is not default,
+ * return error.
+ */
+return false;
+
+return true;
+}
+
+static int l3_cdp_write_msr(unsigned int cos, const uint64_t val[],
+struct feat_node *feat)
+{
+/*
+ * If input cos is more than the cos_max of the feature, we should
+ * not set the value.
+ */
+if ( cos > feat->info.l3_cdp_info.cos_max )
+return -EINVAL;
+
+/* Data */
+if ( get_cdp_data(feat, cos) != val[0] )
+{
+get_cdp_data(feat, cos) = val[0];
+wrmsrl(MSR_IA32_PSR_L3_MASK_DATA(cos), val[0]);
+}
+/* Code */
+if ( get_cdp_code(feat, cos) != val[1] )
+{
+get_cdp_code(feat, cos) = val[1];
+wrmsrl(MSR_IA32_PSR_L3_MASK_CODE(cos), val[1]);
+}
+
+return 0;
+}
+
 struct feat_ops l3_cdp_ops = {
 .get_cos_max = l3_cdp_get_cos_max,
 .get_feat_info = l3_cdp_get_feat_info,
 .get_val = l3_cdp_get_val,
+.get_cos_num = l3_cdp_get_cos_num,
+.get_old_val = l3_cdp_get_old_val,
+.set_new_val = l3_cdp_set_new_val,
+.compare_val = l3_cdp_compare_val,
+.fits_cos_max = l3_cdp_fits_cos_max,
+.write_msr = l3_cdp_write_msr,
 };
 
 static void __init parse_psr_bool(char *s, char *value, char *feature,
-- 
1.9.1


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[Xen-devel] [PATCH RESEND v5 19/24] x86: L2 CAT: implement get value flow.

[Yi Sun]

This patch implements L2 CAT get value callback function and
interface in domctl.

Signed-off-by: Yi Sun 
---
v5:
- remove type check in callback function.
---
 xen/arch/x86/domctl.c   |  7 +++
 xen/arch/x86/psr.c  | 12 
 xen/include/public/domctl.h |  1 +
 3 files changed, 20 insertions(+)

diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c
index db56500..af6153d 100644
--- a/xen/arch/x86/domctl.c
+++ b/xen/arch/x86/domctl.c
@@ -1403,6 +1403,13 @@ long arch_do_domctl(
 copyback = 1;
 break;
 
+case XEN_DOMCTL_PSR_CAT_OP_GET_L2_CBM:
+ret = psr_get_val(d, domctl->u.psr_cat_op.target,
+  >u.psr_cat_op.data,
+  PSR_CBM_TYPE_L2);
+copyback = 1;
+break;
+
 default:
 ret = -EOPNOTSUPP;
 break;
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index b630c48..1fad540 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -730,9 +730,21 @@ static bool l2_cat_get_feat_info(const struct feat_node 
*feat,
 return true;
 }
 
+static bool l2_cat_get_val(const struct feat_node *feat, unsigned int cos,
+  enum cbm_type type, uint64_t *val)
+{
+if ( cos > feat->info.l2_cat_info.cos_max )
+cos = 0;
+
+*val = feat->cos_reg_val[cos];
+
+return true;
+}
+
 struct feat_ops l2_cat_ops = {
 .get_cos_max = l2_cat_get_cos_max,
 .get_feat_info = l2_cat_get_feat_info,
+.get_val = l2_cat_get_val,
 };
 
 static void __init parse_psr_bool(char *s, char *value, char *feature,
diff --git a/xen/include/public/domctl.h b/xen/include/public/domctl.h
index 85cbb7c..8c183ba 100644
--- a/xen/include/public/domctl.h
+++ b/xen/include/public/domctl.h
@@ -1138,6 +1138,7 @@ struct xen_domctl_psr_cat_op {
 #define XEN_DOMCTL_PSR_CAT_OP_SET_L3_DATA3
 #define XEN_DOMCTL_PSR_CAT_OP_GET_L3_CODE4
 #define XEN_DOMCTL_PSR_CAT_OP_GET_L3_DATA5
+#define XEN_DOMCTL_PSR_CAT_OP_GET_L2_CBM 7
 uint32_t cmd;   /* IN: XEN_DOMCTL_PSR_CAT_OP_* */
 uint32_t target;/* IN */
 uint64_t data;  /* IN/OUT */
-- 
1.9.1


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[Xen-devel] [PATCH RESEND v5 15/24] x86: refactor psr: implement get value flow for CDP.

[Yi Sun]

This patch implements L3 CDP get value callback function.

With this patch, 'psr-cat-show' can work for L3 CDP.

Signed-off-by: Yi Sun 
---
v5:
- remove type check in callback function.
---
 xen/arch/x86/psr.c | 16 
 1 file changed, 16 insertions(+)

diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index b856761..dc062ff 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -533,9 +533,25 @@ static bool l3_cdp_get_feat_info(const struct feat_node 
*feat,
 return true;
 }
 
+static bool l3_cdp_get_val(const struct feat_node *feat, unsigned int cos,
+   enum cbm_type type, uint64_t *val)
+{
+if ( cos > feat->info.l3_cdp_info.cos_max )
+/* Use default value. */
+cos = 0;
+
+if ( type == PSR_CBM_TYPE_L3_DATA )
+*val = get_cdp_data(feat, cos);
+else
+*val = get_cdp_code(feat, cos);
+
+return true;
+}
+
 struct feat_ops l3_cdp_ops = {
 .get_cos_max = l3_cdp_get_cos_max,
 .get_feat_info = l3_cdp_get_feat_info,
+.get_val = l3_cdp_get_val,
 };
 
 static void __init parse_psr_bool(char *s, char *value, char *feature,
-- 
1.9.1


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[Xen-devel] [PATCH RESEND v5 24/24] docs: add L2 CAT description in docs.

[Yi Sun]

This patch adds L2 CAT description in related documents.

Signed-off-by: He Chen 
Signed-off-by: Yi Sun 
---
 docs/man/xl.pod.1.in  | 25 ++---
 docs/misc/xl-psr.markdown | 10 --
 2 files changed, 30 insertions(+), 5 deletions(-)

diff --git a/docs/man/xl.pod.1.in b/docs/man/xl.pod.1.in
index 8e2aa5b..2c41ea7 100644
--- a/docs/man/xl.pod.1.in
+++ b/docs/man/xl.pod.1.in
@@ -1701,6 +1701,9 @@ occupancy monitoring share the same set of underlying 
monitoring service. Once
 a domain is attached to the monitoring service, monitoring data can be shown
 for any of these monitoring types.
 
+There is no cache monitoring and memory bandwidth monitoring on L2 cache so
+far.
+
 =over 4
 
 =item B [I]
@@ -1725,7 +1728,7 @@ monitor types are:
 
 Intel Broadwell and later server platforms offer capabilities to configure and
 make use of the Cache Allocation Technology (CAT) mechanisms, which enable more
-cache resources (i.e. L3 cache) to be made available for high priority
+cache resources (i.e. L3/L2 cache) to be made available for high priority
 applications. In the Xen implementation, CAT is used to control cache 
allocation
 on VM basis. To enforce cache on a specific domain, just set capacity bitmasks
 (CBM) for the domain.
@@ -1735,7 +1738,7 @@ Intel Broadwell and later server platforms also offer 
Code/Data Prioritization
 applications. CDP is used on a per VM basis in the Xen implementation. To
 specify code or data CBM for the domain, CDP feature must be enabled and CBM
 type options need to be specified when setting CBM, and the type options (code
-and data) are mutually exclusive.
+and data) are mutually exclusive. There is no CDP support on L2 so far.
 
 =over 4
 
@@ -1752,6 +1755,11 @@ B
 
 Specify the socket to process, otherwise all sockets are processed.
 
+=item B<-l LEVEL>, B<--level=LEVEL>
+
+Specify the cache level to process, otherwise the last level cache (L3) is
+processed.
+
 =item B<-c>, B<--code>
 
 Set code CBM when CDP is enabled.
@@ -1762,10 +1770,21 @@ Set data CBM when CDP is enabled.
 
 =back
 
-=item B [I]
+=item B [I] [I]
 
 Show CAT settings for a certain domain or all domains.
 
+B
+
+=over 4
+
+=item B<-l LEVEL>, B<--level=LEVEL>
+
+Specify the cache level to process, otherwise the last level cache (L3) is
+processed.
+
+=back
+
 =back
 
 =head1 IGNORED FOR COMPATIBILITY WITH XM
diff --git a/docs/misc/xl-psr.markdown b/docs/misc/xl-psr.markdown
index c3c1e8e..bd2b6bd 100644
--- a/docs/misc/xl-psr.markdown
+++ b/docs/misc/xl-psr.markdown
@@ -70,7 +70,7 @@ total-mem-bandwidth instead of cache-occupancy). E.g. after a 
`xl psr-cmt-attach
 
 Cache Allocation Technology (CAT) is a new feature available on Intel
 Broadwell and later server platforms that allows an OS or Hypervisor/VMM to
-partition cache allocation (i.e. L3 cache) based on application priority or
+partition cache allocation (i.e. L3/L2 cache) based on application priority or
 Class of Service (COS). Each COS is configured using capacity bitmasks (CBM)
 which represent cache capacity and indicate the degree of overlap and
 isolation between classes. System cache resource is divided into numbers of
@@ -119,13 +119,19 @@ A cbm is valid only when:
 In a multi-socket system, the same cbm will be set on each socket by default.
 Per socket cbm can be specified with the `--socket SOCKET` option.
 
+In different systems, the different cache level is supported, e.g. L3 cache or
+L2 cache. Per cache level cbm can be specified with the `--level LEVEL` option.
+
 Setting the CBM may not be successful if insufficient COS is available. In
 such case unused COS(es) may be freed by setting CBM of all related domains to
 its default value(all-ones).
 
 Per domain CBM settings can be shown by:
 
-`xl psr-cat-show`
+`xl psr-cat-show [OPTIONS] `
+
+In different systems, the different cache level is supported, e.g. L3 cache or
+L2 cache. Per cache level cbm can be specified with the `--level LEVEL` option.
 
 ## Code and Data Prioritization (CDP)
 
-- 
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[Xen-devel] [PATCH RESEND v5 21/24] tools: L2 CAT: support get HW info for L2 CAT.

[Yi Sun]

This patch implements xl/xc changes to support get HW info
for L2 CAT.

'xl psr-hwinfo' is updated to show both L3 CAT and L2 CAT
info.

Example(on machine which only supports L2 CAT):
Cache Monitoring Technology (CMT):
Enabled : 0
Cache Allocation Technology (CAT): L2
Socket ID   : 0
Maximum COS : 3
CBM length  : 8
Default CBM : 0xff

Signed-off-by: He Chen 
Signed-off-by: Yi Sun 
---
v5:
- modify commit message to remove error log.
- replace unnecessary 'return' to 'break'.
- restore 'libxl_psr_cat_get_l3_info' to keep interface backward compatible
  but change codes in it to call new function to get hw info.
- add 'L2_CBM' into 'psr_cbm_type' because it is interface change which
  should be in same patch with new 'LIBXL_HAVE_' macro.
- addjust logs sentence to make unnecessary error logs not show.
---
 tools/libxc/include/xenctrl.h |  6 ++---
 tools/libxc/xc_psr.c  | 40 +++--
 tools/libxl/libxl.h   |  9 
 tools/libxl/libxl_psr.c   | 19 +++-
 tools/libxl/libxl_types.idl   |  1 +
 tools/libxl/xl_cmdimpl.c  | 52 +--
 6 files changed, 95 insertions(+), 32 deletions(-)

diff --git a/tools/libxc/include/xenctrl.h b/tools/libxc/include/xenctrl.h
index 4ab0f57..7ea0c92 100644
--- a/tools/libxc/include/xenctrl.h
+++ b/tools/libxc/include/xenctrl.h
@@ -2626,9 +2626,9 @@ int xc_psr_cat_set_domain_data(xc_interface *xch, 
uint32_t domid,
 int xc_psr_cat_get_domain_data(xc_interface *xch, uint32_t domid,
xc_psr_cat_type type, uint32_t target,
uint64_t *data);
-int xc_psr_cat_get_l3_info(xc_interface *xch, uint32_t socket,
-   uint32_t *cos_max, uint32_t *cbm_len,
-   bool *cdp_enabled);
+int xc_psr_cat_get_info(xc_interface *xch, uint32_t socket, unsigned int lvl,
+uint32_t *cos_max, uint32_t *cbm_len,
+bool *cdp_enabled);
 
 int xc_get_cpu_levelling_caps(xc_interface *xch, uint32_t *caps);
 int xc_get_cpu_featureset(xc_interface *xch, uint32_t index,
diff --git a/tools/libxc/xc_psr.c b/tools/libxc/xc_psr.c
index 43b3286..6c61aa5 100644
--- a/tools/libxc/xc_psr.c
+++ b/tools/libxc/xc_psr.c
@@ -317,24 +317,40 @@ int xc_psr_cat_get_domain_data(xc_interface *xch, 
uint32_t domid,
 return rc;
 }
 
-int xc_psr_cat_get_l3_info(xc_interface *xch, uint32_t socket,
-   uint32_t *cos_max, uint32_t *cbm_len,
-   bool *cdp_enabled)
+int xc_psr_cat_get_info(xc_interface *xch, uint32_t socket, unsigned int lvl,
+uint32_t *cos_max, uint32_t *cbm_len, bool 
*cdp_enabled)
 {
-int rc;
+int rc = -1;
 DECLARE_SYSCTL;
 
 sysctl.cmd = XEN_SYSCTL_psr_cat_op;
-sysctl.u.psr_cat_op.cmd = XEN_SYSCTL_PSR_CAT_get_l3_info;
 sysctl.u.psr_cat_op.target = socket;
 
-rc = xc_sysctl(xch, );
-if ( !rc )
-{
-*cos_max = sysctl.u.psr_cat_op.u.l3_info.cos_max;
-*cbm_len = sysctl.u.psr_cat_op.u.l3_info.cbm_len;
-*cdp_enabled = sysctl.u.psr_cat_op.u.l3_info.flags &
-   XEN_SYSCTL_PSR_CAT_L3_CDP;
+switch ( lvl ) {
+case 2:
+sysctl.u.psr_cat_op.cmd = XEN_SYSCTL_PSR_CAT_get_l2_info;
+rc = xc_sysctl(xch, );
+if ( !rc )
+{
+*cos_max = sysctl.u.psr_cat_op.u.l2_info.cos_max;
+*cbm_len = sysctl.u.psr_cat_op.u.l2_info.cbm_len;
+*cdp_enabled = false;
+}
+break;
+case 3:
+sysctl.u.psr_cat_op.cmd = XEN_SYSCTL_PSR_CAT_get_l3_info;
+rc = xc_sysctl(xch, );
+if ( !rc )
+{
+*cos_max = sysctl.u.psr_cat_op.u.l3_info.cos_max;
+*cbm_len = sysctl.u.psr_cat_op.u.l3_info.cbm_len;
+*cdp_enabled = sysctl.u.psr_cat_op.u.l3_info.flags &
+   XEN_SYSCTL_PSR_CAT_L3_CDP;
+}
+break;
+default:
+errno = EOPNOTSUPP;
+break;
 }
 
 return rc;
diff --git a/tools/libxl/libxl.h b/tools/libxl/libxl.h
index 3924464..c75a928 100644
--- a/tools/libxl/libxl.h
+++ b/tools/libxl/libxl.h
@@ -904,6 +904,13 @@ void libxl_mac_copy(libxl_ctx *ctx, libxl_mac *dst, const 
libxl_mac *src);
  * If this is defined, the Code and Data Prioritization feature is supported.
  */
 #define LIBXL_HAVE_PSR_CDP 1
+
+/*
+ * LIBXL_HAVE_PSR_L2_CAT
+ *
+ * If this is defined, the L2 Cache Allocation Technology feature is supported.
+ */
+#define LIBXL_HAVE_PSR_L2_CAT 1
 #endif
 
 /*
@@ -2166,6 +2173,8 @@ int libxl_psr_cat_get_cbm(libxl_ctx *ctx, uint32_t domid,
  * On success, the function returns an array of elements in 'info',
  * and the length in 'nr'.
  */
+int libxl_psr_cat_get_info(libxl_ctx *ctx, libxl_psr_cat_info **info,
+   int *nr, unsigned 

[Xen-devel] [PATCH RESEND v5 13/24] x86: refactor psr: implement CPU init and free flow for CDP.

[Yi Sun]

This patch implements the CPU init and free flow for CDP including L3 CDP
initialization callback function.

Signed-off-by: Yi Sun 
---
v5:
- remove 'feat_l3_cdp' free in 'free_feature'.
- Encapsulate cpuid registers into 'struct cpuid_leaf_regs'.
- Print socket info when 'opt_cpu_info' is true.
- rename 'l3_cdp_get_max_cos_max' to 'l3_cdp_get_cos_max'.
- rename 'dat[]' to 'data[]'
- move 'cpu_prepare_work' contents into 'psr_cpu_prepare'.
---
 xen/arch/x86/psr.c | 98 +++---
 1 file changed, 93 insertions(+), 5 deletions(-)

diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index b8d3c82..a979128 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -93,6 +93,7 @@ struct psr_cat_hw_info {
 struct feat_hw_info {
 union {
 struct psr_cat_hw_info l3_cat_info;
+struct psr_cat_hw_info l3_cdp_info;
 };
 };
 
@@ -197,6 +198,21 @@ struct cpuid_leaf_regs {
 unsigned int ecx;
 unsigned int edx;
 };
+/*
+ * get_data - get DATA COS register value from input COS ID.
+ * @feat:the feature list entry.
+ * @cos: the COS ID.
+ */
+#define get_cdp_data(feat, cos)  \
+( feat->cos_reg_val[cos * 2] )
+
+/*
+ * get_cdp_code - get CODE COS register value from input COS ID.
+ * @feat:the feature list entry.
+ * @cos: the COS ID.
+ */
+#define get_cdp_code(feat, cos)  \
+( feat->cos_reg_val[cos * 2 + 1] )
 
 struct psr_assoc {
 uint64_t val;
@@ -219,6 +235,7 @@ static DEFINE_PER_CPU(struct psr_assoc, psr_assoc);
  * inserted into feature list in cpu_init_work().
  */
 static struct feat_node *feat_l3_cat;
+static struct feat_node *feat_l3_cdp;
 
 /* Common functions. */
 static void free_feature(struct psr_socket_info *info)
@@ -448,6 +465,61 @@ static const struct feat_ops l3_cat_ops = {
 .write_msr = l3_cat_write_msr,
 };
 
+/* L3 CDP functions implementation. */
+static void l3_cdp_init_feature(struct cpuid_leaf_regs regs,
+struct feat_node *feat,
+struct psr_socket_info *info)
+{
+struct psr_cat_hw_info l3_cdp;
+unsigned int socket;
+uint64_t val;
+
+/* No valid value so do not enable feature. */
+if ( !regs.eax || !regs.edx )
+return;
+
+l3_cdp.cbm_len = (regs.eax & CAT_CBM_LEN_MASK) + 1;
+/* Cut half of cos_max when CDP is enabled. */
+l3_cdp.cos_max = min(opt_cos_max, regs.edx & CAT_COS_MAX_MASK) >> 1;
+
+/* cos=0 is reserved as default cbm(all ones). */
+get_cdp_code(feat, 0) =
+ (1ull << l3_cdp.cbm_len) - 1;
+get_cdp_data(feat, 0) =
+ (1ull << l3_cdp.cbm_len) - 1;
+
+/* We only write mask1 since mask0 is always all ones by default. */
+wrmsrl(MSR_IA32_PSR_L3_MASK(1), (1ull << l3_cdp.cbm_len) - 1);
+rdmsrl(MSR_IA32_PSR_L3_QOS_CFG, val);
+wrmsrl(MSR_IA32_PSR_L3_QOS_CFG, val | (1 << PSR_L3_QOS_CDP_ENABLE_BIT));
+
+feat->feature = PSR_SOCKET_L3_CDP;
+__set_bit(PSR_SOCKET_L3_CDP, >feat_mask);
+
+feat->info.l3_cdp_info = l3_cdp;
+
+info->nr_feat++;
+
+/* Add this feature into list. */
+list_add_tail(>list, >feat_list);
+
+socket = cpu_to_socket(smp_processor_id());
+if ( opt_cpu_info )
+printk(XENLOG_INFO
+   "L3 CDP: enabled on socket %u, cos_max:%u, cbm_len:%u\n",
+   socket, feat->info.l3_cdp_info.cos_max,
+   feat->info.l3_cdp_info.cbm_len);
+}
+
+static unsigned int l3_cdp_get_cos_max(const struct feat_node *feat)
+{
+return feat->info.l3_cdp_info.cos_max;
+}
+
+struct feat_ops l3_cdp_ops = {
+.get_cos_max = l3_cdp_get_cos_max,
+};
+
 static void __init parse_psr_bool(char *s, char *value, char *feature,
   unsigned int mask)
 {
@@ -1207,11 +1279,19 @@ static void cpu_init_work(void)
 cpuid_count(PSR_CPUID_LEVEL_CAT, 1,
 , , , );
 
-feat = feat_l3_cat;
-feat_l3_cat = NULL;
-feat->ops = l3_cat_ops;
-
-l3_cat_init_feature(regs, feat, info);
+if ( (regs.ecx & PSR_CAT_CDP_CAPABILITY) && (opt_psr & PSR_CDP) &&
+ !test_bit(PSR_SOCKET_L3_CDP, >feat_mask) )
+{
+feat = feat_l3_cdp;
+feat_l3_cdp = NULL;
+feat->ops = l3_cdp_ops;
+l3_cdp_init_feature(regs, feat, info);
+} else {
+feat = feat_l3_cat;
+feat_l3_cat = NULL;
+feat->ops = l3_cat_ops;
+l3_cat_init_feature(regs, feat, info);
+}
 }
 }
 
@@ -1263,6 +1343,14 @@ static int psr_cpu_prepare(unsigned int cpu)
  (feat_l3_cat = xzalloc(struct feat_node)) == NULL )
 return -ENOMEM;
 
+if ( feat_l3_cdp == NULL &&
+ (feat_l3_cdp = xzalloc(struct feat_node)) == NULL )
+{
+xfree(feat_l3_cat);
+feat_l3_cat = NULL;
+return -ENOMEM;
+}
+
  

[Xen-devel] [PATCH RESEND v5 02/24] x86: refactor psr: remove L3 CAT/CDP codes.

[Yi Sun]

The current cache allocation codes in psr.c do not consider
future features addition and are not friendly to extend.

To make psr.c be more flexible to add new features and fulfill
the program principle, open for extension but closed for
modification, we have to refactor the psr.c:
1. Analyze cache allocation features and abstract general data
   structures.
2. Analyze the init and all other functions flow, abstract all
   steps that different features may have different implementations.
   Make these steps be callback functions and register feature
   specific fuctions. Then, the main processes will not be changed
   when introducing a new feature.

Because the quantity of refactor codes is big and the logics are
changed a lot, it will cause reviewers confused if just change
old codes. Reviewers have to understand both old codes and new
implementations. After review iterations from V1 to V3, Jan has
proposed to remove all old cache allocation codes firstly, then
implement new codes step by step. This will help to make codes
be more easily reviewable.

There is no construction without destruction. So, this patch
removes all current L3 CAT/CDP codes in psr.c. The following
patches will introduce the new mechanism.

Signed-off-by: Yi Sun 
Acked-by: Jan Beulich 
---
 xen/arch/x86/psr.c | 470 +
 1 file changed, 5 insertions(+), 465 deletions(-)

diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index 0b5073c..96a8589 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -23,24 +23,6 @@
 #define PSR_CAT(1<<1)
 #define PSR_CDP(1<<2)
 
-struct psr_cat_cbm {
-union {
-uint64_t cbm;
-struct {
-uint64_t code;
-uint64_t data;
-};
-};
-unsigned int ref;
-};
-
-struct psr_cat_socket_info {
-unsigned int cbm_len;
-unsigned int cos_max;
-struct psr_cat_cbm *cos_to_cbm;
-spinlock_t cbm_lock;
-};
-
 struct psr_assoc {
 uint64_t val;
 uint64_t cos_mask;
@@ -48,26 +30,11 @@ struct psr_assoc {
 
 struct psr_cmt *__read_mostly psr_cmt;
 
-static unsigned long *__read_mostly cat_socket_enable;
-static struct psr_cat_socket_info *__read_mostly cat_socket_info;
-static unsigned long *__read_mostly cdp_socket_enable;
-
 static unsigned int opt_psr;
 static unsigned int __initdata opt_rmid_max = 255;
-static unsigned int __read_mostly opt_cos_max = 255;
 static uint64_t rmid_mask;
 static DEFINE_PER_CPU(struct psr_assoc, psr_assoc);
 
-static struct psr_cat_cbm *temp_cos_to_cbm;
-
-static unsigned int get_socket_cpu(unsigned int socket)
-{
-if ( likely(socket < nr_sockets) )
-return cpumask_any(socket_cpumask[socket]);
-
-return nr_cpu_ids;
-}
-
 static void __init parse_psr_bool(char *s, char *value, char *feature,
   unsigned int mask)
 {
@@ -107,9 +74,6 @@ static void __init parse_psr_param(char *s)
 if ( val_str && !strcmp(s, "rmid_max") )
 opt_rmid_max = simple_strtoul(val_str, NULL, 0);
 
-if ( val_str && !strcmp(s, "cos_max") )
-opt_cos_max = simple_strtoul(val_str, NULL, 0);
-
 s = ss + 1;
 } while ( ss );
 }
@@ -213,16 +177,7 @@ static inline void psr_assoc_init(void)
 {
 struct psr_assoc *psra = _cpu(psr_assoc);
 
-if ( cat_socket_info )
-{
-unsigned int socket = cpu_to_socket(smp_processor_id());
-
-if ( test_bit(socket, cat_socket_enable) )
-psra->cos_mask = ((1ull << get_count_order(
- cat_socket_info[socket].cos_max)) - 1) << 32;
-}
-
-if ( psr_cmt_enabled() || psra->cos_mask )
+if ( psr_cmt_enabled() )
 rdmsrl(MSR_IA32_PSR_ASSOC, psra->val);
 }
 
@@ -231,12 +186,6 @@ static inline void psr_assoc_rmid(uint64_t *reg, unsigned 
int rmid)
 *reg = (*reg & ~rmid_mask) | (rmid & rmid_mask);
 }
 
-static inline void psr_assoc_cos(uint64_t *reg, unsigned int cos,
- uint64_t cos_mask)
-{
-*reg = (*reg & ~cos_mask) | (((uint64_t)cos << 32) & cos_mask);
-}
-
 void psr_ctxt_switch_to(struct domain *d)
 {
 struct psr_assoc *psra = _cpu(psr_assoc);
@@ -245,459 +194,54 @@ void psr_ctxt_switch_to(struct domain *d)
 if ( psr_cmt_enabled() )
 psr_assoc_rmid(, d->arch.psr_rmid);
 
-if ( psra->cos_mask )
-psr_assoc_cos(, d->arch.psr_cos_ids ?
-  d->arch.psr_cos_ids[cpu_to_socket(smp_processor_id())] :
-  0, psra->cos_mask);
-
 if ( reg != psra->val )
 {
 wrmsrl(MSR_IA32_PSR_ASSOC, reg);
 psra->val = reg;
 }
 }
-static struct psr_cat_socket_info *get_cat_socket_info(unsigned int socket)
-{
-if ( !cat_socket_info )
-return ERR_PTR(-ENODEV);
-
-if ( socket >= nr_sockets )
-return ERR_PTR(-ENOTSOCK);
-
-if ( !test_bit(socket, cat_socket_enable) )
-return ERR_PTR(-ENOENT);
-
-return 

[Xen-devel] [PATCH RESEND v5 17/24] x86: L2 CAT: implement CPU init and free flow.

[Yi Sun]

This patch implements the CPU init and free flow for L2 CAT including
L2 CAT initialization callback function.

Signed-off-by: Yi Sun 
---
v5:
- remove 'feat_l2_cat' free in 'free_feature'.
- Encapsulate cpuid registers into 'struct cpuid_leaf_regs'.
- Print socket info when 'opt_cpu_info' is true.
- rename 'l2_cat_get_max_cos_max' to 'l2_cat_get_cos_max'.
- rename 'dat[]' to 'data[]'
- move 'cpu_prepare_work' contents into 'psr_cpu_prepare'.
---
 xen/arch/x86/psr.c| 72 +++
 xen/include/asm-x86/psr.h |  1 +
 2 files changed, 73 insertions(+)

diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index 596e5b1..5320ae6 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -94,6 +94,7 @@ struct feat_hw_info {
 union {
 struct psr_cat_hw_info l3_cat_info;
 struct psr_cat_hw_info l3_cdp_info;
+struct psr_cat_hw_info l2_cat_info;
 };
 };
 
@@ -236,6 +237,7 @@ static DEFINE_PER_CPU(struct psr_assoc, psr_assoc);
  */
 static struct feat_node *feat_l3_cat;
 static struct feat_node *feat_l3_cdp;
+static struct feat_node *feat_l2_cat;
 
 /* Common functions. */
 static void free_feature(struct psr_socket_info *info)
@@ -672,6 +674,51 @@ struct feat_ops l3_cdp_ops = {
 .write_msr = l3_cdp_write_msr,
 };
 
+/* L2 CAT callback functions implementation. */
+static void l2_cat_init_feature(struct cpuid_leaf_regs regs,
+struct feat_node *feat,
+struct psr_socket_info *info)
+{
+struct psr_cat_hw_info l2_cat;
+unsigned int socket;
+
+/* No valid values so do not enable the feature. */
+if ( !regs.eax || !regs.edx )
+return;
+
+l2_cat.cbm_len = (regs.eax & CAT_CBM_LEN_MASK) + 1;
+l2_cat.cos_max = min(opt_cos_max, regs.edx & CAT_COS_MAX_MASK);
+
+/* cos=0 is reserved as default cbm(all ones). */
+feat->cos_reg_val[0] = (1ull << l2_cat.cbm_len) - 1;
+
+feat->feature = PSR_SOCKET_L2_CAT;
+__set_bit(PSR_SOCKET_L2_CAT, >feat_mask);
+
+feat->info.l2_cat_info = l2_cat;
+
+info->nr_feat++;
+
+/* Add this feature into list. */
+list_add_tail(>list, >feat_list);
+
+socket = cpu_to_socket(smp_processor_id());
+if ( opt_cpu_info )
+printk(XENLOG_INFO
+   "L2 CAT: enabled on socket %u, cos_max:%u, cbm_len:%u.\n",
+   socket, feat->info.l2_cat_info.cos_max,
+   feat->info.l2_cat_info.cbm_len);
+}
+
+static unsigned int l2_cat_get_cos_max(const struct feat_node *feat)
+{
+return feat->info.l2_cat_info.cos_max;
+}
+
+struct feat_ops l2_cat_ops = {
+.get_cos_max = l2_cat_get_cos_max,
+};
+
 static void __init parse_psr_bool(char *s, char *value, char *feature,
   unsigned int mask)
 {
@@ -1445,6 +1492,20 @@ static void cpu_init_work(void)
 l3_cat_init_feature(regs, feat, info);
 }
 }
+
+cpuid_count(PSR_CPUID_LEVEL_CAT, 0,
+, , , );
+if ( regs.ebx & PSR_RESOURCE_TYPE_L2 )
+{
+/* Initialize L2 CAT according to CPUID. */
+cpuid_count(PSR_CPUID_LEVEL_CAT, 2,
+, , , );
+
+feat = feat_l2_cat;
+feat_l2_cat = NULL;
+feat->ops = l2_cat_ops;
+l2_cat_init_feature(regs, feat, info);
+}
 }
 
 static void cpu_fini_work(unsigned int cpu)
@@ -1503,6 +1564,17 @@ static int psr_cpu_prepare(unsigned int cpu)
 return -ENOMEM;
 }
 
+if ( feat_l2_cat == NULL &&
+ (feat_l2_cat = xzalloc(struct feat_node)) == NULL )
+{
+xfree(feat_l3_cat);
+feat_l3_cat = NULL;
+
+xfree(feat_l3_cdp);
+feat_l3_cdp = NULL;
+return -ENOMEM;
+}
+
 return 0;
 }
 
diff --git a/xen/include/asm-x86/psr.h b/xen/include/asm-x86/psr.h
index 97214fe..d2c7a13 100644
--- a/xen/include/asm-x86/psr.h
+++ b/xen/include/asm-x86/psr.h
@@ -23,6 +23,7 @@
 
 /* Resource Type Enumeration */
 #define PSR_RESOURCE_TYPE_L30x2
+#define PSR_RESOURCE_TYPE_L20x4
 
 /* L3 Monitoring Features */
 #define PSR_CMT_L3_OCCUPANCY   0x1
-- 
1.9.1


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[Xen-devel] [PATCH RESEND v5 10/24] x86: refactor psr: set value: implement cos finding flow.

[Yi Sun]

Continue with patch:
'x86: refactor psr: set value: assemble features value array'

We can try to find if there is a COS ID on which all features' COS registers
values are same as the array assembled before.

Signed-off-by: Yi Sun 
---
v5:
- modify commit message to provide exact patch name to continue from.
- remove 'get_cos_max_from_type' because it can be replaced by
  'get_cos_max'.
- move type check out from callback functions to caller.
- modify variables names to make them better, e.g. 'feat_tmp' to 'feat'.
- modify comments according to changes of codes.
---
 xen/arch/x86/psr.c | 93 ++
 1 file changed, 93 insertions(+)

diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index 7c6f2bf..8832e08 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -141,6 +141,19 @@ struct feat_ops {
const struct feat_node *feat,
enum cbm_type type,
uint64_t m);
+/*
+ * compare_val is used in set value process to compare if the
+ * input value array can match all the features' COS registers values
+ * according to input cos id.
+ *
+ * The return value is the amount of entries to skip in the value array
+ * or error.
+ * 1 - one entry in value array.
+ * 2 - two entries in value array, e.g. CDP uses two entries.
+ * negative - error.
+ */
+int (*compare_val)(const uint64_t val[], const struct feat_node *feat,
+unsigned int cos, bool *found);
 };
 
 /*
@@ -347,6 +360,34 @@ static int l3_cat_set_new_val(uint64_t val[],
 return 0;
 }
 
+static int l3_cat_compare_val(const uint64_t val[],
+  const struct feat_node *feat,
+  unsigned int cos, bool *found)
+{
+uint64_t l3_def_cbm;
+
+l3_def_cbm = (1ull << feat->info.l3_cat_info.cbm_len) - 1;
+
+/*
+ * Different features' cos_max are different. If cos id of the feature
+ * being set exceeds other feature's cos_max, the val of other feature
+ * must be default value. HW supports such case.
+ */
+if ( cos > feat->info.l3_cat_info.cos_max )
+{
+if ( val[0] != l3_def_cbm )
+{
+*found = false;
+return -ENOENT;
+}
+*found = true;
+}
+else
+*found = (val[0] == feat->cos_reg_val[cos]);
+
+return 0;
+}
+
 static const struct feat_ops l3_cat_ops = {
 .get_cos_max = l3_cat_get_cos_max,
 .get_feat_info = l3_cat_get_feat_info,
@@ -354,6 +395,7 @@ static const struct feat_ops l3_cat_ops = {
 .get_cos_num = l3_cat_get_cos_num,
 .get_old_val = l3_cat_get_old_val,
 .set_new_val = l3_cat_set_new_val,
+.compare_val = l3_cat_compare_val,
 };
 
 static void __init parse_psr_bool(char *s, char *value, char *feature,
@@ -706,6 +748,57 @@ static int find_cos(const uint64_t *val, uint32_t 
array_len,
 enum psr_feat_type feat_type,
 const struct psr_socket_info *info)
 {
+unsigned int cos;
+const unsigned int *ref = info->cos_ref;
+const struct feat_node *feat;
+const uint64_t *val_tmp = val;
+int ret;
+bool found = false;
+unsigned int cos_max = 0;
+
+/* cos_max is the one of the feature which is being set. */
+list_for_each_entry(feat, >feat_list, list)
+{
+if ( feat->feature != feat_type )
+continue;
+
+cos_max = feat->ops.get_cos_max(feat);
+if ( cos_max > 0 )
+break;
+}
+
+for ( cos = 0; cos <= cos_max; cos++ )
+{
+if ( cos && !ref[cos] )
+continue;
+
+/* Not found, need find again from beginning. */
+val_tmp = val;
+list_for_each_entry(feat, >feat_list, list)
+{
+/*
+ * Compare value according to feature list order.
+ * We must follow this order because value array is assembled
+ * as this order in get_old_set_new().
+ */
+ret = feat->ops.compare_val(val_tmp, feat, cos, );
+if ( ret < 0 )
+return ret;
+
+/* If fail to match, go to next cos to compare. */
+if ( !found )
+break;
+
+val_tmp += feat->ops.get_cos_num(feat);
+if ( val_tmp - val > array_len )
+return -EINVAL;
+}
+
+/* For this COS ID all entries in the values array did match. Use it. 
*/
+if ( found )
+return cos;
+}
+
 return -ENOENT;
 }
 
-- 
1.9.1


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[Xen-devel] [PATCH RESEND v5 05/24] x86: refactor psr: implement Domain init/free and schedule flows.

[Yi Sun]

This patch implements the Domain init/free and schedule flows.

Signed-off-by: Yi Sun 
---
v5:
- define macro 'PSR_ASSOC_REG_POS' to replace integer 32.
- rename 'l3_cat_get_max_cos_max' to 'l3_cat_get_cos_max'.
- modify variables names to make them better, e.g. 'feat_tmp' to 'feat'.
---
 xen/arch/x86/psr.c | 62 +-
 1 file changed, 61 insertions(+), 1 deletion(-)

diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index e9dc07a..7f06235 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -50,6 +50,8 @@
  */
 #define MAX_COS_REG_CNT  128
 
+#define PSR_ASSOC_REG_POS 32
+
 /*
  * PSR features are managed per socket. Below structure defines the members
  * used to manage these features.
@@ -211,7 +213,13 @@ static void l3_cat_init_feature(struct cpuid_leaf_regs 
regs,
feat->info.l3_cat_info.cbm_len);
 }
 
+static unsigned int l3_cat_get_cos_max(const struct feat_node *feat)
+{
+return feat->info.l3_cat_info.cos_max;
+}
+
 static const struct feat_ops l3_cat_ops = {
+.get_cos_max = l3_cat_get_cos_max,
 };
 
 static void __init parse_psr_bool(char *s, char *value, char *feature,
@@ -355,11 +363,33 @@ void psr_free_rmid(struct domain *d)
 d->arch.psr_rmid = 0;
 }
 
+static inline unsigned int get_max_cos_max(const struct psr_socket_info *info)
+{
+const struct feat_node *feat;
+unsigned int cos_max = 0;
+
+list_for_each_entry(feat, >feat_list, list)
+cos_max = max(feat->ops.get_cos_max(feat), cos_max);
+
+return cos_max;
+}
+
 static inline void psr_assoc_init(void)
 {
 struct psr_assoc *psra = _cpu(psr_assoc);
 
-if ( psr_cmt_enabled() )
+if ( socket_info )
+{
+unsigned int socket = cpu_to_socket(smp_processor_id());
+const struct psr_socket_info *info = socket_info + socket;
+unsigned int cos_max = get_max_cos_max(info);
+
+if ( info->feat_mask )
+psra->cos_mask = ((1ull << get_count_order(cos_max)) - 1) <<
+  PSR_ASSOC_REG_POS;
+}
+
+if ( psr_cmt_enabled() || psra->cos_mask )
 rdmsrl(MSR_IA32_PSR_ASSOC, psra->val);
 }
 
@@ -368,6 +398,13 @@ static inline void psr_assoc_rmid(uint64_t *reg, unsigned 
int rmid)
 *reg = (*reg & ~rmid_mask) | (rmid & rmid_mask);
 }
 
+static inline void psr_assoc_cos(uint64_t *reg, unsigned int cos,
+ uint64_t cos_mask)
+{
+*reg = (*reg & ~cos_mask) |
+(((uint64_t)cos << PSR_ASSOC_REG_POS) & cos_mask);
+}
+
 void psr_ctxt_switch_to(struct domain *d)
 {
 struct psr_assoc *psra = _cpu(psr_assoc);
@@ -376,6 +413,11 @@ void psr_ctxt_switch_to(struct domain *d)
 if ( psr_cmt_enabled() )
 psr_assoc_rmid(, d->arch.psr_rmid);
 
+if ( psra->cos_mask )
+psr_assoc_cos(, d->arch.psr_cos_ids ?
+  d->arch.psr_cos_ids[cpu_to_socket(smp_processor_id())] :
+  0, psra->cos_mask);
+
 if ( reg != psra->val )
 {
 wrmsrl(MSR_IA32_PSR_ASSOC, reg);
@@ -401,14 +443,32 @@ int psr_set_l3_cbm(struct domain *d, unsigned int socket,
 return 0;
 }
 
+/* Called with domain lock held, no extra lock needed for 'psr_cos_ids' */
+static void psr_free_cos(struct domain *d)
+{
+if( !d->arch.psr_cos_ids )
+return;
+
+xfree(d->arch.psr_cos_ids);
+d->arch.psr_cos_ids = NULL;
+}
+
 int psr_domain_init(struct domain *d)
 {
+if ( socket_info )
+{
+d->arch.psr_cos_ids = xzalloc_array(unsigned int, nr_sockets);
+if ( !d->arch.psr_cos_ids )
+return -ENOMEM;
+}
+
 return 0;
 }
 
 void psr_domain_free(struct domain *d)
 {
 psr_free_rmid(d);
+psr_free_cos(d);
 }
 
 static void cpu_init_work(void)
-- 
1.9.1


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[Xen-devel] [PATCH RESEND v5 06/24] x86: refactor psr: implement get hw info flow.

[Yi Sun]

This patch implements get HW info flow including L3 CAT callback
function.

It also changes sysctl interface to make it more general.

With this patch, 'psr-hwinfo' can work for L3 CAT.

Signed-off-by: Yi Sun 
---
v5:
- add function 'psr_cbm_type_to_feat_type' to covert 'cbm_type' to
  'psr_feat_type'. This is part of codes to move type check out from
  callback functions.
- remove type check from feature callback functions.
- rename 'dat[]' to 'data[]'
- check if feature type match in caller of feature callback function.
---
 xen/arch/x86/psr.c| 73 +--
 xen/arch/x86/sysctl.c | 14 +
 xen/include/asm-x86/psr.h |  9 --
 3 files changed, 86 insertions(+), 10 deletions(-)

diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index 7f06235..319bfcc 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -109,6 +109,9 @@ struct feat_node;
 struct feat_ops {
 /* get_cos_max is used to get feature's cos_max. */
 unsigned int (*get_cos_max)(const struct feat_node *feat);
+/* get_feat_info is used to get feature HW info. */
+bool (*get_feat_info)(const struct feat_node *feat,
+  uint32_t data[], unsigned int array_len);
 };
 
 /*
@@ -177,6 +180,23 @@ static void free_feature(struct psr_socket_info *info)
 }
 }
 
+static enum psr_feat_type psr_cbm_type_to_feat_type(enum cbm_type type)
+{
+enum psr_feat_type feat_type;
+
+/* Judge if feature is enabled. */
+switch ( type ) {
+case PSR_CBM_TYPE_L3:
+feat_type = PSR_SOCKET_L3_CAT;
+break;
+default:
+feat_type = 0x;
+break;
+}
+
+return feat_type;
+}
+
 /* L3 CAT functions implementation. */
 static void l3_cat_init_feature(struct cpuid_leaf_regs regs,
 struct feat_node *feat,
@@ -218,8 +238,22 @@ static unsigned int l3_cat_get_cos_max(const struct 
feat_node *feat)
 return feat->info.l3_cat_info.cos_max;
 }
 
+static bool l3_cat_get_feat_info(const struct feat_node *feat,
+ uint32_t data[], unsigned int array_len)
+{
+if ( !data || 3 > array_len )
+return false;
+
+data[CBM_LEN] = feat->info.l3_cat_info.cbm_len;
+data[COS_MAX] = feat->info.l3_cat_info.cos_max;
+data[PSR_FLAG] = 0;
+
+return true;
+}
+
 static const struct feat_ops l3_cat_ops = {
 .get_cos_max = l3_cat_get_cos_max,
+.get_feat_info = l3_cat_get_feat_info,
 };
 
 static void __init parse_psr_bool(char *s, char *value, char *feature,
@@ -425,10 +459,43 @@ void psr_ctxt_switch_to(struct domain *d)
 }
 }
 
-int psr_get_cat_l3_info(unsigned int socket, uint32_t *cbm_len,
-uint32_t *cos_max, uint32_t *flags)
+static struct psr_socket_info *get_socket_info(unsigned int socket)
 {
-return 0;
+if ( !socket_info )
+return ERR_PTR(-ENODEV);
+
+if ( socket >= nr_sockets )
+return ERR_PTR(-ENOTSOCK);
+
+if ( !socket_info[socket].feat_mask )
+return ERR_PTR(-ENOENT);
+
+return socket_info + socket;
+}
+
+int psr_get_info(unsigned int socket, enum cbm_type type,
+ uint32_t data[], unsigned int array_len)
+{
+const struct psr_socket_info *info = get_socket_info(socket);
+const struct feat_node *feat;
+enum psr_feat_type feat_type;
+
+if ( IS_ERR(info) )
+return PTR_ERR(info);
+
+feat_type = psr_cbm_type_to_feat_type(type);
+list_for_each_entry(feat, >feat_list, list)
+{
+if ( feat->feature != feat_type )
+continue;
+
+if ( feat->ops.get_feat_info(feat, data, array_len) )
+return 0;
+else
+return -EINVAL;
+}
+
+return -ENOENT;
 }
 
 int psr_get_l3_cbm(struct domain *d, unsigned int socket,
diff --git a/xen/arch/x86/sysctl.c b/xen/arch/x86/sysctl.c
index 14e7dc7..d90db78 100644
--- a/xen/arch/x86/sysctl.c
+++ b/xen/arch/x86/sysctl.c
@@ -176,15 +176,19 @@ long arch_do_sysctl(
 switch ( sysctl->u.psr_cat_op.cmd )
 {
 case XEN_SYSCTL_PSR_CAT_get_l3_info:
-ret = psr_get_cat_l3_info(sysctl->u.psr_cat_op.target,
-  >u.psr_cat_op.u.l3_info.cbm_len,
-  >u.psr_cat_op.u.l3_info.cos_max,
-  >u.psr_cat_op.u.l3_info.flags);
+{
+uint32_t data[3];
+ret = psr_get_info(sysctl->u.psr_cat_op.target,
+   PSR_CBM_TYPE_L3, data, 3);
+
+sysctl->u.psr_cat_op.u.l3_info.cbm_len = data[CBM_LEN];
+sysctl->u.psr_cat_op.u.l3_info.cos_max = data[COS_MAX];
+sysctl->u.psr_cat_op.u.l3_info.flags   = data[PSR_FLAG];
 
 if ( !ret && __copy_field_to_guest(u_sysctl, sysctl, u.psr_cat_op) 
)
 ret = -EFAULT;
 break;
-
+}
 default:
 ret = 

[Xen-devel] [PATCH RESEND v5 03/24] x86: refactor psr: implement main data structures.

[Yi Sun]

To construct an extendible framework, we need analyze PSR features
and abstract the common things and feature specific things. Then,
encapsulate them into different data structures.

By analyzing PSR features, we can get below map.
+--+--+--+
  ->| Dom0 | Dom1 | ...  |
  | +--+--+--+
  ||
  |Dom ID  | cos_id of domain
  |V
  |
+-+
User ->| PSR
 |
 Socket ID |  +--+---+---+  
 |
   |  | Socket0 Info | Socket 1 Info |...|  
 |
   |  +--+---+---+  
 |
   ||   cos_id=0   cos_id=1 
 ... |
   ||  
+---+---+---+ |
   ||->Ref   : | ref 0 | ref 1 
| ...   | |
   ||  
+---+---+---+ |
   ||  
+---+---+---+ |
   ||->L3 CAT: | cos 0 | cos 1 
| ...   | |
   ||  
+---+---+---+ |
   ||  
+---+---+---+ |
   ||->L2 CAT: | cos 0 | cos 1 
| ...   | |
   ||  
+---+---+---+ |
   ||  
+---+---+---+---+---+ |
   ||->CDP   : | cos0 code | cos0 data | cos1 code | cos1 data 
| ...   | |
   |   
+---+---+---+---+---+ |
   
+-+

So, we need define a socket info data structure, 'struct
psr_socket_info' to manage information per socket. It contains a
reference count array according to COS ID and a feature list to
manage all features enabled. Every entry of the reference count
array is used to record how many domains are using the COS registers
according to the COS ID. For example, L3 CAT and L2 CAT are enabled,
Dom1 uses COS_ID=1 registers of both features to save CBM values, like
below.
+---+---+---+-+
| COS 0 | COS 1 | COS 2 | ... |
+---+---+---+-+
L3 CAT  | 0x7ff | 0x1ff | ...   | ... |
+---+---+---+-+
L2 CAT  | 0xff  | 0xff  | ...   | ... |
+---+---+---+-+

If Dom2 has same CBM values, it can reuse these registers which COS_ID=1.
That means, both Dom1 and Dom2 use same COS registers(ID=1) to save same
L3/L2 values. So, the value ref[1] is 2 which means 2 domains are using
COS_ID 1.

To manage a feature, we need define a feature node data structure,
'struct feat_node', to manage feature's specific HW info, its callback
functions (all feature's specific behaviors are encapsulated into these
callback functions), and an array of all COS registers values of this
feature.

CDP is a special feature which uses two entries of the array
for one COS ID. So, the number of CDP COS registers is the half of L3
CAT. E.g. L3 CAT has 16 COS registers, then CDP has 8 COS registers if
it is enabled. CDP uses the COS registers array as below.

 
+---+---+---+---+---+
CDP cos_reg_val[] index: | 0 | 1 | 2 | 3 |
...|
 
+---+---+---+---+---+
  value: | cos0 code | cos0 data | cos1 code | cos1 data |
...|
 
+---+---+---+---+---+

For more details, please refer spec and codes.

Signed-off-by: Yi Sun 
---
v5:
- explain CDP more in commit message.
- remove exact SDM chapter number but only keep title.
- remove init_feature from callback function ops structure.
---
 xen/arch/x86/psr.c | 104 +
 1 file changed, 104 insertions(+)

diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index 96a8589..f7ff3fc 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -17,12 +17,116 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
+/*
+ * Terminology:
+ * - CAT Cache Allocation Technology
+ * - CBM Capacity BitMasks
+ * - CDP Code and Data Prioritization
+ * - COS/CLOSClass 

[Xen-devel] [PATCH RESEND v5 12/24] x86: refactor psr: set value: implement write msr flow.

[Yi Sun]

Continue with previous patch:
'x86: refactor psr: set value: implement cos id picking flow.'

We have got all features values and COS ID to set. Then, we write MSRs of all
features except the setting value is same as original value.

Till now, set value process is completed.

Signed-off-by: Yi Sun 
---
v5:
- modify commit message to provide exact patch name to continue from.
- modify return value of callback functions because we do not need them
  to return number of entries the feature uses. In caller, we call
  'get_cos_num' to get the number of entries the feature uses.
- move type check out from callback functions to caller.
- modify variables names to make them better, e.g. 'feat_tmp' to 'feat'.
---
 xen/arch/x86/psr.c | 78 +-
 1 file changed, 77 insertions(+), 1 deletion(-)

diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index c3e25bf..b8d3c82 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -165,6 +165,9 @@ struct feat_ops {
 bool (*fits_cos_max)(const uint64_t val[],
  const struct feat_node *feat,
  unsigned int cos);
+/* write_msr is used to write out feature MSR register. */
+int (*write_msr)(unsigned int cos, const uint64_t val[],
+ struct feat_node *feat);
 };
 
 /*
@@ -418,6 +421,21 @@ static bool l3_cat_fits_cos_max(const uint64_t val[],
 return true;
 }
 
+static int l3_cat_write_msr(unsigned int cos, const uint64_t val[],
+struct feat_node *feat)
+{
+if ( cos > feat->info.l3_cat_info.cos_max )
+return -EINVAL;
+
+if ( feat->cos_reg_val[cos] != val[0] )
+{
+feat->cos_reg_val[cos] = val[0];
+wrmsrl(MSR_IA32_PSR_L3_MASK(cos), val[0]);
+}
+
+return 0;
+}
+
 static const struct feat_ops l3_cat_ops = {
 .get_cos_max = l3_cat_get_cos_max,
 .get_feat_info = l3_cat_get_feat_info,
@@ -427,6 +445,7 @@ static const struct feat_ops l3_cat_ops = {
 .set_new_val = l3_cat_set_new_val,
 .compare_val = l3_cat_compare_val,
 .fits_cos_max = l3_cat_fits_cos_max,
+.write_msr = l3_cat_write_msr,
 };
 
 static void __init parse_psr_bool(char *s, char *value, char *feature,
@@ -909,10 +928,67 @@ static int pick_avail_cos(const struct psr_socket_info 
*info,
 return -ENOENT;
 }
 
+static unsigned int get_socket_cpu(unsigned int socket)
+{
+if ( likely(socket < nr_sockets) )
+return cpumask_any(socket_cpumask[socket]);
+
+return nr_cpu_ids;
+}
+
+struct cos_write_info
+{
+unsigned int cos;
+struct list_head *feat_list;
+const uint64_t *val;
+};
+
+static void do_write_psr_msr(void *data)
+{
+struct cos_write_info *info = (struct cos_write_info *)data;
+unsigned int cos   = info->cos;
+struct list_head *feat_list= info->feat_list;
+const uint64_t *val= info->val;
+struct feat_node *feat;
+int ret;
+
+if ( !feat_list )
+return;
+
+/* We need set all features values into MSRs. */
+list_for_each_entry(feat, feat_list, list)
+{
+ret = feat->ops.write_msr(cos, val, feat);
+if ( ret < 0 )
+return;
+
+val += feat->ops.get_cos_num(feat);
+}
+}
+
 static int write_psr_msr(unsigned int socket, unsigned int cos,
  const uint64_t *val)
 {
-return -ENOENT;
+struct psr_socket_info *info = get_socket_info(socket);
+struct cos_write_info data =
+{
+.cos = cos,
+.feat_list = >feat_list,
+.val = val,
+};
+
+if ( socket == cpu_to_socket(smp_processor_id()) )
+do_write_psr_msr();
+else
+{
+unsigned int cpu = get_socket_cpu(socket);
+
+if ( cpu >= nr_cpu_ids )
+return -ENOTSOCK;
+on_selected_cpus(cpumask_of(cpu), do_write_psr_msr, , 1);
+}
+
+return 0;
 }
 
 int psr_set_val(struct domain *d, unsigned int socket,
-- 
1.9.1


___
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Xen-devel@lists.xen.org
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[Xen-devel] [PATCH RESEND v5 11/24] x86: refactor psr: set value: implement cos id picking flow.

[Yi Sun]

Continue with previous patch:
'x86: refactor psr: set value: implement cos finding flow.'

If fail to find a COS ID, we need pick a new COS ID for domain. Only COS ID
that ref[COS_ID] is 1 or 0 can be picked to input a new set feature values.

Signed-off-by: Yi Sun 
---
v5:
- modify commit message to provide exact patch name to continue from.
- change 'exceeds_cos_max' to 'fits_cos_max' to be accurate.
- modify comments according to changes of codes.
- modify return value of callback functions because we do not need them
  to return number of entries the feature uses. In caller, we call
  'get_cos_num' to get the number of entries the feature uses.
- move type check out from callback functions to caller.
- modify variables names to make them better, e.g. 'feat_tmp' to 'feat'.
---
 xen/arch/x86/psr.c | 99 ++
 1 file changed, 99 insertions(+)

diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index 8832e08..c3e25bf 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -154,6 +154,17 @@ struct feat_ops {
  */
 int (*compare_val)(const uint64_t val[], const struct feat_node *feat,
 unsigned int cos, bool *found);
+/*
+ * fits_cos_max is used to check if the input cos id exceeds the
+ * feature's cos_max and if the input value is not the default one.
+ * Even if the associated cos exceeds the cos_max, HW can work with default
+ * value. That is the reason we need check if input value is default one.
+ * If both criteria are fulfilled, that means the input exceeds the range.
+ * If not, that means the input fits the requirements.
+ */
+bool (*fits_cos_max)(const uint64_t val[],
+ const struct feat_node *feat,
+ unsigned int cos);
 };
 
 /*
@@ -388,6 +399,25 @@ static int l3_cat_compare_val(const uint64_t val[],
 return 0;
 }
 
+static bool l3_cat_fits_cos_max(const uint64_t val[],
+const struct feat_node *feat,
+unsigned int cos)
+{
+uint64_t l3_def_cbm;
+
+l3_def_cbm = (1ull << feat->info.l3_cat_info.cbm_len) - 1;
+
+if ( cos > feat->info.l3_cat_info.cos_max &&
+ val[0] != l3_def_cbm )
+/*
+ * Exceed cos_max and value to set is not default,
+ * return error.
+ */
+return false;
+
+return true;
+}
+
 static const struct feat_ops l3_cat_ops = {
 .get_cos_max = l3_cat_get_cos_max,
 .get_feat_info = l3_cat_get_feat_info,
@@ -396,6 +426,7 @@ static const struct feat_ops l3_cat_ops = {
 .get_old_val = l3_cat_get_old_val,
 .set_new_val = l3_cat_set_new_val,
 .compare_val = l3_cat_compare_val,
+.fits_cos_max = l3_cat_fits_cos_max,
 };
 
 static void __init parse_psr_bool(char *s, char *value, char *feature,
@@ -802,11 +833,79 @@ static int find_cos(const uint64_t *val, uint32_t 
array_len,
 return -ENOENT;
 }
 
+static bool fits_cos_max(const uint64_t *val,
+ uint32_t array_len,
+ const struct psr_socket_info *info,
+ unsigned int cos)
+{
+unsigned int ret;
+const uint64_t *val_tmp = val;
+const struct feat_node *feat;
+
+list_for_each_entry(feat, >feat_list, list)
+{
+ret = feat->ops.fits_cos_max(val_tmp, feat, cos);
+if ( !ret )
+return false;
+
+val_tmp += feat->ops.get_cos_num(feat);
+if ( val_tmp - val > array_len )
+return false;
+}
+
+return true;
+}
+
 static int pick_avail_cos(const struct psr_socket_info *info,
   const uint64_t *val, uint32_t array_len,
   unsigned int old_cos,
   enum psr_feat_type feat_type)
 {
+unsigned int cos;
+unsigned int cos_max = 0;
+const struct feat_node *feat;
+const unsigned int *ref = info->cos_ref;
+
+/*
+ * cos_max is the one of the feature which is being set.
+ */
+list_for_each_entry(feat, >feat_list, list)
+{
+if ( feat->feature != feat_type )
+continue;
+
+cos_max = feat->ops.get_cos_max(feat);
+if ( cos_max > 0 )
+break;
+}
+
+if ( !cos_max )
+return -ENOENT;
+
+/*
+ * If old cos is referred only by the domain, then use it. And, we cannot
+ * use id 0 because it stores the default values.
+ */
+if ( old_cos && ref[old_cos] == 1 &&
+ fits_cos_max(val, array_len, info, old_cos) )
+return old_cos;
+
+/* Find an unused one other than cos0. */
+for ( cos = 1; cos <= cos_max; cos++ )
+{
+/*
+ * ref is 0 means this COS is not used by other domain and
+ * can be used for current setting.
+ */
+if ( !ref[cos] )
+{
+if ( !fits_cos_max(val, 

[Xen-devel] [PATCH RESEND v5 04/24] x86: refactor psr: implement CPU init and free flow.

[Yi Sun]

This patch implements the CPU init and free flow including L3 CAT
initialization and feature list free.

Signed-off-by: Yi Sun 
---
v5:
- modify commit message beacuse of code changes.
- add 'struct cpuid_leaf_regs' to save cpu registers value to reduce
  parameters of init_feature function.
- modify comments to make them accurate.
- modify variables names to make them better, e.g. 'feat_tmp' to 'feat'.
- use 'list_for_each_entry_safe' when free features.
- do not delete 'feat_l3_cat' to make it can be reused when cpu online.
- use 'current_cpu_data'.
- clear 'X86_FEATURE_PQE' if cpuid_level is not right.
- Print socket info when 'opt_cpu_info' is true.
- remove 'cpu_prepare_work' function and move contents of it into
  'psr_cpu_prepare'.
---
 xen/arch/x86/psr.c | 176 -
 1 file changed, 174 insertions(+), 2 deletions(-)

diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index f7ff3fc..e9dc07a 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -35,6 +35,9 @@
 #define PSR_CAT(1<<1)
 #define PSR_CDP(1<<2)
 
+#define CAT_CBM_LEN_MASK 0x1f
+#define CAT_COS_MAX_MASK 0x
+
 /*
  * Per SDM chapter 'Cache Allocation Technology: Cache Mask Configuration',
  * the MSRs range from 0C90H through 0D0FH (inclusive), enables support for
@@ -127,6 +130,13 @@ struct feat_node {
 struct list_head list;
 };
 
+struct cpuid_leaf_regs {
+unsigned int eax;
+unsigned int ebx;
+unsigned int ecx;
+unsigned int edx;
+};
+
 struct psr_assoc {
 uint64_t val;
 uint64_t cos_mask;
@@ -134,11 +144,76 @@ struct psr_assoc {
 
 struct psr_cmt *__read_mostly psr_cmt;
 
+static struct psr_socket_info *__read_mostly socket_info;
+
 static unsigned int opt_psr;
 static unsigned int __initdata opt_rmid_max = 255;
+static unsigned int __read_mostly opt_cos_max = MAX_COS_REG_CNT;
 static uint64_t rmid_mask;
 static DEFINE_PER_CPU(struct psr_assoc, psr_assoc);
 
+/*
+ * Declare global feature list entry for every feature to facilitate the
+ * feature list creation. It will be allocated in psr_cpu_prepare() and
+ * inserted into feature list in cpu_init_work().
+ */
+static struct feat_node *feat_l3_cat;
+
+/* Common functions. */
+static void free_feature(struct psr_socket_info *info)
+{
+struct feat_node *feat, *next;
+
+if ( !info )
+return;
+
+list_for_each_entry_safe(feat, next, >feat_list, list)
+{
+clear_bit(feat->feature, >feat_mask);
+list_del(>list);
+xfree(feat);
+}
+}
+
+/* L3 CAT functions implementation. */
+static void l3_cat_init_feature(struct cpuid_leaf_regs regs,
+struct feat_node *feat,
+struct psr_socket_info *info)
+{
+struct psr_cat_hw_info l3_cat;
+unsigned int socket;
+
+/* No valid value so do not enable feature. */
+if ( !regs.eax || !regs.edx )
+return;
+
+l3_cat.cbm_len = (regs.eax & CAT_CBM_LEN_MASK) + 1;
+l3_cat.cos_max = min(opt_cos_max, regs.edx & CAT_COS_MAX_MASK);
+
+/* cos=0 is reserved as default cbm(all bits within cbm_len are 1). */
+feat->cos_reg_val[0] = (1ull << l3_cat.cbm_len) - 1;
+
+feat->feature = PSR_SOCKET_L3_CAT;
+__set_bit(PSR_SOCKET_L3_CAT, >feat_mask);
+
+feat->info.l3_cat_info = l3_cat;
+
+info->nr_feat++;
+
+/* Add this feature into list. */
+list_add_tail(>list, >feat_list);
+
+socket = cpu_to_socket(smp_processor_id());
+if ( opt_cpu_info )
+printk(XENLOG_INFO
+   "L3 CAT: enabled on socket %u, cos_max:%u, cbm_len:%u\n",
+   socket, feat->info.l3_cat_info.cos_max,
+   feat->info.l3_cat_info.cbm_len);
+}
+
+static const struct feat_ops l3_cat_ops = {
+};
+
 static void __init parse_psr_bool(char *s, char *value, char *feature,
   unsigned int mask)
 {
@@ -178,6 +253,9 @@ static void __init parse_psr_param(char *s)
 if ( val_str && !strcmp(s, "rmid_max") )
 opt_rmid_max = simple_strtoul(val_str, NULL, 0);
 
+if ( val_str && !strcmp(s, "cos_max") )
+opt_cos_max = simple_strtoul(val_str, NULL, 0);
+
 s = ss + 1;
 } while ( ss );
 }
@@ -333,18 +411,108 @@ void psr_domain_free(struct domain *d)
 psr_free_rmid(d);
 }
 
+static void cpu_init_work(void)
+{
+struct psr_socket_info *info;
+unsigned int socket;
+unsigned int cpu = smp_processor_id();
+struct feat_node *feat;
+struct cpuid_leaf_regs regs;
+
+if ( !cpu_has(_cpu_data, X86_FEATURE_PQE) )
+return;
+else if ( current_cpu_data.cpuid_level < PSR_CPUID_LEVEL_CAT )
+{
+clear_bit(X86_FEATURE_PQE, current_cpu_data.x86_capability);
+return;
+}
+
+socket = cpu_to_socket(cpu);
+info = socket_info + socket;
+if ( info->feat_mask )
+return;
+
+INIT_LIST_HEAD(>feat_list);
+

[Xen-devel] [PATCH RESEND v5 07/24] x86: refactor psr: implement get value flow.

[Yi Sun]

This patch implements get value flow including L3 CAT callback
function.

It also changes domctl interface to make it more general.

With this patch, 'psr-cat-show' can work for L3 CAT.

Signed-off-by: Yi Sun 
---
v5:
- rename 'dat[]' to 'data[]'
- modify variables names to make them better, e.g. 'feat_tmp' to 'feat'.
- check if feature type match in caller of feature callback function.
---
 xen/arch/x86/domctl.c | 18 +-
 xen/arch/x86/psr.c| 41 ++---
 xen/include/asm-x86/psr.h |  4 ++--
 3 files changed, 49 insertions(+), 14 deletions(-)

diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c
index ab141b1..11d2127 100644
--- a/xen/arch/x86/domctl.c
+++ b/xen/arch/x86/domctl.c
@@ -1383,23 +1383,23 @@ long arch_do_domctl(
 break;
 
 case XEN_DOMCTL_PSR_CAT_OP_GET_L3_CBM:
-ret = psr_get_l3_cbm(d, domctl->u.psr_cat_op.target,
- >u.psr_cat_op.data,
- PSR_CBM_TYPE_L3);
+ret = psr_get_val(d, domctl->u.psr_cat_op.target,
+  >u.psr_cat_op.data,
+  PSR_CBM_TYPE_L3);
 copyback = 1;
 break;
 
 case XEN_DOMCTL_PSR_CAT_OP_GET_L3_CODE:
-ret = psr_get_l3_cbm(d, domctl->u.psr_cat_op.target,
- >u.psr_cat_op.data,
- PSR_CBM_TYPE_L3_CODE);
+ret = psr_get_val(d, domctl->u.psr_cat_op.target,
+  >u.psr_cat_op.data,
+  PSR_CBM_TYPE_L3_CODE);
 copyback = 1;
 break;
 
 case XEN_DOMCTL_PSR_CAT_OP_GET_L3_DATA:
-ret = psr_get_l3_cbm(d, domctl->u.psr_cat_op.target,
- >u.psr_cat_op.data,
- PSR_CBM_TYPE_L3_DATA);
+ret = psr_get_val(d, domctl->u.psr_cat_op.target,
+  >u.psr_cat_op.data,
+  PSR_CBM_TYPE_L3_DATA);
 copyback = 1;
 break;
 
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index 319bfcc..3cbb60c 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -112,6 +112,9 @@ struct feat_ops {
 /* get_feat_info is used to get feature HW info. */
 bool (*get_feat_info)(const struct feat_node *feat,
   uint32_t data[], unsigned int array_len);
+/* get_val is used to get feature COS register value. */
+bool (*get_val)(const struct feat_node *feat, unsigned int cos,
+enum cbm_type type, uint64_t *val);
 };
 
 /*
@@ -251,9 +254,22 @@ static bool l3_cat_get_feat_info(const struct feat_node 
*feat,
 return true;
 }
 
+static bool l3_cat_get_val(const struct feat_node *feat, unsigned int cos,
+   enum cbm_type type, uint64_t *val)
+{
+if ( cos > feat->info.l3_cat_info.cos_max )
+/* Use default value. */
+cos = 0;
+
+*val =  feat->cos_reg_val[cos];
+
+return true;
+}
+
 static const struct feat_ops l3_cat_ops = {
 .get_cos_max = l3_cat_get_cos_max,
 .get_feat_info = l3_cat_get_feat_info,
+.get_val = l3_cat_get_val,
 };
 
 static void __init parse_psr_bool(char *s, char *value, char *feature,
@@ -498,10 +514,29 @@ int psr_get_info(unsigned int socket, enum cbm_type type,
 return -ENOENT;
 }
 
-int psr_get_l3_cbm(struct domain *d, unsigned int socket,
-   uint64_t *cbm, enum cbm_type type)
+int psr_get_val(struct domain *d, unsigned int socket,
+uint64_t *val, enum cbm_type type)
 {
-return 0;
+const struct psr_socket_info *info = get_socket_info(socket);
+unsigned int cos = d->arch.psr_cos_ids[socket];
+const struct feat_node *feat;
+enum psr_feat_type feat_type;
+
+if ( IS_ERR(info) )
+return PTR_ERR(info);
+
+feat_type = psr_cbm_type_to_feat_type(type);
+list_for_each_entry(feat, >feat_list, list)
+{
+if ( feat->feature != feat_type )
+continue;
+
+if ( feat->ops.get_val(feat, cos, type, val) )
+/* Found */
+return 0;
+}
+
+return -ENOENT;
 }
 
 int psr_set_l3_cbm(struct domain *d, unsigned int socket,
diff --git a/xen/include/asm-x86/psr.h b/xen/include/asm-x86/psr.h
index e3b18bc..d50e359 100644
--- a/xen/include/asm-x86/psr.h
+++ b/xen/include/asm-x86/psr.h
@@ -70,8 +70,8 @@ void psr_ctxt_switch_to(struct domain *d);
 
 int psr_get_info(unsigned int socket, enum cbm_type type,
  uint32_t data[], unsigned int array_len);
-int psr_get_l3_cbm(struct domain *d, unsigned int socket,
-   uint64_t *cbm, enum cbm_type type);
+int psr_get_val(struct domain *d, unsigned int socket,
+uint64_t *val, enum cbm_type type);
 int psr_set_l3_cbm(struct domain *d, unsigned int socket,

[Xen-devel] [PATCH RESEND v5 09/24] x86: refactor psr: set value: assemble features value array.

[Yi Sun]

Only can one COS ID be used by one domain at one time. That means all enabled
features' COS registers at this COS ID are valid for this domain at that time.

When user updates a feature's value, we need make sure all other features'
values are not affected. So, we firstly need assemble an array which contains
all features current values and replace the setting feature's value in array
to new value.

Then, we can try to find if there is a COS ID on which all features' COS
registers values are same as the array. If we can find, we just use this COS
ID. If fail to find, we need allocate a new COS ID.

This patch implements value array assembling flow.

Signed-off-by: Yi Sun 
---
v5:
- modify comments according to changes of codes.
- change 'bool_t' to 'bool'.
- modify return value of callback functions because we do not need them
  to return number of entries the feature uses. In caller, we call
  'get_cos_num' to get the number of entries the feature uses.
- modify variables names to make them better, e.g. 'feat_tmp' to 'feat'.
---
 xen/arch/x86/psr.c | 145 +++--
 1 file changed, 142 insertions(+), 3 deletions(-)

diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index 050b0df..7c6f2bf 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -115,6 +115,32 @@ struct feat_ops {
 /* get_val is used to get feature COS register value. */
 bool (*get_val)(const struct feat_node *feat, unsigned int cos,
 enum cbm_type type, uint64_t *val);
+/*
+ * get_cos_num is used to get the COS registers amount used by the
+ * feature for one setting, e.g. CDP uses 2 COSs but CAT uses 1.
+ */
+unsigned int (*get_cos_num)(const struct feat_node *feat);
+/*
+ * get_old_val and set_new_val are a pair of functions called in order.
+ * The caller will traverse all features in the list and call both
+ * functions for every feature to do below two things:
+ * 1. get old_cos register value of all supported features and
+ * 2. set the new value for the feature.
+ *
+ * All the values are set into value array according the traversal order,
+ * meaning the same order of feature list members.
+ *
+ * The return value meaning:
+ * 0 - success.
+ * negative - error.
+ */
+int (*get_old_val)(uint64_t val[],
+   const struct feat_node *feat,
+   unsigned int old_cos);
+int (*set_new_val)(uint64_t val[],
+   const struct feat_node *feat,
+   enum cbm_type type,
+   uint64_t m);
 };
 
 /*
@@ -200,6 +226,29 @@ static enum psr_feat_type psr_cbm_type_to_feat_type(enum 
cbm_type type)
 return feat_type;
 }
 
+static bool psr_check_cbm(unsigned int cbm_len, uint64_t cbm)
+{
+unsigned int first_bit, zero_bit;
+
+/* Set bits should only in the range of [0, cbm_len). */
+if ( cbm & (~0ull << cbm_len) )
+return false;
+
+/* At least one bit need to be set. */
+if ( cbm == 0 )
+return false;
+
+first_bit = find_first_bit(, cbm_len);
+zero_bit = find_next_zero_bit(, cbm_len, first_bit);
+
+/* Set bits should be contiguous. */
+if ( zero_bit < cbm_len &&
+ find_next_bit(, cbm_len, zero_bit) < cbm_len )
+return false;
+
+return true;
+}
+
 /* L3 CAT functions implementation. */
 static void l3_cat_init_feature(struct cpuid_leaf_regs regs,
 struct feat_node *feat,
@@ -266,10 +315,45 @@ static bool l3_cat_get_val(const struct feat_node *feat, 
unsigned int cos,
 return true;
 }
 
+static unsigned int l3_cat_get_cos_num(const struct feat_node *feat)
+{
+return 1;
+}
+
+static int l3_cat_get_old_val(uint64_t val[],
+  const struct feat_node *feat,
+  unsigned int old_cos)
+{
+if ( old_cos > feat->info.l3_cat_info.cos_max )
+/* Use default value. */
+old_cos = 0;
+
+/* CAT */
+val[0] =  feat->cos_reg_val[old_cos];
+
+return 0;
+}
+
+static int l3_cat_set_new_val(uint64_t val[],
+  const struct feat_node *feat,
+  enum cbm_type type,
+  uint64_t m)
+{
+if ( !psr_check_cbm(feat->info.l3_cat_info.cbm_len, m) )
+return -EINVAL;
+
+val[0] = m;
+
+return 0;
+}
+
 static const struct feat_ops l3_cat_ops = {
 .get_cos_max = l3_cat_get_cos_max,
 .get_feat_info = l3_cat_get_feat_info,
 .get_val = l3_cat_get_val,
+.get_cos_num = l3_cat_get_cos_num,
+.get_old_val = l3_cat_get_old_val,
+.set_new_val = l3_cat_set_new_val,
 };
 
 static void __init parse_psr_bool(char *s, char *value, char *feature,
@@ -542,7 +626,14 @@ int psr_get_val(struct domain *d, unsigned int socket,
 /* Set value functions */
 static unsigned int get_cos_num(const 

[Xen-devel] [PATCH RESEND v5 01/24] docs: create L2 Cache Allocation Technology (CAT) feature document

[Yi Sun]

This patch creates L2 CAT feature document in doc/features/.
It describes details of L2 CAT.

Signed-off-by: Yi Sun 
---
 docs/features/intel_psr_l2_cat.pandoc | 347 ++
 1 file changed, 347 insertions(+)
 create mode 100644 docs/features/intel_psr_l2_cat.pandoc

diff --git a/docs/features/intel_psr_l2_cat.pandoc 
b/docs/features/intel_psr_l2_cat.pandoc
new file mode 100644
index 000..77bd61f
--- /dev/null
+++ b/docs/features/intel_psr_l2_cat.pandoc
@@ -0,0 +1,347 @@
+% Intel L2 Cache Allocation Technology (L2 CAT) Feature
+% Revision 1.0
+
+\clearpage
+
+# Basics
+
+ 
+ Status: **Tech Preview**
+
+Architecture(s): Intel x86
+
+   Component(s): Hypervisor, toolstack
+
+   Hardware: Atom codename Goldmont and beyond CPUs
+ 
+
+# Overview
+
+L2 CAT allows an OS or Hypervisor/VMM to control allocation of a
+CPU's shared L2 cache based on application priority or Class of Service
+(COS). Each CLOS is configured using capacity bitmasks (CBM) which
+represent cache capacity and indicate the degree of overlap and
+isolation between classes. Once L2 CAT is configured, the processor
+allows access to portions of L2 cache according to the established
+class of service.
+
+## Terminology
+
+* CAT Cache Allocation Technology
+* CBM Capacity BitMasks
+* CDP Code and Data Prioritization
+* COS/CLOSClass of Service
+* MSRsMachine Specific Registers
+* PSR Intel Platform Shared Resource
+* VMM Virtual Machine Monitor
+
+# User details
+
+* Feature Enabling:
+
+  Add "psr=cat" to boot line parameter to enable all supported level CAT
+  features.
+
+* xl interfaces:
+
+  1. `psr-cat-show [OPTIONS] domain-id`:
+
+ Show domain L2 or L3 CAT CBM.
+
+ New option `-l` is added.
+ `-l2`: Show cbm for L2 cache.
+ `-l3`: Show cbm for L3 cache.
+
+ If neither `-l2` nor `-l3` is given, show both of them. If any one
+ is not supported, will print error info.
+
+  2. `psr-cat-cbm-set [OPTIONS] domain-id cbm`:
+
+ Set domain L2 or L3 CBM.
+
+ New option `-l` is added.
+ `-l2`: Specify cbm for L2 cache.
+ `-l3`: Specify cbm for L3 cache.
+
+ If neither `-l2` nor `-l3` is given, level 3 is the default option.
+
+  3. `psr-hwinfo [OPTIONS]`:
+
+ Show L2 & L3 CAT HW informations on every socket.
+
+# Technical details
+
+L2 CAT is a member of Intel PSR features and part of CAT, it shares
+some base PSR infrastructure in Xen.
+
+## Hardware perspective
+
+L2 CAT defines a new range MSRs to assign different L2 cache access
+patterns which are known as CBMs, each CBM is associated with a COS.
+
+```
+
++++
+   IA32_PQR_ASSOC   | MSR (per socket)   |Address |
+ ++---+---+ +++
+ ||COS|   | | IA32_L2_QOS_MASK_0 | 0xD10  |
+ ++---+---+ +++
+└-> | ...|  ...   |
++++
+| IA32_L2_QOS_MASK_n | 0xD10+n (n<64) |
++++
+```
+
+When context switch happens, the COS of VCPU is written to per-thread
+MSR `IA32_PQR_ASSOC`, and then hardware enforces L2 cache allocation
+according to the corresponding CBM.
+
+## The relationship between L2 CAT and L3 CAT/CDP
+
+L2 CAT is independent of L3 CAT/CDP, which means L2 CAT would be enabled
+while L3 CAT/CDP is disabled, or L2 CAT and L3 CAT/CDP are all enabled.
+
+L2 CAT uses a new range CBMs from 0xD10 ~ 0xD10+n (n<64), following by
+the L3 CAT/CDP CBMs, and supports setting different L2 cache accessing
+patterns from L3 cache. Like L3 CAT/CDP requirement, the bits of CBM of
+L2 CAT must be continuous too.
+
+N.B. L2 CAT and L3 CAT/CDP share the same COS field in the same
+associate register `IA32_PQR_ASSOC`, which means one COS associates to a
+pair of L2 CBM and L3 CBM.
+
+Besides, the max COS of L2 CAT may be different from L3 CAT/CDP (or
+other PSR features in future). In some cases, a VM is permitted to have a
+COS that is beyond one (or more) of PSR features but within the others.
+For instance, let's assume the max COS of L2 CAT is 8 but the max COS of
+L3 CAT is 16, when a VM is assigned 9 as COS, the L3 CBM associated to
+COS 9 would be enforced, but for L2 CAT, the behavior is fully open (no
+limit) since COS 9 is beyond the max COS (8) of L2 CAT.
+
+## Design Overview
+
+* Core COS/CBM association
+
+  When enforcing L2 CAT, all cores of domains have the same default
+  COS (COS0) which associated to the fully open CBM (all ones bitmask)
+  to access all L2 cache. 

[Xen-devel] [PATCH RESEND v5 00/24] Enable L2 Cache Allocation Technology & Refactor psr.c

[Yi Sun]

Hi all,

We plan to bring a new PSR (Platform Shared Resource) feature called
Intel L2 Cache Allocation Technology (L2 CAT) to Xen.

Besides the L2 CAT implementaion, we refactor the psr.c to make it more
flexible to add new features and fulfill the principle, open for extension
but closed for modification. We abstract the general operations of all
features and encapsulate them into a structure. Then, the development
of new feature is simple to mainly implement these callback functions.

The patch set can be found at:
https://github.com/yisun-git/xen_l2_cat_v5.git l2_cat_v5

v5:
- patch 3: address Jan's comments.
- explain CDP more in commit message.
- remove exact SDM chapter number but only keep title.
- remove init_feature from callback function ops structure.
- patch 4: address Jan's comments.
- modify commit message beacuse of code changes.
- add 'struct cpuid_leaf_regs' to save cpu registers value to reduce
  parameters of init_feature function.
- modify comments to make them accurate.
- modify variables names to make them better, e.g. 'feat_tmp' to 'feat'.
- use 'list_for_each_entry_safe' when free features.
- do not delete 'feat_l3_cat' to make it can be reused when cpu online.
- use 'current_cpu_data'.
- clear 'X86_FEATURE_PQE' if cpuid_level is not right.
- Print socket info when 'opt_cpu_info' is true.
- remove 'cpu_prepare_work' function and move contents of it into
  'psr_cpu_prepare'.
- patch 5: address Jan's comments.
- define macro 'PSR_ASSOC_REG_POS' to replace integer 32.
- rename 'l3_cat_get_max_cos_max' to 'l3_cat_get_cos_max'.
- modify variables names to make them better, e.g. 'feat_tmp' to 'feat'.
- patch 6: address Jan's comments.
- add function 'psr_cbm_type_to_feat_type' to covert 'cbm_type' to
  'psr_feat_type'. This is part of codes to move type check out from
  callback functions.
- remove type check from feature callback functions.
- rename 'dat[]' to 'data[]'
- check if feature type match in caller of feature callback function.
- patch 7: address Jan's comments.
- rename 'dat[]' to 'data[]'
- modify variables names to make them better, e.g. 'feat_tmp' to 'feat'.
- check if feature type match in caller of feature callback function.
- patch 8: address Jan's comments.
- modify commit message because of function name change.
- change 'alloc_new_cos' to 'pick_avail_cos' to make name accurate.
- divide 'get_old_set_new' to two functions, 'assemble_val_array' and
  'set_new_val_to_array'.
- check feature type when entering 'psr_set_val'.
- remove cast.
- use ASSERT to check ref.
- rename 'dat[]' to 'data[]'
- patch 9: address Jan's comments.
- modify comments according to changes of codes.
- change 'bool_t' to 'bool'.
- modify return value of callback functions because we do not need them
  to return number of entries the feature uses. In caller, we call
  'get_cos_num' to get the number of entries the feature uses.
- modify variables names to make them better, e.g. 'feat_tmp' to 'feat'.
- patch 10: address Jan's comments.
- modify commit message to provide exact patch name to continue from.
- remove 'get_cos_max_from_type' because it can be replaced by
  'get_cos_max'.
- move type check out from callback functions to caller.
- modify variables names to make them better, e.g. 'feat_tmp' to 'feat'.
- modify comments according to changes of codes.
- patch 11: address Jan's comments.
- modify commit message to provide exact patch name to continue from.
- change 'exceeds_cos_max' to 'fits_cos_max' to be accurate.
- modify comments according to changes of codes.
- modify return value of callback functions because we do not need them
  to return number of entries the feature uses. In caller, we call
  'get_cos_num' to get the number of entries the feature uses.
- move type check out from callback functions to caller.
- modify variables names to make them better, e.g. 'feat_tmp' to 'feat'.
- patch 12: address Jan's comments.
- modify commit message to provide exact patch name to continue from.
- modify return value of callback functions because we do not need them
  to return number of entries the feature uses. In caller, we call
  'get_cos_num' to get the number of entries the feature uses.
- move type check out from callback functions to caller.
- modify variables names to make them better, e.g. 'feat_tmp' to 'feat'.
- patch 13: address Jan's comments.
- remove 'feat_l3_cdp' free in 'free_feature'.
- Encapsulate cpuid registers into 'struct cpuid_leaf_regs'.
- Print socket info when 'opt_cpu_info' is true.
- rename 'l3_cdp_get_max_cos_max' to 'l3_cdp_get_cos_max'.
- rename 'dat[]' to 'data[]'
- move 'cpu_prepare_work' contents into 'psr_cpu_prepare'.
- patch 14: address Jan's comments.
- rename 'dat[]' to 'data[]'
- 

[Xen-devel] [PATCH v2 1/3] x86/mtrr: drop positive_have_wrcomb()

[Doug Goldstein]

The only call to have_wrcomb() was always to the generic implementation.
positive_have_wrcomb() was unused.

Signed-off-by: Doug Goldstein 
Acked-by: Jan Beulich 
---
Retaining ACK from <57b480fd027800106...@prv-mh.provo.novell.com>
---
---
 xen/arch/x86/cpu/mtrr/generic.c | 5 -
 xen/arch/x86/cpu/mtrr/mtrr.h| 2 --
 2 files changed, 7 deletions(-)

diff --git a/xen/arch/x86/cpu/mtrr/generic.c b/xen/arch/x86/cpu/mtrr/generic.c
index b7d3293..8d4537a 100644
--- a/xen/arch/x86/cpu/mtrr/generic.c
+++ b/xen/arch/x86/cpu/mtrr/generic.c
@@ -557,11 +557,6 @@ static int generic_have_wrcomb(void)
return (config & (1ULL << 10));
 }
 
-int positive_have_wrcomb(void)
-{
-   return 1;
-}
-
 /* generic structure...
  */
 const struct mtrr_ops generic_mtrr_ops = {
diff --git a/xen/arch/x86/cpu/mtrr/mtrr.h b/xen/arch/x86/cpu/mtrr/mtrr.h
index 53d369d..ec168f9 100644
--- a/xen/arch/x86/cpu/mtrr/mtrr.h
+++ b/xen/arch/x86/cpu/mtrr/mtrr.h
@@ -31,8 +31,6 @@ extern int generic_validate_add_page(unsigned long base, 
unsigned long size,
 
 extern const struct mtrr_ops generic_mtrr_ops;
 
-extern int positive_have_wrcomb(void);
-
 /* library functions for processor-specific routines */
 struct set_mtrr_context {
unsigned long flags;
-- 
git-series 0.9.1

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[Xen-devel] [PATCH v2 2/3] x86/mtrr: drop unused func prototypes and struct

[Doug Goldstein]

These weren't used so drop them.

Signed-off-by: Doug Goldstein 
Reviewed-by: Jan Beulich 
---
Retained R-b from <57b48184027800106...@prv-mh.provo.novell.com>
---
 xen/arch/x86/cpu/mtrr/mtrr.h | 15 ---
 1 file changed, 15 deletions(-)

diff --git a/xen/arch/x86/cpu/mtrr/mtrr.h b/xen/arch/x86/cpu/mtrr/mtrr.h
index ec168f9..bb57def 100644
--- a/xen/arch/x86/cpu/mtrr/mtrr.h
+++ b/xen/arch/x86/cpu/mtrr/mtrr.h
@@ -31,18 +31,6 @@ extern int generic_validate_add_page(unsigned long base, 
unsigned long size,
 
 extern const struct mtrr_ops generic_mtrr_ops;
 
-/* library functions for processor-specific routines */
-struct set_mtrr_context {
-   unsigned long flags;
-   unsigned long cr4val;
-   uint64_t deftype;
-   u32 ccr3;
-};
-
-void set_mtrr_done(struct set_mtrr_context *ctxt);
-void set_mtrr_cache_disable(struct set_mtrr_context *ctxt);
-void set_mtrr_prepare_save(struct set_mtrr_context *ctxt);
-
 void get_mtrr_state(void);
 
 extern void set_mtrr_ops(const struct mtrr_ops *);
@@ -56,6 +44,3 @@ extern const struct mtrr_ops *mtrr_if;
 extern unsigned int num_var_ranges;
 
 void mtrr_state_warn(void);
-
-extern int amd_init_mtrr(void);
-extern int cyrix_init_mtrr(void);
-- 
git-series 0.9.1

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[Xen-devel] [PATCH v2 3/3] x86/mtrr: convert use_intel_if u32 to bool

[Doug Goldstein]

This field is always only 1 currently but may allow 0 in the future so
convert it to a bool to provide proper range checking by the compiler.

Signed-off-by: Doug Goldstein 
---
 xen/arch/x86/cpu/mtrr/generic.c | 2 +-
 xen/arch/x86/cpu/mtrr/mtrr.h| 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/xen/arch/x86/cpu/mtrr/generic.c b/xen/arch/x86/cpu/mtrr/generic.c
index 8d4537a..104baf9 100644
--- a/xen/arch/x86/cpu/mtrr/generic.c
+++ b/xen/arch/x86/cpu/mtrr/generic.c
@@ -560,7 +560,7 @@ static int generic_have_wrcomb(void)
 /* generic structure...
  */
 const struct mtrr_ops generic_mtrr_ops = {
-   .use_intel_if  = 1,
+   .use_intel_if  = true,
.set_all   = generic_set_all,
.get   = generic_get_mtrr,
.get_free_region   = generic_get_free_region,
diff --git a/xen/arch/x86/cpu/mtrr/mtrr.h b/xen/arch/x86/cpu/mtrr/mtrr.h
index bb57def..ae4aad9 100644
--- a/xen/arch/x86/cpu/mtrr/mtrr.h
+++ b/xen/arch/x86/cpu/mtrr/mtrr.h
@@ -9,7 +9,7 @@
 
 struct mtrr_ops {
u32 vendor;
-   u32 use_intel_if;
+   booluse_intel_if;
 // void(*init)(void);
void(*set)(unsigned int reg, unsigned long base,
   unsigned long size, mtrr_type type);
@@ -39,7 +39,7 @@ extern u64 size_or_mask, size_and_mask;
 extern const struct mtrr_ops *mtrr_if;
 
 #define is_cpu(vnd)(mtrr_if && mtrr_if->vendor == X86_VENDOR_##vnd)
-#define use_intel()(mtrr_if && mtrr_if->use_intel_if == 1)
+#define use_intel()(mtrr_if && mtrr_if->use_intel_if == true)
 
 extern unsigned int num_var_ranges;
 
-- 
git-series 0.9.1

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[Xen-devel] [PATCH v2 0/3] x86/mtrr: basic cleanups

[Doug Goldstein]

Retained the parts that were not objected to by plans to disable mtrrs on
PVH containers.

Doug Goldstein (3):
  x86/mtrr: drop positive_have_wrcomb()
  x86/mtrr: drop unused func prototypes and struct
  x86/mtrr: convert use_intel_if u32 to bool

 xen/arch/x86/cpu/mtrr/generic.c |  7 +--
 xen/arch/x86/cpu/mtrr/mtrr.h| 21 ++---
 2 files changed, 3 insertions(+), 25 deletions(-)

base-commit: 12ec20c732a63f26dc243a847343b8b796c2d88c
-- 
git-series 0.9.1

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Re: [Xen-devel] [early RFC] ARM PCI Passthrough design document

[Manish Jaggi]

Hi Julien,

On 12/29/2016 07:34 PM, Julien Grall wrote:
> Hi all,
> 
> The document below is an early version of a design
> proposal for PCI Passthrough in Xen. It aims to
> describe from an high level perspective the interaction
> with the different subsystems and how guest will be able
> to discover and access PCI.
> 
> I am aware that a similar design has been posted recently
> by Cavium (see [1]), however the approach to expose PCI
> to guest is different. We have request to run unmodified
> baremetal OS on Xen, a such guest would directly
> access the devices and no PV drivers will be used.
> 
> That's why this design is based on emulating a root controller.
> This also has the advantage to have the VM interface as close
> as baremetal allowing the guest to use firmware tables to discover
> the devices.
> 
> Currently on ARM, Xen does not have any knowledge about PCI devices.
> This means that IOMMU and interrupt controller (such as ITS)
> requiring specific configuration will not work with PCI even with
> DOM0.
> 
> The PCI Passthrough work could be divided in 2 phases:
>   * Phase 1: Register all PCI devices in Xen => will allow
>  to use ITS and SMMU with PCI in Xen
> * Phase 2: Assign devices to guests
> 
> This document aims to describe the 2 phases, but for now only phase
> 1 is fully described.
> 
> I have sent the design document to start to gather feedback on
> phase 1.
> 
> Cheers,
> 
> [1] https://lists.xen.org/archives/html/xen-devel/2016-12/msg00224.html 
> 
> 
> % PCI pass-through support on ARM
> % Julien Grall 
> % Draft A
> 
> # Preface
> 
> This document aims to describe the components required to enable PCI
> passthrough on ARM.
> 
> This is an early draft and some questions are still unanswered, when this is
> the case the text will contain XXX.
> 
> # Introduction
> 
> PCI passthrough allows to give control of physical PCI devices to guest. This
> means that the guest will have full and direct access to the PCI device.
> 
> ARM is supporting one kind of guest that is exploiting as much as possible
> virtualization support in hardware. The guest will rely on PV driver only
> for IO (e.g block, network), interrupts will come through the virtualized
> interrupt controller. This means that there are no big changes required
> within the kernel.
> 
> By consequence, it would be possible to replace PV drivers by assigning real
> devices to the guest for I/O access. Xen on ARM would therefore be able to
> run unmodified operating system.
> 
> To achieve this goal, it looks more sensible to go towards emulating the
> host bridge (we will go into more details later). A guest would be able
> to take advantage of the firmware tables and obviating the need for a specific
> driver for Xen.
> 
> Thus in this document we follow the emulated host bridge approach.
> 
> # PCI terminologies
> 
> Each PCI device under a host bridge is uniquely identified by its Requester ID
> (AKA RID). A Requester ID is a triplet of Bus number, Device number, and
> Function.
> 
> When the platform has multiple host bridges, the software can add fourth
> number called Segment to differentiate host bridges. A PCI device will
> then uniquely by segment:bus:device:function (AKA SBDF).
> 
> So given a specific SBDF, it would be possible to find the host bridge and the
> RID associated to a PCI device.
> 
> # Interaction of the PCI subsystem with other subsystems
> 
> In order to have a PCI device fully working, Xen will need to configure
> other subsystems subsytems such as the SMMU and the Interrupt Controller.
> 
> The interaction expected between the PCI subsystem and the other is:
> * Add a device
> * Remove a device
> * Assign a device to a guest
> * Deassign a device from a guest
> 
> XXX: Detail the interaction when assigning/deassigning device
> 
> The following subsections will briefly describe the interaction from an
> higher level perspective. Implementation details (callback, structure...)
> is out of scope.
> 
> ## SMMU
> 
> The SMMU will be used to isolate the PCI device when accessing the memory
> (for instance DMA and MSI Doorbells). Often the SMMU will be configured using
> a StreamID (SID) that can be deduced from the RID with the help of the 
> firmware
> tables (see below).
> 
> Whilst in theory all the memory transaction issued by a PCI device should
> go through the SMMU, on certain platforms some of the memory transaction may
> not reach the SMMU because they are interpreted by the host bridge. For
> instance this could happen if the MSI doorbell is built into the PCI host
> bridge. See [6] for more details.
> 
> XXX: I think this could be solved by using the host memory layout when
> creating a guest with PCI devices => Detail it.
> 
> ## Interrupt controller
> 
> PCI supports three kind of interrupts: legacy interrupt, MSI and MSI-X. On ARM
> legacy interrupts will be mapped to SPIs. MSI and MSI-x will be

[Xen-devel] [PATCH v2] xen-netfront: Fix Rx stall during network stress and OOM

[Remanan Pillai]

From: Vineeth Remanan Pillai 

During an OOM scenario, request slots could not be created as skb
allocation fails. So the netback cannot pass in packets and netfront
wrongly assumes that there is no more work to be done and it disables
polling. This causes Rx to stall.

The issue is with the retry logic which schedules the timer if the
created slots are less than NET_RX_SLOTS_MIN. The count of new request
slots to be pushed are calculated as a difference between new req_prod
and rsp_cons which could be more than the actual slots, if there are
unconsumed responses.

The fix is to calculate the count of newly created slots as the
difference between new req_prod and old req_prod.

Signed-off-by: Vineeth Remanan Pillai 
Reviewed-by: Juergen Gross 
---
Changes in v2:
- Removed the old implementation of enabling polling on
  skb allocation error.
- Corrected the refill timer logic to schedule when newly
  created slots since last push is less than NET_RX_SLOTS_MIN.

 drivers/net/xen-netfront.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/xen-netfront.c b/drivers/net/xen-netfront.c
index 40f26b6..2c7c29f 100644
--- a/drivers/net/xen-netfront.c
+++ b/drivers/net/xen-netfront.c
@@ -321,7 +321,7 @@ static void xennet_alloc_rx_buffers(struct netfront_queue 
*queue)
queue->rx.req_prod_pvt = req_prod;
 
/* Not enough requests? Try again later. */
-   if (req_prod - queue->rx.rsp_cons < NET_RX_SLOTS_MIN) {
+   if (req_prod - queue->rx.sring->req_prod < NET_RX_SLOTS_MIN) {
mod_timer(>rx_refill_timer, jiffies + (HZ/10));
return;
}
-- 
2.7.4


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[Xen-devel] [ovmf baseline-only test] 68391: tolerable trouble: blocked/broken

[Platform Team regression test user]

This run is configured for baseline tests only.

flight 68391 ovmf real [real]
http://osstest.xs.citrite.net/~osstest/testlogs/logs/68391/

Failures :-/ but no regressions.

Regressions which are regarded as allowable (not blocking):
 build-i3863 host-install(3)   broken baseline untested
 build-amd64   3 host-install(3)   broken baseline untested
 build-i386-pvops  3 host-install(3)   broken baseline untested
 build-i386-xsm3 host-install(3)   broken baseline untested
 build-amd64-pvops 3 host-install(3)   broken baseline untested
 build-amd64-xsm   3 host-install(3)   broken baseline untested

Tests which did not succeed, but are not blocking:
 test-amd64-amd64-xl-qemuu-ovmf-amd64  1 build-check(1) blocked n/a
 build-amd64-libvirt   1 build-check(1)   blocked  n/a
 test-amd64-i386-xl-qemuu-ovmf-amd64  1 build-check(1)  blocked n/a
 build-i386-libvirt1 build-check(1)   blocked  n/a

version targeted for testing:
 ovmf 7be6e6776253d3638f03375e346e978228af5edb
baseline version:
 ovmf 315d9d08fd77db1024ccc5307823da8aaed85e2f

Last test of basis68383  2017-01-17 14:46:21 Z1 days
Testing same since68391  2017-01-18 11:19:02 Z0 days1 attempts


People who touched revisions under test:
  Gary Lin 

jobs:
 build-amd64-xsm  broken  
 build-i386-xsm   broken  
 build-amd64  broken  
 build-i386   broken  
 build-amd64-libvirt  blocked 
 build-i386-libvirt   blocked 
 build-amd64-pvopsbroken  
 build-i386-pvops broken  
 test-amd64-amd64-xl-qemuu-ovmf-amd64 blocked 
 test-amd64-i386-xl-qemuu-ovmf-amd64  blocked 



sg-report-flight on osstest.xs.citrite.net
logs: /home/osstest/logs
images: /home/osstest/images

Logs, config files, etc. are available at
http://osstest.xs.citrite.net/~osstest/testlogs/logs

Test harness code can be found at
http://xenbits.xensource.com/gitweb?p=osstest.git;a=summary

broken-step build-i386 host-install(3)
broken-step build-amd64 host-install(3)
broken-step build-i386-pvops host-install(3)
broken-step build-i386-xsm host-install(3)
broken-step build-amd64-pvops host-install(3)
broken-step build-amd64-xsm host-install(3)

Push not applicable.


commit 7be6e6776253d3638f03375e346e978228af5edb
Author: Gary Lin 
Date:   Mon Jan 16 14:30:10 2017 +0800

NetworkPkg/TlsAuthConfigDxe: Declare EFIAPI for the ChooseFile handler

The ChooseFile handler, UpdateCAFromFile, has to be EFIAPI or gcc would
use the wrong ABI and cause the crash of the firmware. This commit also
removes the unnecessary type casting in ChooseFile.

Cc: Siyuan Fu 
Cc: Jiaxin Wu 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gary Lin 
Reviewed-by: Siyuan Fu 
Reviewed-by: Jiaxin Wu 

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Re: [Xen-devel] [PATCH 6/6] x86/cpuid: Only recalculate the shared feature bits once

[Doug Goldstein]

On 1/18/17 2:40 PM, Andrew Cooper wrote:
> With accurate vendor information available, the shared bits can be sorted out
> during recalculation, rather than at query time in the legacy cpuid path.
> 
> This means that:
>  * Duplication can be dropped from the automatically generated cpuid data.
>  * The toolstack need not worry about setting them appropriately.
>  * They can be dropped from the system maximum featuresets.
> 
> While editing gen-cpuid.py, reflow some comments which exceeded the expected
> line length.
> 
> Signed-off-by: Andrew Cooper 

Reviewed-by: Doug Goldstein 

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Re: [Xen-devel] [PATCH 5/6] x86/cpuid: Handle the long vendor string in guest_cpuid()

[Doug Goldstein]

On 1/18/17 2:40 PM, Andrew Cooper wrote:
> Leaves 0x8002 through 0x8004 are plain ASCII text, and require no
> specific recalculation.
> 
> Signed-off-by: Andrew Cooper 

Reviewed-by: Doug Goldstein 

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Re: [Xen-devel] [PATCH 4/6] x86/cpuid: Handle leaf 0x80000000 in guest_cpuid()

[Doug Goldstein]

On 1/18/17 2:40 PM, Andrew Cooper wrote:
> The calculations for p->extd.max_leaf are reworked to force a value of at
> least 0x8000, and to take the domains chosen vendor into account when
> clamping maximum value.
> 
> The high short vendor information is clobbered or duplicated according to the
> chosen vendor.
> 
> Signed-off-by: Andrew Cooper 

Reviewed-by: Doug Goldstein 

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Re: [Xen-devel] [PATCH 3/6] x86/cpuid: Handle leaf 0 in guest_cpuid()

[Doug Goldstein]

On 1/18/17 2:40 PM, Andrew Cooper wrote:
> Calculate a domains x86_vendor early in recalculate_cpuid_policy(); subsequent
> patches need to make other recalculation decisions based on it.
> 
> Signed-off-by: Andrew Cooper 

Reviewed-by: Doug Goldstein 

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Re: [Xen-devel] [PATCH 2/6] x86/cpuid: Remove BUG_ON() condition from guest_cpuid()

[Doug Goldstein]

On 1/18/17 2:40 PM, Andrew Cooper wrote:
> Include a min() against the appropriate ARRAY_SIZE(), and ASSERT() that
> max_subleaf is within ARRAY_SIZE().
> 
> This is more robust to unexpected problems in a release build of Xen.
> 
> Signed-off-by: Andrew Cooper 

Reviewed-by: Doug Goldstein 

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Re: [Xen-devel] [PATCH 1/6] x86/cpuid: Hide VT-x/SVM from HVM-based control domains

[Doug Goldstein]

On 1/18/17 2:40 PM, Andrew Cooper wrote:
> The VT-x/SVM features are hidden from PV dom0 by the pv_featureset[] upper
> mask, but nothing thusfar has prevented the features being visible in

thus far? Could be the difference between British English and American
English.

> HVM-based control domains (where there is no toolstack decision to hide the
> features).
> 
> As a side effect of calling nestedhvm_enabled() earlier during domain
> creation, it needs to cope with the params[] array array not having been

array array?

> allocated.
> 
> Reported-by: Roger Pau Monné 
> Signed-off-by: Andrew Cooper 

Reviewed-by: Doug Goldstein 

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[Xen-devel] [PATCH v5 2/5] efi: build xen.gz with EFI code

[Doug Goldstein]

From: Daniel Kiper 

Build xen.gz with EFI code. We need this to support multiboot2
protocol on EFI platforms.

If we wish to load non-ELF file using multiboot (v1) or multiboot2 then
it must contain "linear" (or "flat") representation of code and data.
This is requirement of both boot protocols. Currently, PE file contains
many sections which are not "linear" (one after another without any holes)
or even do not have representation in a file (e.g. BSS). From EFI point
of view everything is OK and works. However, this file layout cannot be
properly interpreted by multiboot protocols family. In theory there is
a chance that we could build proper PE file (from multiboot protocols POV)
using current build system. However, it means that xen.efi further diverge
from Xen ELF file (in terms of contents and build method). On the other
hand ELF has all needed properties. So, it means that this is good starting
point for further development. Additionally, I think that this is also good
starting point for further xen.efi code and build optimizations. It looks
that there is a chance that finally we can generate xen.efi directly from
Xen ELF using just simple objcopy or other tool. This way we will have one
Xen binary which can be loaded by three boot protocols: EFI native loader,
multiboot (v1) and multiboot2.

Signed-off-by: Daniel Kiper 
Acked-by: Jan Beulich 
Reviewed-by: Doug Goldstein 
---
v6 - suggestions/fixes:
   - improve efi_enabled() checks in efi_runtime_call()
 (suggested by Jan Beulich).

v5 - suggestions/fixes:
   - properly calculate efi symbol address in
 xen/arch/x86/xen.lds.S (I hope that this
 change does not invalidate Jan's ACK).

v4 - suggestions/fixes:
   - functions should return -ENOSYS instead
 of -EOPNOTSUPP if EFI runtime services
 are not available
 (suggested by Jan Beulich),
   - remove stale bits from xen/arch/x86/Makefile
 (suggested by Jan Beulich).

v3 - suggestions/fixes:
   - check for EFI platform in EFI code
 (suggested by Jan Beulich),
   - fix Makefiles
 (suggested by Jan Beulich),
   - improve commit message
 (suggested by Jan Beulich).

v2 - suggestions/fixes:
   - build EFI code only if it is supported in a given build environment
 (suggested by Jan Beulich).
---
---
 xen/arch/x86/Makefile |  2 +-
 xen/arch/x86/efi/Makefile | 12 
 xen/arch/x86/xen.lds.S|  4 ++--
 xen/common/efi/boot.c |  3 +++
 xen/common/efi/runtime.c  |  9 +
 5 files changed, 19 insertions(+), 11 deletions(-)

diff --git a/xen/arch/x86/Makefile b/xen/arch/x86/Makefile
index 7f6b5d7..2e22cdf 100644
--- a/xen/arch/x86/Makefile
+++ b/xen/arch/x86/Makefile
@@ -219,6 +219,6 @@ efi/mkreloc: efi/mkreloc.c
 clean::
rm -f asm-offsets.s *.lds boot/*.o boot/*~ boot/core boot/mkelf32
rm -f $(BASEDIR)/.xen-syms.[0-9]* boot/.*.d
-   rm -f $(BASEDIR)/.xen.efi.[0-9]* efi/*.o efi/.*.d efi/*.efi 
efi/disabled efi/mkreloc
+   rm -f $(BASEDIR)/.xen.efi.[0-9]* efi/*.efi efi/disabled efi/mkreloc
rm -f boot/reloc.S boot/reloc.lnk boot/reloc.bin
rm -f note.o
diff --git a/xen/arch/x86/efi/Makefile b/xen/arch/x86/efi/Makefile
index ad3fdf7..442f3fc 100644
--- a/xen/arch/x86/efi/Makefile
+++ b/xen/arch/x86/efi/Makefile
@@ -1,18 +1,14 @@
 CFLAGS += -fshort-wchar
 
-obj-y += stub.o
-
-create = test -e $(1) || touch -t 19990101 $(1)
-
 efi := y$(shell rm -f disabled)
 efi := $(if $(efi),$(shell $(CC) $(filter-out $(CFLAGS-y) .%.d,$(CFLAGS)) -c 
check.c 2>disabled && echo y))
 efi := $(if $(efi),$(shell $(LD) -mi386pep --subsystem=10 -o check.efi check.o 
2>disabled && echo y))
-efi := $(if $(efi),$(shell rm disabled)y,$(shell $(call create,boot.init.o); 
$(call create,runtime.o)))
-
-extra-$(efi) += boot.init.o relocs-dummy.o runtime.o compat.o buildid.o
+efi := $(if $(efi),$(shell rm disabled)y)
 
 %.o: %.ihex
$(OBJCOPY) -I ihex -O binary $< $@
 
-stub.o: $(extra-y)
+obj-y := stub.o
+obj-$(efi) := boot.init.o compat.o relocs-dummy.o runtime.o
+extra-$(efi) += buildid.o
 nogcov-$(efi) += stub.o
diff --git a/xen/arch/x86/xen.lds.S b/xen/arch/x86/xen.lds.S
index 7676de9..b0b1c9b 100644
--- a/xen/arch/x86/xen.lds.S
+++ b/xen/arch/x86/xen.lds.S
@@ -270,10 +270,10 @@ SECTIONS
   .pad : {
 . = ALIGN(MB(16));
   } :text
-#else
-  efi = .;
 #endif
 
+  efi = DEFINED(efi) ? efi : .;
+
   /* Sections to be discarded */
   /DISCARD/ : {
*(.exit.text)
diff --git a/xen/common/efi/boot.c b/xen/common/efi/boot.c
index 3e5e4ab..df8c702 100644
--- a/xen/common/efi/boot.c
+++ b/xen/common/efi/boot.c
@@ -1251,6 +1251,9 @@ void __init efi_init_memory(void)
 } *extra, *extra_head = NULL;
 #endif
 
+if ( !efi_enabled(EFI_BOOT) )
+return;
+
 printk(XENLOG_INFO "EFI memory map:%s\n",
map_bs ? " (mapping BootServices)" : "");
 for ( i = 0; i < efi_memmap_size; i += efi_mdesc_size )
diff --git 

[Xen-devel] [PATCH v5 0/5] multiboot2 protocol support

[Doug Goldstein]

This is a series based on v11 of Daniel Kiper's
"x86: multiboot2 protocol support" series. It aims to collect up all the
fixes and changes that Andrew Cooper, Jan Beulich and myself discovered in
code review and testing on actual hardware. I've had problems with the
relocation portion of the series so I've dropped it as all the hardware I
am needing to support presently for my $EMPLOYER does not load anything at
the 1mb mark. To me this adds MB2 support for all pieces of hardware that
don't have things located at 1mb so it's an incremental step. I've also
dropped the early command line conversion to C as it was done in support
of the relocation changes and therefore not necessary. In the end my goal
is to help Daniel out by providing the portion of the series that works
on half a dozen physical machines I've tested with and integrates all
changes as discussed on the v11 thread. The reason I am posting this is that
Daniel has said he won't be able to address feedback and issues identified
for another 2 weeks but my requirements from my $EMPLOYER are more immediate
than that.

Feel free to grab this series at: https://github.com/cardoe/xen/tree/doug-mb2-v5

v5 - All changes contained within 5/5 along with a description there.
v4 - All changes contained within 5/5 along with a description there.
v3 - address review comments by Jan Beulich. They are contained within 5/5.
v2 - separate my fixes from Daniel's original series
   - add back some ACKs I accidentally dropped

Daniel Kiper (4):
  x86: add multiboot2 protocol support
  efi: build xen.gz with EFI code
  efi: create new early memory allocator
  x86: add multiboot2 protocol support for EFI platforms

Doug Goldstein (1):
  fix: add multiboot2 protocol support for EFI platforms

 xen/arch/x86/Makefile |   2 +-
 xen/arch/x86/boot/Makefile|   3 +-
 xen/arch/x86/boot/head.S  | 361 +--
 xen/arch/x86/boot/reloc.c | 148 -
 xen/arch/x86/efi/Makefile |  12 +-
 xen/arch/x86/efi/efi-boot.h   |  63 +++--
 xen/arch/x86/efi/stub.c   |  38 +++-
 xen/arch/x86/setup.c  |   3 +-
 xen/arch/x86/x86_64/asm-offsets.c |  11 +-
 xen/arch/x86/xen.lds.S|  16 +-
 xen/common/efi/boot.c |  64 +-
 xen/common/efi/runtime.c  |   9 +-
 xen/include/xen/config.h  |   1 +-
 xen/include/xen/multiboot2.h  | 169 +++-
 14 files changed, 852 insertions(+), 48 deletions(-)
 create mode 100644 xen/include/xen/multiboot2.h

base-commit: 98be5ffc05e689e2131f175ed95b011a7270db67
-- 
git-series 0.9.1

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[Xen-devel] [PATCH v5 5/5] fix: add multiboot2 protocol support for EFI platforms

[Doug Goldstein]

This should be squashed into the 4/4 patch 'x86: add multiboot2 protocol
support for EFI platforms'.

- fix incorrect assembly (identified by Andrew Cooper)
- fix issue where the trampoline size was left as 0 and the
  way the memory is allocated for the trampolines we would go to
  the end of an available section and then subtract off the size
  to decide where to place it. The end result was that we would
  always copy the trampolines and the 32-bit stack into some
  form of reserved memory after the conventional region we
  wanted to put things into. On some systems this did not
  manifest as a crash while on others it did. Reworked the
  changes to always reserve 64kb for both the stack and the size
  of the trampolines. Added a build time assert to make sure we have
  enough room always.

Signed-off-by: Doug Goldstein 
Reviewed-by: Jan Beulich 
---
Doug v5 - change comment style in xen.lds.S as requested by Jan Beulich.
- fix comment around ExitBootServices()
  (suggested by Andrew Cooper)
- change multiboot2 efi entry point name to __mb2_efi64_start
  (suggested by Andrew Cooper)
Doug v4 - change wording around "stack base"
  (found by Jan Beulich)
- added build time assert as suggested by Jan Beulich
- added a KB() macro to make our sizes consistent with MB() and
  GB().
Doug v3 - drop ASSERTs since they are runtime only without any output.
  This should be completely mitigated by using max() and
  ensuring we have a sane value.
  (found by Jan Beulich)
- removed extra_mem variable that was incorrectly left behind.
  (found by Jan Beulich)
- fix comment around the "start of stack"
  (found by Jan Beulich)
Doug v2 - new in this version to help show what's changed
---
---
 xen/arch/x86/boot/head.S| 7 ---
 xen/arch/x86/efi/efi-boot.h | 8 
 xen/arch/x86/efi/stub.c | 2 +-
 xen/arch/x86/xen.lds.S  | 8 
 xen/include/xen/config.h| 1 +
 5 files changed, 18 insertions(+), 8 deletions(-)

diff --git a/xen/arch/x86/boot/head.S b/xen/arch/x86/boot/head.S
index ac93df0..f2e8cc9 100644
--- a/xen/arch/x86/boot/head.S
+++ b/xen/arch/x86/boot/head.S
@@ -89,12 +89,12 @@ multiboot2_header_start:
0, /* Number of the lines - no preference. */ \
0  /* Number of bits per pixel - no preference. */
 
-/* Inhibit bootloader from calling ExitBootServices(). */
+/* Request that ExitBootServices() not be called. */
 mb2ht_init MB2_HT(EFI_BS), MB2_HT(OPTIONAL)
 
 /* EFI64 entry point. */
 mb2ht_init MB2_HT(ENTRY_ADDRESS_EFI64), MB2_HT(OPTIONAL), \
-   sym_phys(__efi64_start)
+   sym_phys(__mb2_efi64_start)
 
 /* Multiboot2 header end tag. */
 mb2ht_init MB2_HT(END), MB2_HT(REQUIRED)
@@ -169,7 +169,7 @@ not_multiboot:
 
 .code64
 
-__efi64_start:
+__mb2_efi64_start:
 cld
 
 /* VGA is not available on EFI platforms. */
@@ -519,6 +519,7 @@ trampoline_setup:
 1:
 /* Switch to low-memory stack.  */
 mov sym_phys(trampoline_phys),%edi
+/* The stack ends 64kb after the location of trampoline_phys */
 lea 0x1(%edi),%esp
 lea trampoline_boot_cpu_entry-trampoline_start(%edi),%eax
 pushl   $BOOT_CS32
diff --git a/xen/arch/x86/efi/efi-boot.h b/xen/arch/x86/efi/efi-boot.h
index dc857d8..d2ebf21 100644
--- a/xen/arch/x86/efi/efi-boot.h
+++ b/xen/arch/x86/efi/efi-boot.h
@@ -146,8 +146,6 @@ static void __init 
efi_arch_process_memory_map(EFI_SYSTEM_TABLE *SystemTable,
 {
 struct e820entry *e;
 unsigned int i;
-/* Check for extra mem for mbi data if Xen is loaded via multiboot2 
protocol. */
-UINTN extra_mem = efi_enabled(EFI_LOADER) ? 0 : (64 << 10);
 
 /* Populate E820 table and check trampoline area availability. */
 e = e820map - 1;
@@ -170,8 +168,7 @@ static void __init 
efi_arch_process_memory_map(EFI_SYSTEM_TABLE *SystemTable,
 /* fall through */
 case EfiConventionalMemory:
 if ( !trampoline_phys && desc->PhysicalStart + len <= 0x10 &&
- len >= cfg.size + extra_mem &&
- desc->PhysicalStart + len > cfg.addr )
+ len >= cfg.size && desc->PhysicalStart + len > cfg.addr )
 cfg.addr = (desc->PhysicalStart + len - cfg.size) & PAGE_MASK;
 /* fall through */
 case EfiLoaderCode:
@@ -686,6 +683,9 @@ paddr_t __init efi_multiboot2(EFI_HANDLE ImageHandle, 
EFI_SYSTEM_TABLE *SystemTa
 setup_efi_pci();
 efi_variables();
 
+/* This is the maximum size of our trampoline + our low memory stack */
+cfg.size = KB(64);
+
 if ( gop )
 efi_set_gop_mode(gop, gop_mode);
 
diff --git a/xen/arch/x86/efi/stub.c b/xen/arch/x86/efi/stub.c
index 6ea6aa1..b81adc0 100644
--- 

[Xen-devel] [PATCH v5 3/5] efi: create new early memory allocator

[Doug Goldstein]

From: Daniel Kiper 

There is a problem with place_string() which is used as early memory
allocator. It gets memory chunks starting from start symbol and goes
down. Sadly this does not work when Xen is loaded using multiboot2
protocol because then the start lives on 1 MiB address and we should
not allocate a memory from below of it. So, I tried to use mem_lower
address calculated by GRUB2. However, this solution works only on some
machines. There are machines in the wild (e.g. Dell PowerEdge R820)
which uses first ~640 KiB for boot services code or data... :-(((
Hence, we need new memory allocator for Xen EFI boot code which is
quite simple and generic and could be used by place_string() and
efi_arch_allocate_mmap_buffer(). I think about following solutions:

1) We could use native EFI allocation functions (e.g. AllocatePool()
   or AllocatePages()) to get memory chunk. However, later (somewhere
   in __start_xen()) we must copy its contents to safe place or reserve
   it in e820 memory map and map it in Xen virtual address space. This
   means that the code referring to Xen command line, loaded modules and
   EFI memory map, mostly in __start_xen(), will be further complicated
   and diverge from legacy BIOS cases. Additionally, both former things
   have to be placed below 4 GiB because their addresses are stored in
   multiboot_info_t structure which has 32-bit relevant members.

2) We may allocate memory area statically somewhere in Xen code which
   could be used as memory pool for early dynamic allocations. Looks
   quite simple. Additionally, it would not depend on EFI at all and
   could be used on legacy BIOS platforms if we need it. However, we
   must carefully choose size of this pool. We do not want increase Xen
   binary size too much and waste too much memory but also we must fit
   at least memory map on x86 EFI platforms. As I saw on small machine,
   e.g. IBM System x3550 M2 with 8 GiB RAM, memory map may contain more
   than 200 entries. Every entry on x86-64 platform is 40 bytes in size.
   So, it means that we need more than 8 KiB for EFI memory map only.
   Additionally, if we use this memory pool for Xen and modules command
   line storage (it would be used when xen.efi is executed as EFI application)
   then we should add, I think, about 1 KiB. In this case, to be on safe
   side, we should assume at least 64 KiB pool for early memory allocations.
   Which is about 4 times of our earlier calculations. However, during
   discussion on Xen-devel Jan Beulich suggested that just in case we should
   use 1 MiB memory pool like it is in original place_string() implementation.
   So, let's use 1 MiB as it was proposed. If we think that we should not
   waste unallocated memory in the pool on running system then we can mark
   this region as __initdata and move all required data to dynamically
   allocated places somewhere in __start_xen().

2a) We could put memory pool into .bss.page_aligned section. Then allocate
memory chunks starting from the lowest address. After init phase we can
free unused portion of the memory pool as in case of .init.text or 
.init.data
sections. This way we do not need to allocate any space in image file and
freeing of unused area in the memory pool is very simple.

Now #2a solution is implemented because it is quite simple and requires
limited number of changes, especially in __start_xen().

The new allocator is quite generic and can be used on ARM platforms too.

Signed-off-by: Daniel Kiper 
Acked-by: Jan Beulich 
Acked-by: Julien Grall 
Reviewed-by: Doug Goldstein 
---
Doug v1 - removed stale paragraph

v11 - suggestions/fixes:
- #ifdef only EBMALLOC_SIZE from ebmalloc machinery
  (suggested by Jan Beulich).

v10 - suggestions/fixes:
- remove unneeded ARM free_ebmalloc_unused_mem() stub.

v9 - suggestions/fixes:
   - call free_ebmalloc_unused_mem() from efi_init_memory()
 instead of xen/arch/arm/setup.c:init_done()
 (suggested by Jan Beulich),
   - improve comments.

v8 - suggestions/fixes:
   - disable whole ebmalloc machinery on ARM platforms,
   - add comment saying what should be done before
 enabling ebmalloc on ARM,
 (suggested by Julien Grall),
   - move ebmalloc code before efi-boot.h inclusion and
 remove unneeded forward declaration
 (suggested by Jan Beulich),
   - remove free_ebmalloc_unused_mem() call from
 xen/arch/arm/setup.c:init_done()
 (suggested by Julien Grall),
   - improve commit message.

v7 - suggestions/fixes:
   - enable most of ebmalloc machinery on ARM platforms
 (suggested by Jan Beulich),
   - remove unneeded cast
 (suggested by Jan Beulich),
   - wrap long line
 (suggested by Jan Beulich),
   - improve commit message.

v6 - suggestions/fixes:
   - optimize ebmalloc allocator,
   - move ebmalloc machinery to xen/common/efi/boot.c
 (suggested by 

[Xen-devel] [PATCH v5 4/5] x86: add multiboot2 protocol support for EFI platforms

[Doug Goldstein]

From: Daniel Kiper 

This way Xen can be loaded on EFI platforms using GRUB2 and
other boot loaders which support multiboot2 protocol.

Signed-off-by: Daniel Kiper 
Reviewed-by: Doug Goldstein 
Tested-by: Doug Goldstein 
---
Doug v2 - dropped all my changes and moved them into their own patch
Doug v1 - fix incorrect assembly (identified by Andrew Cooper)
- fix issue where the trampoline size was left as 0 and the
  way the memory is allocated for the trampolines we would go to
  the end of an available section and then subtract off the size
  to decide where to place it. The end result was that we would
  always copy the trampolines and the 32-bit stack into some
  form of reserved memory after the conventional region we
  wanted to put things into. On some systems this did not
  manifest as a crash while on others it did. Reworked the
  changes to always reserve 64kb for both the stack and the size
  of the trampolines. Added an ASSERT to make sure we never blow
  through this size.

v10 - suggestions/fixes:
- replace ljmpl with lretq
  (suggested by Andrew Cooper),
- introduce efi_platform to increase code readability
  (suggested by Andrew Cooper).

v9 - suggestions/fixes:
   - use .L labels instead of numeric ones in multiboot2 data scanning loops
 (suggested by Jan Beulich).

v8 - suggestions/fixes:
   - use __bss_start(%rip)/__bss_end(%rip) instead of
 of .startof.(.bss)(%rip)/$.sizeof.(.bss) because
 latter is not tested extensively in different
 built environments yet
 (suggested by Andrew Cooper),
   - fix multiboot2 data scanning loop in x86_32 code
 (suggested by Jan Beulich),
   - add check for extra mem for mbi data if Xen is loaded
 via multiboot2 protocol on EFI platform
 (suggested by Jan Beulich),
   - improve comments
 (suggested by Jan Beulich).

v7 - suggestions/fixes:
   - do not allocate twice memory for trampoline if we were
 loaded via multiboot2 protocol on EFI platform,
   - wrap long line
 (suggested by Jan Beulich),
   - improve comments
 (suggested by Jan Beulich).

v6 - suggestions/fixes:
   - improve label names in assembly
 error printing code
 (suggested by Jan Beulich),
   - improve comments
 (suggested by Jan Beulich),
   - various minor cleanups and fixes
 (suggested by Jan Beulich).

v4 - suggestions/fixes:
   - remove redundant BSS alignment,
   - update BSS alignment check,
   - use __set_bit() instead of set_bit() if possible
 (suggested by Jan Beulich),
   - call efi_arch_cpu() from efi_multiboot2()
 even if the same work is done later in
 other place right now
 (suggested by Jan Beulich),
   - xen/arch/x86/efi/stub.c:efi_multiboot2()
 fail properly on EFI platforms,
   - do not read data beyond the end of multiboot2
 information in xen/arch/x86/boot/head.S
 (suggested by Jan Beulich),
   - use 32-bit registers in x86_64 code if possible
 (suggested by Jan Beulich),
   - multiboot2 information address is 64-bit
 in x86_64 code, so, treat it is as is
 (suggested by Jan Beulich),
   - use cmovcc if possible,
   - leave only one space between rep and stosq
 (suggested by Jan Beulich),
   - improve error handling,
   - improve early error messages,
 (suggested by Jan Beulich),
   - improve early error messages printing code,
   - improve label names
 (suggested by Jan Beulich),
   - improve comments
 (suggested by Jan Beulich),
   - various minor cleanups.

v3 - suggestions/fixes:
   - take into account alignment when skipping multiboot2 fixed part
 (suggested by Konrad Rzeszutek Wilk),
   - improve segment registers initialization
 (suggested by Jan Beulich),
   - improve comments
 (suggested by Jan Beulich and Konrad Rzeszutek Wilk),
   - improve commit message
 (suggested by Jan Beulich).

v2 - suggestions/fixes:
   - generate multiboot2 header using macros
 (suggested by Jan Beulich),
   - switch CPU to x86_32 mode before
 jumping to 32-bit code
 (suggested by Andrew Cooper),
   - reduce code changes to increase patch readability
 (suggested by Jan Beulich),
   - improve comments
 (suggested by Jan Beulich),
   - ignore MULTIBOOT2_TAG_TYPE_BASIC_MEMINFO tag on EFI platform
 and find on my own multiboot2.mem_lower value,
   - stop execution if EFI platform is detected
 in legacy BIOS path.
---
---
 xen/arch/x86/boot/head.S  | 263 +--
 xen/arch/x86/efi/efi-boot.h   |  54 +-
 xen/arch/x86/efi/stub.c   |  38 -
 xen/arch/x86/x86_64/asm-offsets.c |   2 +-
 xen/arch/x86/xen.lds.S|   4 +-
 xen/common/efi/boot.c |  11 +-
 6 files changed, 349 insertions(+), 23 deletions(-)

diff --git a/xen/arch/x86/boot/head.S b/xen/arch/x86/boot/head.S
index 

[Xen-devel] [PATCH v5 1/5] x86: add multiboot2 protocol support

[Doug Goldstein]

From: Daniel Kiper 

Add multiboot2 protocol support. Alter min memory limit handling as we
now may not find it from either multiboot (v1) or multiboot2.

This way we are laying the foundation for EFI + GRUB2 + Xen development.

Signed-off-by: Daniel Kiper 
Reviewed-by: Jan Beulich 
Reviewed-by: Doug Goldstein 
---
v9 - suggestions/fixes:
   - use .L label instead of numeric one in multiboot2 data scanning loop;
 I hope that this change does not invalidate Jan's Reviewed-by
 (suggested by Jan Beulich).

v8 - suggestions/fixes:
   - use sizeof(/) instead of sizeof()
 if it is possible
 (suggested by Jan Beulich).

v7 - suggestions/fixes:
   - rename mbi_mbi/mbi2_mbi to mbi_reloc/mbi2_reloc respectively
 (suggested by Jan Beulich),
   - initialize mbi_out->flags using "|=" instead of "="
 (suggested by Jan Beulich),
   - use sizeof(*mmap_dst) instead of sizeof(memory_map_t)
 if it makes sense
 (suggested by Jan Beulich).

v6 - suggestions/fixes:
   - properly index multiboot2_tag_mmap_t.entries[]
 (suggested by Jan Beulich),
   - do not index mbi_out_mods[] beyond its end
 (suggested by Andrew Cooper),
   - reduce number of casts
 (suggested by Andrew Cooper and Jan Beulich),
   - add braces to increase code readability
 (suggested by Andrew Cooper).

v5 - suggestions/fixes:
   - check multiboot2_tag_mmap_t.entry_size before
 multiboot2_tag_mmap_t.entries[] use
 (suggested by Jan Beulich),
   - properly index multiboot2_tag_mmap_t.entries[]
 (suggested by Jan Beulich),
   - use "type name[]" instad of "type name[0]"
 in xen/include/xen/multiboot2.h
 (suggested by Jan Beulich),
   - remove unneeded comment
 (suggested by Jan Beulich).

v4 - suggestions/fixes:
   - avoid assembly usage in xen/arch/x86/boot/reloc.c,
   - fix boundary check issue and optimize
 for() loops in mbi2_mbi(),
   - move to stdcall calling convention,
   - remove unneeded typeof() from ALIGN_UP() macro
 (suggested by Jan Beulich),
   - add and use NULL definition in xen/arch/x86/boot/reloc.c
 (suggested by Jan Beulich),
   - do not read data beyond the end of multiboot2
 information in xen/arch/x86/boot/head.S
 (suggested by Jan Beulich),
   - add :req to some .macro arguments
 (suggested by Jan Beulich),
   - use cmovcc if possible,
   - add .L to multiboot2_header_end label
 (suggested by Jan Beulich),
   - add .L to multiboot2_proto label
 (suggested by Jan Beulich),
   - improve label names
 (suggested by Jan Beulich).

v3 - suggestions/fixes:
   - reorder reloc() arguments
 (suggested by Jan Beulich),
   - remove .L from multiboot2 header labels
 (suggested by Andrew Cooper, Jan Beulich and Konrad Rzeszutek Wilk),
   - take into account alignment when skipping multiboot2 fixed part
 (suggested by Konrad Rzeszutek Wilk),
   - create modules data if modules count != 0
 (suggested by Jan Beulich),
   - improve macros
 (suggested by Jan Beulich),
   - reduce number of casts
 (suggested by Jan Beulich),
   - use const if possible
 (suggested by Jan Beulich),
   - drop static and __used__ attribute from reloc()
 (suggested by Jan Beulich),
   - remove isolated/stray __packed attribute from
 multiboot2_memory_map_t type definition
 (suggested by Jan Beulich),
   - reformat xen/include/xen/multiboot2.h
 (suggested by Konrad Rzeszutek Wilk),
   - improve comments
 (suggested by Konrad Rzeszutek Wilk),
   - remove hard tabs
 (suggested by Jan Beulich and Konrad Rzeszutek Wilk).

v2 - suggestions/fixes:
   - generate multiboot2 header using macros
 (suggested by Jan Beulich),
   - improve comments
 (suggested by Jan Beulich),
   - simplify assembly in xen/arch/x86/boot/head.S
 (suggested by Jan Beulich),
   - do not include include/xen/compiler.h
 in xen/arch/x86/boot/reloc.c
 (suggested by Jan Beulich),
   - do not read data beyond the end of multiboot2 information
 (suggested by Jan Beulich).

v2 - not fixed yet:
   - dynamic dependency generation for xen/arch/x86/boot/reloc.S;
 this requires more work; I am not sure that it pays because
 potential patch requires more changes than addition of just
 multiboot2.h to Makefile
 (suggested by Jan Beulich),
   - isolated/stray __packed attribute usage for multiboot2_memory_map_t
 (suggested by Jan Beulich).
---
---
 xen/arch/x86/boot/Makefile|   3 +-
 xen/arch/x86/boot/head.S  | 107 +++-
 xen/arch/x86/boot/reloc.c | 148 ++-
 xen/arch/x86/x86_64/asm-offsets.c |   9 ++-
 xen/include/xen/multiboot2.h  | 169 +++-
 5 files changed, 426 insertions(+), 10 deletions(-)
 create mode 100644 xen/include/xen/multiboot2.h

diff --git a/xen/arch/x86/boot/Makefile b/xen/arch/x86/boot/Makefile
index 5fdb5ae..06893d8 100644
--- 

Re: [Xen-devel] [PATCH v4 5/5] fix: add multiboot2 protocol support for EFI platforms

[Doug Goldstein]

On 1/18/17 4:25 PM, Daniel Kiper wrote:
> On Wed, Jan 18, 2017 at 07:52:44AM -0700, Jan Beulich wrote:

>>
>> ... the comment style here fixed (which could be done upon commit
>> or when Daniel merges this back into his series).
> 
> Hmmm... Why this patch and #0 was not CC-ed to me?
>

You say this like I did it intentionally to upset you. I switched to
using git-series and as a result my workflow changed slightly. When I
glanced at 1/5 it had you CCed and I assumed this one was as well.

> Anyway, it looks that I have cleared my backlog to some extent and now I am
> able to take a stab on v12. There is a chance that I will have it with Doug's
> and some additional fixes on Friday or Monday.

So then there should be no issue with this landing before that or not.
The changes for you will be identical. A simple rebase --onto would
actually be easier than folding this into your larger series.

Can you tell me what were the fixes to the relocation code?

-- 
Doug Goldstein



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[Xen-devel] [distros-debian-squeeze test] 68390: trouble: blocked/broken

[Platform Team regression test user]

flight 68390 distros-debian-squeeze real [real]
http://osstest.xs.citrite.net/~osstest/testlogs/logs/68390/

Failures and problems with tests :-(

Tests which did not succeed and are blocking,
including tests which could not be run:
 build-armhf-pvops 3 host-install(3) broken REGR. vs. 68358
 build-armhf   3 host-install(3) broken REGR. vs. 68358
 build-i386-pvops  3 host-install(3) broken REGR. vs. 68358
 build-i3863 host-install(3) broken REGR. vs. 68358
 build-amd64   3 host-install(3) broken REGR. vs. 68358
 build-amd64-pvops 3 host-install(3) broken REGR. vs. 68358

Tests which did not succeed, but are not blocking:
 test-amd64-i386-amd64-squeeze-netboot-pygrub  1 build-check(1) blocked n/a
 test-amd64-amd64-amd64-squeeze-netboot-pygrub  1 build-check(1)blocked n/a
 test-amd64-i386-i386-squeeze-netboot-pygrub  1 build-check(1)  blocked n/a
 test-amd64-amd64-i386-squeeze-netboot-pygrub  1 build-check(1) blocked n/a

baseline version:
 flight   68358

jobs:
 build-amd64  broken  
 build-armhf  broken  
 build-i386   broken  
 build-amd64-pvopsbroken  
 build-armhf-pvopsbroken  
 build-i386-pvops broken  
 test-amd64-amd64-amd64-squeeze-netboot-pygrubblocked 
 test-amd64-i386-amd64-squeeze-netboot-pygrub blocked 
 test-amd64-amd64-i386-squeeze-netboot-pygrub blocked 
 test-amd64-i386-i386-squeeze-netboot-pygrub  blocked 



sg-report-flight on osstest.xs.citrite.net
logs: /home/osstest/logs
images: /home/osstest/images

Logs, config files, etc. are available at
http://osstest.xs.citrite.net/~osstest/testlogs/logs

Test harness code can be found at
http://xenbits.xensource.com/gitweb?p=osstest.git;a=summary


Push not applicable.


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[Xen-devel] [ovmf test] 104261: all pass - PUSHED

[osstest service owner]

flight 104261 ovmf real [real]
http://logs.test-lab.xenproject.org/osstest/logs/104261/

Perfect :-)
All tests in this flight passed as required
version targeted for testing:
 ovmf 88fd27e5b2cae68ff5a11cd5560ef5f98d001c42
baseline version:
 ovmf 7be6e6776253d3638f03375e346e978228af5edb

Last test of basis   104239  2017-01-18 05:15:57 Z0 days
Testing same since   104254  2017-01-18 11:13:19 Z0 days2 attempts


People who touched revisions under test:
  Star Zeng 

jobs:
 build-amd64-xsm  pass
 build-i386-xsm   pass
 build-amd64  pass
 build-i386   pass
 build-amd64-libvirt  pass
 build-i386-libvirt   pass
 build-amd64-pvopspass
 build-i386-pvops pass
 test-amd64-amd64-xl-qemuu-ovmf-amd64 pass
 test-amd64-i386-xl-qemuu-ovmf-amd64  pass



sg-report-flight on osstest.test-lab.xenproject.org
logs: /home/logs/logs
images: /home/logs/images

Logs, config files, etc. are available at
http://logs.test-lab.xenproject.org/osstest/logs

Explanation of these reports, and of osstest in general, is at
http://xenbits.xen.org/gitweb/?p=osstest.git;a=blob;f=README.email;hb=master
http://xenbits.xen.org/gitweb/?p=osstest.git;a=blob;f=README;hb=master

Test harness code can be found at
http://xenbits.xen.org/gitweb?p=osstest.git;a=summary


Pushing revision :

+ branch=ovmf
+ revision=88fd27e5b2cae68ff5a11cd5560ef5f98d001c42
+ . ./cri-lock-repos
++ . ./cri-common
+++ . ./cri-getconfig
+++ umask 002
+++ getrepos
 getconfig Repos
 perl -e '
use Osstest;
readglobalconfig();
print $c{"Repos"} or die $!;
'
+++ local repos=/home/osstest/repos
+++ '[' -z /home/osstest/repos ']'
+++ '[' '!' -d /home/osstest/repos ']'
+++ echo /home/osstest/repos
++ repos=/home/osstest/repos
++ repos_lock=/home/osstest/repos/lock
++ '[' x '!=' x/home/osstest/repos/lock ']'
++ OSSTEST_REPOS_LOCK_LOCKED=/home/osstest/repos/lock
++ exec with-lock-ex -w /home/osstest/repos/lock ./ap-push ovmf 
88fd27e5b2cae68ff5a11cd5560ef5f98d001c42
+ branch=ovmf
+ revision=88fd27e5b2cae68ff5a11cd5560ef5f98d001c42
+ . ./cri-lock-repos
++ . ./cri-common
+++ . ./cri-getconfig
+++ umask 002
+++ getrepos
 getconfig Repos
 perl -e '
use Osstest;
readglobalconfig();
print $c{"Repos"} or die $!;
'
+++ local repos=/home/osstest/repos
+++ '[' -z /home/osstest/repos ']'
+++ '[' '!' -d /home/osstest/repos ']'
+++ echo /home/osstest/repos
++ repos=/home/osstest/repos
++ repos_lock=/home/osstest/repos/lock
++ '[' x/home/osstest/repos/lock '!=' x/home/osstest/repos/lock ']'
+ . ./cri-common
++ . ./cri-getconfig
++ umask 002
+ select_xenbranch
+ case "$branch" in
+ tree=ovmf
+ xenbranch=xen-unstable
+ '[' xovmf = xlinux ']'
+ linuxbranch=
+ '[' x = x ']'
+ qemuubranch=qemu-upstream-unstable
+ select_prevxenbranch
++ ./cri-getprevxenbranch xen-unstable
+ prevxenbranch=xen-4.8-testing
+ '[' x88fd27e5b2cae68ff5a11cd5560ef5f98d001c42 = x ']'
+ : tested/2.6.39.x
+ . ./ap-common
++ : osst...@xenbits.xen.org
+++ getconfig OsstestUpstream
+++ perl -e '
use Osstest;
readglobalconfig();
print $c{"OsstestUpstream"} or die $!;
'
++ :
++ : git://xenbits.xen.org/xen.git
++ : osst...@xenbits.xen.org:/home/xen/git/xen.git
++ : git://xenbits.xen.org/qemu-xen-traditional.git
++ : git://git.kernel.org
++ : git://git.kernel.org/pub/scm/linux/kernel/git
++ : git
++ : git://xenbits.xen.org/xtf.git
++ : osst...@xenbits.xen.org:/home/xen/git/xtf.git
++ : git://xenbits.xen.org/xtf.git
++ : git://xenbits.xen.org/libvirt.git
++ : osst...@xenbits.xen.org:/home/xen/git/libvirt.git
++ : git://xenbits.xen.org/libvirt.git
++ : git://xenbits.xen.org/osstest/rumprun.git
++ : git
++ : git://xenbits.xen.org/osstest/rumprun.git
++ : osst...@xenbits.xen.org:/home/xen/git/osstest/rumprun.git
++ : git://git.seabios.org/seabios.git
++ : osst...@xenbits.xen.org:/home/xen/git/osstest/seabios.git
++ : git://xenbits.xen.org/osstest/seabios.git
++ : https://github.com/tianocore/edk2.git
++ : osst...@xenbits.xen.org:/home/xen/git/osstest/ovmf.git
++ : git://xenbits.xen.org/osstest/ovmf.git
++ : git://xenbits.xen.org/osstest/linux-firmware.git
++ : osst...@xenbits.xen.org:/home/osstest/ext/linux-firmware.git
++ : git://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git
++ : 

[Xen-devel] [xen-4.6-testing test] 104251: tolerable FAIL - PUSHED

[osstest service owner]

flight 104251 xen-4.6-testing real [real]
http://logs.test-lab.xenproject.org/osstest/logs/104251/

Failures :-/ but no regressions.

Regressions which are regarded as allowable (not blocking):
 test-armhf-armhf-libvirt-xsm 13 saverestore-support-checkfail  like 103795
 test-armhf-armhf-libvirt-raw 12 saverestore-support-checkfail  like 103795
 test-armhf-armhf-libvirt 13 saverestore-support-checkfail  like 103795
 test-amd64-i386-xl-qemuu-win7-amd64 16 guest-stop fail like 103795
 test-amd64-i386-xl-qemut-win7-amd64 16 guest-stop fail like 103795
 test-amd64-amd64-xl-qemuu-win7-amd64 16 guest-stopfail like 103795
 test-armhf-armhf-libvirt-qcow2 12 saverestore-support-check   fail like 103795
 test-amd64-amd64-xl-qemut-win7-amd64 16 guest-stopfail like 103795
 test-armhf-armhf-xl-rtds 15 guest-start/debian.repeatfail  like 103795

Tests which did not succeed, but are not blocking:
 test-xtf-amd64-amd64-4   62 xtf/test-pv32pae-xsa-194 fail   never pass
 test-xtf-amd64-amd64-5   62 xtf/test-pv32pae-xsa-194 fail   never pass
 test-xtf-amd64-amd64-3   62 xtf/test-pv32pae-xsa-194 fail   never pass
 test-xtf-amd64-amd64-1   62 xtf/test-pv32pae-xsa-194 fail   never pass
 test-amd64-amd64-libvirt-xsm 12 migrate-support-checkfail   never pass
 test-xtf-amd64-amd64-2   62 xtf/test-pv32pae-xsa-194 fail   never pass
 test-amd64-i386-libvirt-xsm  12 migrate-support-checkfail   never pass
 test-amd64-amd64-xl-pvh-intel 11 guest-start  fail  never pass
 test-amd64-amd64-libvirt 12 migrate-support-checkfail   never pass
 test-amd64-i386-libvirt  12 migrate-support-checkfail   never pass
 test-amd64-amd64-xl-pvh-amd  11 guest-start  fail   never pass
 test-amd64-amd64-libvirt-qemuu-debianhvm-amd64-xsm 10 migrate-support-check 
fail never pass
 test-amd64-i386-libvirt-qemuu-debianhvm-amd64-xsm 10 migrate-support-check 
fail never pass
 test-armhf-armhf-xl-arndale  12 migrate-support-checkfail   never pass
 test-armhf-armhf-xl-arndale  13 saverestore-support-checkfail   never pass
 test-armhf-armhf-xl  12 migrate-support-checkfail   never pass
 test-armhf-armhf-xl  13 saverestore-support-checkfail   never pass
 test-armhf-armhf-libvirt-xsm 12 migrate-support-checkfail   never pass
 test-amd64-amd64-qemuu-nested-amd 16 debian-hvm-install/l1/l2  fail never pass
 test-amd64-amd64-libvirt-vhd 11 migrate-support-checkfail   never pass
 test-armhf-armhf-libvirt-raw 11 migrate-support-checkfail   never pass
 test-armhf-armhf-xl-xsm  12 migrate-support-checkfail   never pass
 test-armhf-armhf-xl-xsm  13 saverestore-support-checkfail   never pass
 test-armhf-armhf-xl-cubietruck 12 migrate-support-checkfail never pass
 test-armhf-armhf-xl-cubietruck 13 saverestore-support-checkfail never pass
 test-armhf-armhf-xl-multivcpu 12 migrate-support-checkfail  never pass
 test-armhf-armhf-xl-multivcpu 13 saverestore-support-checkfail  never pass
 test-armhf-armhf-xl-credit2  12 migrate-support-checkfail   never pass
 test-armhf-armhf-xl-credit2  13 saverestore-support-checkfail   never pass
 test-armhf-armhf-libvirt 12 migrate-support-checkfail   never pass
 test-armhf-armhf-xl-vhd  11 migrate-support-checkfail   never pass
 test-armhf-armhf-xl-vhd  12 saverestore-support-checkfail   never pass
 test-armhf-armhf-libvirt-qcow2 11 migrate-support-checkfail never pass
 test-armhf-armhf-xl-rtds 12 migrate-support-checkfail   never pass
 test-armhf-armhf-xl-rtds 13 saverestore-support-checkfail   never pass

version targeted for testing:
 xen  468a313def4e6b31dfb2514353d5457789714a5b
baseline version:
 xen  2eb074fddbecf40e0cdac5c5fe28fb6c7b5cc371

Last test of basis   103795  2016-12-21 21:38:08 Z   28 days
Testing same since   104251  2017-01-18 09:54:28 Z0 days1 attempts


People who touched revisions under test:
  Andrew Cooper 
  Jan Beulich 
  Kevin Tian 
  Luwei Kang 

jobs:
 build-amd64-xsm  pass
 build-armhf-xsm  pass
 build-i386-xsm   pass
 build-amd64-xtf  pass
 build-amd64  pass
 build-armhf  pass
 build-i386   pass
 build-amd64-libvirt  pass
 build-armhf-libvirt  

[Xen-devel] [xen-unstable-smoke test] 104276: tolerable all pass - PUSHED

[osstest service owner]

flight 104276 xen-unstable-smoke real [real]
http://logs.test-lab.xenproject.org/osstest/logs/104276/

Failures :-/ but no regressions.

Tests which did not succeed, but are not blocking:
 test-amd64-amd64-libvirt 12 migrate-support-checkfail   never pass
 test-armhf-armhf-xl  12 migrate-support-checkfail   never pass
 test-armhf-armhf-xl  13 saverestore-support-checkfail   never pass

version targeted for testing:
 xen  12ec20c732a63f26dc243a847343b8b796c2d88c
baseline version:
 xen  3f50ad8dae7f01df3adbbec7b9ce34b61f13d09c

Last test of basis   104262  2017-01-18 15:13:08 Z0 days
Testing same since   104276  2017-01-18 22:01:19 Z0 days1 attempts


People who touched revisions under test:
  Julien Grall 

jobs:
 build-amd64  pass
 build-armhf  pass
 build-amd64-libvirt  pass
 test-armhf-armhf-xl  pass
 test-amd64-amd64-xl-qemuu-debianhvm-i386 pass
 test-amd64-amd64-libvirt pass



sg-report-flight on osstest.test-lab.xenproject.org
logs: /home/logs/logs
images: /home/logs/images

Logs, config files, etc. are available at
http://logs.test-lab.xenproject.org/osstest/logs

Explanation of these reports, and of osstest in general, is at
http://xenbits.xen.org/gitweb/?p=osstest.git;a=blob;f=README.email;hb=master
http://xenbits.xen.org/gitweb/?p=osstest.git;a=blob;f=README;hb=master

Test harness code can be found at
http://xenbits.xen.org/gitweb?p=osstest.git;a=summary


Pushing revision :

+ branch=xen-unstable-smoke
+ revision=12ec20c732a63f26dc243a847343b8b796c2d88c
+ . ./cri-lock-repos
++ . ./cri-common
+++ . ./cri-getconfig
+++ umask 002
+++ getrepos
 getconfig Repos
 perl -e '
use Osstest;
readglobalconfig();
print $c{"Repos"} or die $!;
'
+++ local repos=/home/osstest/repos
+++ '[' -z /home/osstest/repos ']'
+++ '[' '!' -d /home/osstest/repos ']'
+++ echo /home/osstest/repos
++ repos=/home/osstest/repos
++ repos_lock=/home/osstest/repos/lock
++ '[' x '!=' x/home/osstest/repos/lock ']'
++ OSSTEST_REPOS_LOCK_LOCKED=/home/osstest/repos/lock
++ exec with-lock-ex -w /home/osstest/repos/lock ./ap-push xen-unstable-smoke 
12ec20c732a63f26dc243a847343b8b796c2d88c
+ branch=xen-unstable-smoke
+ revision=12ec20c732a63f26dc243a847343b8b796c2d88c
+ . ./cri-lock-repos
++ . ./cri-common
+++ . ./cri-getconfig
+++ umask 002
+++ getrepos
 getconfig Repos
 perl -e '
use Osstest;
readglobalconfig();
print $c{"Repos"} or die $!;
'
+++ local repos=/home/osstest/repos
+++ '[' -z /home/osstest/repos ']'
+++ '[' '!' -d /home/osstest/repos ']'
+++ echo /home/osstest/repos
++ repos=/home/osstest/repos
++ repos_lock=/home/osstest/repos/lock
++ '[' x/home/osstest/repos/lock '!=' x/home/osstest/repos/lock ']'
+ . ./cri-common
++ . ./cri-getconfig
++ umask 002
+ select_xenbranch
+ case "$branch" in
+ tree=xen
+ xenbranch=xen-unstable-smoke
+ qemuubranch=qemu-upstream-unstable
+ '[' xxen = xlinux ']'
+ linuxbranch=
+ '[' xqemu-upstream-unstable = x ']'
+ select_prevxenbranch
++ ./cri-getprevxenbranch xen-unstable-smoke
+ prevxenbranch=xen-4.8-testing
+ '[' x12ec20c732a63f26dc243a847343b8b796c2d88c = x ']'
+ : tested/2.6.39.x
+ . ./ap-common
++ : osst...@xenbits.xen.org
+++ getconfig OsstestUpstream
+++ perl -e '
use Osstest;
readglobalconfig();
print $c{"OsstestUpstream"} or die $!;
'
++ :
++ : git://xenbits.xen.org/xen.git
++ : osst...@xenbits.xen.org:/home/xen/git/xen.git
++ : git://xenbits.xen.org/qemu-xen-traditional.git
++ : git://git.kernel.org
++ : git://git.kernel.org/pub/scm/linux/kernel/git
++ : git
++ : git://xenbits.xen.org/xtf.git
++ : osst...@xenbits.xen.org:/home/xen/git/xtf.git
++ : git://xenbits.xen.org/xtf.git
++ : git://xenbits.xen.org/libvirt.git
++ : osst...@xenbits.xen.org:/home/xen/git/libvirt.git
++ : git://xenbits.xen.org/libvirt.git
++ : git://xenbits.xen.org/osstest/rumprun.git
++ : git
++ : git://xenbits.xen.org/osstest/rumprun.git
++ : osst...@xenbits.xen.org:/home/xen/git/osstest/rumprun.git
++ : git://git.seabios.org/seabios.git
++ : osst...@xenbits.xen.org:/home/xen/git/osstest/seabios.git
++ : git://xenbits.xen.org/osstest/seabios.git
++ : https://github.com/tianocore/edk2.git
++ : osst...@xenbits.xen.org:/home/xen/git/osstest/ovmf.git
++ : git://xenbits.xen.org/osstest/ovmf.git
++ : git://xenbits.xen.org/osstest/linux-firmware.git
++ : osst...@xenbits.xen.org:/home/osstest/ext/linux-firmware.git
++ : 

Re: [Xen-devel] [PATCH RFC 1/8] golang/xenlight: Create stub package

[Ronald Rojas]

On Wed, Jan 18, 2017 at 11:10:32PM +0100, Dario Faggioli wrote:
> Hey,
> 
> I'm afraid I can't comment on nothing, as I'm not at all into go.
> 
> But there's a thing that I've noticed while skipping the patch out of
> curiosity...
> 
> On Wed, 2017-01-18 at 14:56 -0500, Ronald Rojas wrote:
> > diff --git a/tools/Makefile b/tools/Makefile
> > index 77e0723..fd49e7f 100644
> > --- a/tools/Makefile
> > +++ b/tools/Makefile
> > @@ -6,12 +6,13 @@ SUBDIRS-y += include
> >  SUBDIRS-y += libs
> >  SUBDIRS-y += libxc
> >  SUBDIRS-y += flask
> > -SUBDIRS-y += fuzz
> >
> Why does this needs to be removed?
This was a mistake and should not have been removed. I'll
fix it in the next revision.

Thanks, 
Ronald
> 
> Dario
> -- 
> <> (Raistlin Majere)
> -
> Dario Faggioli, Ph.D, http://about.me/dario.faggioli
> Senior Software Engineer, Citrix Systems R Ltd., Cambridge (UK)



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[Xen-devel] [xen-unstable baseline-only test] 68389: tolerable trouble: blocked/broken

[Platform Team regression test user]

This run is configured for baseline tests only.

flight 68389 xen-unstable real [real]
http://osstest.xs.citrite.net/~osstest/testlogs/logs/68389/

Failures :-/ but no regressions.

Regressions which are regarded as allowable (not blocking):
 build-armhf-xsm   3 host-install(3)   broken baseline untested
 build-armhf   3 host-install(3)   broken baseline untested
 build-armhf-pvops 3 host-install(3)   broken baseline untested
 build-i386-oldkern3 host-install(3)   broken baseline untested
 build-i386-pvops  3 host-install(3)   broken baseline untested
 build-i386-xsm3 host-install(3)   broken baseline untested
 build-i386-prev   3 host-install(3)   broken baseline untested
 build-amd64-xsm   3 host-install(3)   broken baseline untested
 build-amd64-oldkern   3 host-install(3)   broken baseline untested
 build-amd64-xtf   3 host-install(3)   broken baseline untested
 build-amd64-pvops 3 host-install(3)   broken baseline untested
 build-i3863 host-install(3)   broken baseline untested
 build-amd64-prev  3 host-install(3)   broken baseline untested
 build-amd64   3 host-install(3)   broken baseline untested

Tests which did not succeed, but are not blocking:
 test-amd64-amd64-xl-qemuu-debianhvm-amd64  1 build-check(1)blocked n/a
 test-amd64-i386-freebsd10-i386  1 build-check(1)   blocked  n/a
 test-amd64-amd64-qemuu-nested-intel  1 build-check(1)  blocked n/a
 test-amd64-i386-libvirt-qemuu-debianhvm-amd64-xsm 1 build-check(1) blocked n/a
 test-xtf-amd64-amd64-11 build-check(1)   blocked  n/a
 test-armhf-armhf-xl-midway1 build-check(1)   blocked  n/a
 test-armhf-armhf-libvirt  1 build-check(1)   blocked  n/a
 test-amd64-i386-xl-qemuu-debianhvm-amd64-xsm  1 build-check(1) blocked n/a
 test-amd64-i386-xl-qemut-debianhvm-amd64-xsm  1 build-check(1) blocked n/a
 test-amd64-amd64-migrupgrade  1 build-check(1)   blocked  n/a
 test-amd64-amd64-xl-qemut-stubdom-debianhvm-amd64-xsm 1 build-check(1) blocked 
n/a
 test-amd64-i386-xl-qemuu-winxpsp3-vcpus1  1 build-check(1) blocked n/a
 test-armhf-armhf-libvirt-raw  1 build-check(1)   blocked  n/a
 test-amd64-i386-libvirt-xsm   1 build-check(1)   blocked  n/a
 test-amd64-amd64-xl-multivcpu  1 build-check(1)   blocked  n/a
 test-amd64-i386-xl-qemuu-winxpsp3  1 build-check(1)   blocked  n/a
 test-amd64-amd64-libvirt  1 build-check(1)   blocked  n/a
 test-amd64-i386-xl-qemut-winxpsp3  1 build-check(1)   blocked  n/a
 test-amd64-amd64-xl-pvh-amd   1 build-check(1)   blocked  n/a
 test-amd64-i386-xl-qemut-debianhvm-amd64  1 build-check(1) blocked n/a
 test-amd64-i386-qemut-rhel6hvm-intel  1 build-check(1) blocked n/a
 test-amd64-i386-freebsd10-amd64  1 build-check(1)   blocked  n/a
 test-amd64-amd64-pair 1 build-check(1)   blocked  n/a
 test-armhf-armhf-xl-credit2   1 build-check(1)   blocked  n/a
 build-i386-rumprun1 build-check(1)   blocked  n/a
 test-amd64-amd64-xl-qemuu-win7-amd64  1 build-check(1) blocked n/a
 test-amd64-amd64-libvirt-qemuu-debianhvm-amd64-xsm 1 build-check(1) blocked n/a
 test-amd64-amd64-pygrub   1 build-check(1)   blocked  n/a
 test-amd64-amd64-xl-qemuu-winxpsp3  1 build-check(1)   blocked n/a
 test-amd64-amd64-xl-qcow2 1 build-check(1)   blocked  n/a
 test-amd64-amd64-amd64-pvgrub  1 build-check(1)   blocked  n/a
 test-xtf-amd64-amd64-21 build-check(1)   blocked  n/a
 test-amd64-amd64-xl-qemut-win7-amd64  1 build-check(1) blocked n/a
 test-amd64-i386-xl-qemuu-debianhvm-amd64  1 build-check(1) blocked n/a
 test-armhf-armhf-libvirt-xsm  1 build-check(1)   blocked  n/a
 build-amd64-rumprun   1 build-check(1)   blocked  n/a
 build-i386-libvirt1 build-check(1)   blocked  n/a
 test-amd64-i386-xl1 build-check(1)   blocked  n/a
 test-amd64-i386-libvirt-pair  1 build-check(1)   blocked  n/a
 test-xtf-amd64-amd64-41 build-check(1)   blocked  n/a
 test-amd64-amd64-xl-qemuu-ovmf-amd64  1 build-check(1) blocked n/a
 test-amd64-amd64-libvirt-vhd  1 build-check(1)   blocked  n/a
 test-amd64-amd64-xl-credit2   1 build-check(1)   blocked  n/a
 test-armhf-armhf-xl-multivcpu  1 build-check(1)   blocked  n/a
 test-amd64-i386-xl-xsm1 build-check(1)   blocked  n/a
 build-amd64-libvirt   1 build-check(1)   blocked  n/a
 

Re: [Xen-devel] [PATCH] kexec: followup to STATUS patch v3 already in staging

[Daniel Kiper]

On Wed, Jan 18, 2017 at 03:47:26PM -0600, Eric DeVolder wrote:
> This contains the two corrections pointed out by Jan Beulich
> for the kexec STATUS call just introduced.
>
> Note: In kexec_status(), the use of test_bit() can also return
> EPERM, so the return value from test_bit() must be checked to
> ensure that kexec_status() always returns 0, 1 or -1, per the
> public header description.
>
> Note: My handling of the test_bit() scenario is to explicitly
> check for return value of 1, so any value other than 1 causes
> kexec_status to return 0.

One nitpick. Subject should be:

[PATCH v2 0/2] kexec: followup to STATUS patch v3 already in staging

and then following patches should have in subject:

[PATCH v2 1/2] ...
[PATCH v2 2/2] ...

However, IMO regardless of that patches can go in.

Daniel

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Re: [Xen-devel] [PATCH 2/2] kexec: ensure kexec_status() always returns 0 or 1

[Daniel Kiper]

On Wed, Jan 18, 2017 at 03:47:28PM -0600, Eric DeVolder wrote:
> The use of test_bit() can also return EPERM, so the
> return value from test_bit() must be checked to
> ensure that kexec_status() always returns 0, 1 or
> -1, per the public header description.
>
> Signed-off-by: Eric DeVolder 

Reviewed-by: Daniel Kiper 

Daniel

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Re: [Xen-devel] [PATCH 1/2] Put back blank line for readability purposes.

[Daniel Kiper]

On Wed, Jan 18, 2017 at 03:47:27PM -0600, Eric DeVolder wrote:
> This blank line was accidentally removed during
> the insertion of the kexec_status() declarations.
>
> Signed-off-by: Eric DeVolder 

Reviewed-by: Daniel Kiper 

Daniel

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Re: [Xen-devel] [PATCH RFC 2/8] golang/xenlight: Add error constants and standard handling

[Dario Faggioli]

On Wed, 2017-01-18 at 14:56 -0500, Ronald Rojas wrote:
> Create error type Errorxl for throwing proper xenlight
> errors.
> 
> Update Ctx functions to throw Errorxl errors.
> 
> Signed-off-by: Ronald Rojas 
> ---
>  tools/golang/xenlight/xenlight.go | 77
> +--
>  1 file changed, 73 insertions(+), 4 deletions(-)
> 
> diff --git a/tools/golang/xenlight/xenlight.go
> b/tools/golang/xenlight/xenlight.go
> index 1f10e51..d58f8b8 100644
> --- a/tools/golang/xenlight/xenlight.go
> +++ b/tools/golang/xenlight/xenlight.go
> @@ -32,6 +32,77 @@ import (
>  )
>  
>  /*
> + * Errors
> + */
> +type Errorxl int
> +
> +const (
> + ErrorNonspecific  = Errorxl(-
> C.ERROR_NONSPECIFIC)
> + ErrorVersion  = Errorxl(-
> C.ERROR_VERSION)
> + ErrorFail = Errorxl(-C.ERROR_FAIL)
> + ErrorNi   = Errorxl(-C.ERROR_NI)
> + ErrorNomem= Errorxl(-C.ERROR_NOMEM)
> + ErrorInval= Errorxl(-C.ERROR_INVAL)
> + ErrorBadfail  = Errorxl(-
> C.ERROR_BADFAIL)
> + ErrorGuestTimedout= Errorxl(-
> C.ERROR_GUEST_TIMEDOUT)
> + ErrorTimedout = Errorxl(-
> C.ERROR_TIMEDOUT)
> + ErrorNoparavirt   = Errorxl(-
> C.ERROR_NOPARAVIRT)
> + ErrorNotReady = Errorxl(-
> C.ERROR_NOT_READY)
> + ErrorOseventRegFail   = Errorxl(-
> C.ERROR_OSEVENT_REG_FAIL)
> + ErrorBufferfull   = Errorxl(-
> C.ERROR_BUFFERFULL)
> + ErrorUnknownChild = Errorxl(-
> C.ERROR_UNKNOWN_CHILD)
> + ErrorLockFail = Errorxl(-
> C.ERROR_LOCK_FAIL)
> + ErrorJsonConfigEmpty  = Errorxl(-
> C.ERROR_JSON_CONFIG_EMPTY)
> + ErrorDeviceExists = Errorxl(-
> C.ERROR_DEVICE_EXISTS)
> + ErrorCheckpointDevopsDoesNotMatch = Errorxl(-
> C.ERROR_CHECKPOINT_DEVOPS_DOES_NOT_MATCH)
> + ErrorCheckpointDeviceNotSupported = Errorxl(-
> C.ERROR_CHECKPOINT_DEVICE_NOT_SUPPORTED)
> + ErrorVnumaConfigInvalid   = Errorxl(-
> C.ERROR_VNUMA_CONFIG_INVALID)
> + ErrorDomainNotfound   = Errorxl(-
> C.ERROR_DOMAIN_NOTFOUND)
> + ErrorAborted  = Errorxl(-
> C.ERROR_ABORTED)
> + ErrorNotfound = Errorxl(-
> C.ERROR_NOTFOUND)
> + ErrorDomainDestroyed  = Errorxl(-
> C.ERROR_DOMAIN_DESTROYED)
> + ErrorFeatureRemoved   = Errorxl(-
> C.ERROR_FEATURE_REMOVED)
> +)
> +
> +var errors = [...]string{
> + ErrorNonspecific:  "Non-specific error",
> + ErrorVersion:  "Wrong version",
> + ErrorFail: "Failed",
> + ErrorNi:   "Null",
> + ErrorNomem:"No memory",
> + ErrorInval:"Invalid",
> + ErrorBadfail:  "Bad Fail",
> + ErrorGuestTimedout:"Guest timed out",
> + ErrorTimedout: "Timed out",
> + ErrorNoparavirt:   "No Paravirtualization",
> + ErrorNotReady: "Not ready",
> + ErrorOseventRegFail:   "OS event failed",
> + ErrorBufferfull:   "Buffer full",
> + ErrorUnknownChild: "Unknown child",
> + ErrorLockFail: "Lock failed",
> + ErrorJsonConfigEmpty:  "JSON config empyt",
> + ErrorDeviceExists: "Device exists",
> + ErrorCheckpointDevopsDoesNotMatch: "Checkpoint devops does
> not match",
> + ErrorCheckpointDeviceNotSupported: "Checkpoint device not
> supported",
> + ErrorVnumaConfigInvalid:   "VNUMA config invalid",
> + ErrorDomainNotfound:   "Domain not found",
> + ErrorAborted:  "Aborted",
> + ErrorNotfound: "Not found",
> + ErrorDomainDestroyed:  "Domain destroyed",
> + ErrorFeatureRemoved:   "Feature removed",
> +}
> +
> +func (e Errorxl) Error() string {
> + if 0 <= -int(e) && -int(e) < len(errors) {
> + s := errors[-e]
> + if s != "" {
> + return s
> + }
> + }
> + return "errorxl " + strconv.Itoa(int(e))
> +}
> +
> +/*
>   * Types: Builtins
>   */
>  type Context struct {
> @@ -55,8 +126,7 @@ func (Ctx *Context) Open() (err error) {
>   ret := C.libxl_ctx_alloc(unsafe.Pointer(),
> C.LIBXL_VERSION, 0, nil)
>  
>   if ret != 0 {
> - //FIXME: proper error
> - err = createError("Allocating libxl context: ", ret)
> + err = Errorxl(ret)
>
In general, it's not good practise to do something in patch n, and then
undo/redo it in patch n+1 (or in general n+m), within the same series.

Reason is, it makes things 

Re: [Xen-devel] [PATCH RFC 1/8] golang/xenlight: Create stub package

[Dario Faggioli]

Hey,

I'm afraid I can't comment on nothing, as I'm not at all into go.

But there's a thing that I've noticed while skipping the patch out of
curiosity...

On Wed, 2017-01-18 at 14:56 -0500, Ronald Rojas wrote:
> diff --git a/tools/Makefile b/tools/Makefile
> index 77e0723..fd49e7f 100644
> --- a/tools/Makefile
> +++ b/tools/Makefile
> @@ -6,12 +6,13 @@ SUBDIRS-y += include
>  SUBDIRS-y += libs
>  SUBDIRS-y += libxc
>  SUBDIRS-y += flask
> -SUBDIRS-y += fuzz
>
Why does this needs to be removed?

Dario
-- 
<> (Raistlin Majere)
-
Dario Faggioli, Ph.D, http://about.me/dario.faggioli
Senior Software Engineer, Citrix Systems R Ltd., Cambridge (UK)

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[Xen-devel] [PATCH 1/2] Put back blank line for readability purposes.

[Eric DeVolder]

This blank line was accidentally removed during
the insertion of the kexec_status() declarations.

Signed-off-by: Eric DeVolder 
---
 xen/include/public/kexec.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/xen/include/public/kexec.h b/xen/include/public/kexec.h
index c200e8c..74ea981 100644
--- a/xen/include/public/kexec.h
+++ b/xen/include/public/kexec.h
@@ -240,6 +240,7 @@ typedef struct xen_kexec_status {
 uint8_t type;
 } xen_kexec_status_t;
 DEFINE_XEN_GUEST_HANDLE(xen_kexec_status_t);
+
 #else /* __XEN_INTERFACE_VERSION__ < 0x00040400 */
 
 #define KEXEC_CMD_kexec_load KEXEC_CMD_kexec_load_v1
-- 
2.7.4


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[Xen-devel] [PATCH 2/2] kexec: ensure kexec_status() always returns 0 or 1

[Eric DeVolder]

The use of test_bit() can also return EPERM, so the
return value from test_bit() must be checked to
ensure that kexec_status() always returns 0, 1 or
-1, per the public header description.

Signed-off-by: Eric DeVolder 
---
 xen/common/kexec.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/common/kexec.c b/xen/common/kexec.c
index aa808cb..40b76d5 100644
--- a/xen/common/kexec.c
+++ b/xen/common/kexec.c
@@ -1182,7 +1182,7 @@ static int kexec_status(XEN_GUEST_HANDLE_PARAM(void) uarg)
 if ( kexec_load_get_bits(status.type, , ) )
 return -EINVAL;
 
-return test_bit(bit, _flags);
+return (test_bit(bit, _flags) == 1);
 }
 
 static int do_kexec_op_internal(unsigned long op,
-- 
2.7.4


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[Xen-devel] [PATCH] kexec: followup to STATUS patch v3 already in staging

[Eric DeVolder]

This contains the two corrections pointed out by Jan Beulich
for the kexec STATUS call just introduced.

Note: In kexec_status(), the use of test_bit() can also return
EPERM, so the return value from test_bit() must be checked to
ensure that kexec_status() always returns 0, 1 or -1, per the
public header description.

Note: My handling of the test_bit() scenario is to explicitly
check for return value of 1, so any value other than 1 causes
kexec_status to return 0.


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[Xen-devel] [xen-4.7-testing test] 104250: regressions - FAIL

[osstest service owner]

flight 104250 xen-4.7-testing real [real]
http://logs.test-lab.xenproject.org/osstest/logs/104250/

Regressions :-(

Tests which did not succeed and are blocking,
including tests which could not be run:
 test-amd64-amd64-qemuu-nested-amd 13 xen-boot/l1 fail REGR. vs. 103850

Regressions which are regarded as allowable (not blocking):
 test-armhf-armhf-libvirt-xsm 13 saverestore-support-checkfail  like 103850
 test-armhf-armhf-libvirt 13 saverestore-support-checkfail  like 103850
 test-armhf-armhf-libvirt-raw 12 saverestore-support-checkfail  like 103850
 test-amd64-i386-xl-qemuu-win7-amd64 16 guest-stop fail like 103850
 test-amd64-i386-xl-qemut-win7-amd64 16 guest-stop fail like 103850
 test-armhf-armhf-libvirt-qcow2 12 saverestore-support-check   fail like 103850
 test-amd64-amd64-xl-qemuu-win7-amd64 16 guest-stopfail like 103850

Tests which did not succeed, but are not blocking:
 test-amd64-i386-libvirt-xsm  12 migrate-support-checkfail   never pass
 test-amd64-amd64-xl-pvh-intel 11 guest-start  fail  never pass
 test-amd64-amd64-xl-pvh-amd  11 guest-start  fail   never pass
 test-amd64-amd64-libvirt 12 migrate-support-checkfail   never pass
 test-amd64-amd64-libvirt-xsm 12 migrate-support-checkfail   never pass
 test-amd64-amd64-libvirt-qemuu-debianhvm-amd64-xsm 10 migrate-support-check 
fail never pass
 test-amd64-i386-libvirt-qemuu-debianhvm-amd64-xsm 10 migrate-support-check 
fail never pass
 test-amd64-amd64-libvirt-vhd 11 migrate-support-checkfail   never pass
 test-armhf-armhf-xl-xsm  12 migrate-support-checkfail   never pass
 test-armhf-armhf-xl-xsm  13 saverestore-support-checkfail   never pass
 test-armhf-armhf-libvirt-xsm 12 migrate-support-checkfail   never pass
 test-armhf-armhf-xl-credit2  12 migrate-support-checkfail   never pass
 test-armhf-armhf-xl-credit2  13 saverestore-support-checkfail   never pass
 test-armhf-armhf-xl-arndale  12 migrate-support-checkfail   never pass
 test-armhf-armhf-xl-arndale  13 saverestore-support-checkfail   never pass
 test-armhf-armhf-libvirt 12 migrate-support-checkfail   never pass
 test-armhf-armhf-libvirt-raw 11 migrate-support-checkfail   never pass
 test-armhf-armhf-xl-rtds 12 migrate-support-checkfail   never pass
 test-armhf-armhf-xl-rtds 13 saverestore-support-checkfail   never pass
 test-armhf-armhf-xl  12 migrate-support-checkfail   never pass
 test-armhf-armhf-xl  13 saverestore-support-checkfail   never pass
 test-armhf-armhf-xl-cubietruck 12 migrate-support-checkfail never pass
 test-armhf-armhf-xl-cubietruck 13 saverestore-support-checkfail never pass
 test-armhf-armhf-xl-multivcpu 12 migrate-support-checkfail  never pass
 test-armhf-armhf-xl-multivcpu 13 saverestore-support-checkfail  never pass
 test-amd64-amd64-xl-qemut-win7-amd64 16 guest-stop fail never pass
 test-amd64-i386-libvirt  12 migrate-support-checkfail   never pass
 test-armhf-armhf-libvirt-qcow2 11 migrate-support-checkfail never pass
 test-armhf-armhf-xl-vhd  11 migrate-support-checkfail   never pass
 test-armhf-armhf-xl-vhd  12 saverestore-support-checkfail   never pass

version targeted for testing:
 xen  24dc62731cd198d0396135392338abb3d285b18a
baseline version:
 xen  9f3c5553ebf5978992cf02664002570e15ed8ebd

Last test of basis   103850  2016-12-23 14:49:04 Z   26 days
Testing same since   104250  2017-01-18 09:54:01 Z0 days1 attempts


People who touched revisions under test:
  Andrew Cooper 
  Jan Beulich 
  Kevin Tian 
  Luwei Kang 

jobs:
 build-amd64-xsm  pass
 build-armhf-xsm  pass
 build-i386-xsm   pass
 build-amd64-xtf  pass
 build-amd64  pass
 build-armhf  pass
 build-i386   pass
 build-amd64-libvirt  pass
 build-armhf-libvirt  pass
 build-i386-libvirt   pass
 build-amd64-prev pass
 build-i386-prev  pass
 build-amd64-pvopspass
 build-armhf-pvopspass
 build-i386-pvops 

Re: [Xen-devel] [PATCH] xen/arm: gic-v3: Make sure read from ICC_IAR1_EL1 is visible on the redistributor

[Stefano Stabellini]

On Wed, 18 Jan 2017, Julien Grall wrote:
> >From the GICv3 spec (IHI069C) section 4.1.1:
> "The effects of reading ICC_IAR0_EL1 and ICC_IAR1_EL1 on the state of a
> returned INTID are not guaranteed to be visible until after the execution
> of a DSB".
> 
> Because of the GIC is an external component, a dsb sy is required.
> Without it the sysreg read may not have been made visible on the
> redistributor.
> 
> Signed-off-by: Julien Grall 

Reviewed-by: Stefano Stabellini 

> ---
> 
> This patch should be backported up to Xen 4.6.
> ---
>  xen/arch/arm/gic-v3.c | 6 +-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
> index 57ed9d9..955591b 100644
> --- a/xen/arch/arm/gic-v3.c
> +++ b/xen/arch/arm/gic-v3.c
> @@ -459,7 +459,11 @@ static void gicv3_dir_irq(struct irq_desc *irqd)
>  
>  static unsigned int gicv3_read_irq(void)
>  {
> -return READ_SYSREG32(ICC_IAR1_EL1);
> +unsigned int irq = READ_SYSREG32(ICC_IAR1_EL1);
> +
> +dsb(sy);
> +
> +return irq;
>  }
>  
>  static inline uint64_t gicv3_mpidr_to_affinity(int cpu)
> -- 
> 1.9.1
> 

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Re: [Xen-devel] [PATCH v4 5/5] fix: add multiboot2 protocol support for EFI platforms

[Daniel Kiper]

On Wed, Jan 18, 2017 at 07:52:44AM -0700, Jan Beulich wrote:
> >>> On 18.01.17 at 15:17,  wrote:
> > This should be squashed into the 4/4 patch 'x86: add multiboot2 protocol
> > support for EFI platforms'.
> >
> > - fix incorrect assembly (identified by Andrew Cooper)
> > - fix issue where the trampoline size was left as 0 and the
> >   way the memory is allocated for the trampolines we would go to
> >   the end of an available section and then subtract off the size
> >   to decide where to place it. The end result was that we would
> >   always copy the trampolines and the 32-bit stack into some
> >   form of reserved memory after the conventional region we
> >   wanted to put things into. On some systems this did not
> >   manifest as a crash while on others it did. Reworked the
> >   changes to always reserve 64kb for both the stack and the size
> >   of the trampolines. Added a build time assert to make sure we have
> >   enough room always.
> >
> > Signed-off-by: Doug Goldstein 
>
> Reviewed-by: Jan Beulich 
> with ...
>
> > --- a/xen/arch/x86/xen.lds.S
> > +++ b/xen/arch/x86/xen.lds.S
> > @@ -333,3 +333,10 @@ ASSERT(IS_ALIGNED(trampoline_start, 4),
> > "trampoline_start misaligned")
> >  ASSERT(IS_ALIGNED(trampoline_end,   4), "trampoline_end misaligned")
> >  ASSERT(IS_ALIGNED(__bss_start,  8), "__bss_start misaligned")
> >  ASSERT(IS_ALIGNED(__bss_end,8), "__bss_end misaligned")
> > +
> > +/* The trampolines and the low memory stack must fit in 64kb. In testing
> > + * the low memory stack never exceeded 1kb so just require that the
> > + * trampolines fit in 63kb, leaving 1kb for the stack.
> > + */
> > +ASSERT((trampoline_end - trampoline_start) < KB(63),
> > +"not enough room for trampolines and low memory stack")
>
> ... the comment style here fixed (which could be done upon commit
> or when Daniel merges this back into his series).

Hmmm... Why this patch and #0 was not CC-ed to me?

Anyway, it looks that I have cleared my backlog to some extent and now I am
able to take a stab on v12. There is a chance that I will have it with Doug's
and some additional fixes on Friday or Monday.

Daniel

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Re: [Xen-devel] Followup corrections to kexec STATUS patch v3

[Daniel Kiper]

On Wed, Jan 18, 2017 at 12:01:06PM -0600, Eric DeVolder wrote:
> This contains the two corrections pointed out by Jan Beulich
> for the kexec STATUS call just introduced.
>
> Note: In kexec_status(), the use of test_bit() can also return
> EPERM, so the return value from test_bit() must be checked to
> ensure that kexec_status() always returns 0, 1 or -1, per the
> public header description.
>
> Note: My handling of the test_bit() scenario is to explicitly
> check for return value of 1, so any value other than 1 causes
> kexec_status to return 0.

Great, however:
  - please use "git format-patch -n ..." to create patches,
  - first patch in the series should have [PATCH 0/3] in the subject,
  - both patches lack of your SOB.

Daniel

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Re: [Xen-devel] [PATCH 1/2] xen/kbdif: update protocol documentation

[Stefano Stabellini]

On Wed, 18 Jan 2017, Oleksandr Andrushchenko wrote:
> On 01/12/2017 08:36 AM, Oleksandr Andrushchenko wrote:
> > On 01/12/2017 12:50 AM, Dario Faggioli wrote:
> > > On Wed, 2017-01-11 at 20:40 +0200, Oleksandr Andrushchenko wrote:
> > > > On 01/11/2017 07:35 PM, Dario Faggioli wrote:
> > > > >   It's indeed a repetition, but a good one, IMO: it helps the reader,
> > > > > as
> > > > > she won't have to go back to figure out how big the struct was, how
> > > > > the
> > > > > macro was call and to what value it was defined).
> > > > I am still not convinced that we should put it.
> > > > Probably we can go the way other RFCs do, like TCP [1], 802.11 [2]
> > > > etc:
> > > > those do not define any reserved fields at the bottom of structures,
> > > > (which are effectively padding?) but are limited to only those fields
> > > > which are defined.
> > > > 
> > > In principle, I like the idea of following the example of those RFCs.
> > > However, I'd say that what we should value most is consistency within
> > > our own source tree.
> > > 
> > > But, TBH, there aren't many binary diagram already committed in
> > > include/public/io, so it's hard to tell.
> > > 
> > > FWIW, I still think that providing a clue to the reader about the size
> > > --even if already specified somewhere else-- would be beneficial, but
> > > it's a rather minor thing, and I certainly can leave with whatever you
> > > and the maintainer(s) agree upon.
> > fair enough
> > > Regards,
> > > Dario
> > Konrad, could you please define what that ASCII box
> > notation should look like?
> > 
> Stefano, Konrad
> As per my understanding this is the only thing blocking multi-touch
> and updated kbdif protocol from being upgraded/extended )
> Could you please make some decision on this any time soon?

I would use something like:

0 1 2 3
  * +-+-+-+-+ 
  * |   _TYPE_MOTION  |   reserved  |4
  * +-+-+-+-+
  * | rel_x |8
  * +-+-+-+-+
  * | rel_y |12
  * +-+-+-+-+
  * | rel_z |16
  * +-+-+-+-+
  * |   reserved|20
  * +-+-+-+-+
  * |/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/|40
  * +-+-+-+-+

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Re: [Xen-devel] [PATCH v2] xen-netfront: Fix Rx stall during network stress and OOM

[Vineeth Remanan Pillai]

On 01/18/2017 12:10 PM, David Miller wrote:

This v2 never made it into patchwork.  I don't know why, so please resend it to
netdev with the accumulated reviewed-by etc. tags added.

Thanks.

Sorry about that. Will resend as a separate thread right away.

Thanks


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Re: [Xen-devel] [PATCH v2 3/3] xen: optimize xenbus driver for multiple concurrent xenstore accesses

[Boris Ostrovsky]

On 01/16/2017 09:15 AM, Juergen Gross wrote:
> +
> +static uint32_t xs_request_enter(struct xb_req_data *req)
> +{
> + uint32_t rq_id;
> +
> + req->type = req->msg.type;
> +
> + spin_lock(_state_lock);
> + for (;;) {
> + if (req->msg.tx_id != 0)
> + break;
> + if (xs_suspend_active) {
> + spin_unlock(_state_lock);
> + wait_event(xs_state_enter_wq, xs_suspend_active == 0);
> + spin_lock(_state_lock);
> + continue;
> + }
> + if (req->type == XS_TRANSACTION_START)
> + xs_state_users++;
> + break;
> + }
> + xs_state_users++;
> + rq_id = xs_request_id++;
> + spin_unlock(_state_lock);
> +
> + return rq_id;
> +}

I should have noticed this last time but I've been looking at this code
again and I don't think I understand why you are incrementing count for
XS_TRANSACTION_START inside the loop.

In fact, why not just 'while(xs_suspend_active) {}' loop?

-boris


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Re: [Xen-devel] [PATCH v2 0/2] xen-netback: fix memory leaks on XenBus disconnect

[David Miller]

From: Igor Druzhinin 
Date: Tue, 17 Jan 2017 20:49:36 +

> Just split the initial patch in two as proposed by Wei.
> 
> Since the approach for locking netdev statistics is inconsistent (tends not
> to have any locking at all) accross the kernel we'd better to rely on our
> internal lock for this purpose.

Series applied, thanks.

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Re: [Xen-devel] [PATCH v2] xen-netfront: Fix Rx stall during network stress and OOM

[David Miller]

This v2 never made it into patchwork.  I don't know why, so please resend it to
netdev with the accumulated reviewed-by etc. tags added.

Thanks.

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Re: [Xen-devel] [PATCH v2] xen-netfront: Fix Rx stall during network stress and OOM

[David Miller]

From: Vineeth Remanan Pillai 
Date: Wed, 18 Jan 2017 09:02:17 -0800

> 
> On 01/15/2017 10:24 PM, Juergen Gross wrote:
>> On 13/01/17 18:55, Remanan Pillai wrote:
>>> From: Vineeth Remanan Pillai 
>>>
>>> During an OOM scenario, request slots could not be created as skb
>>> allocation fails. So the netback cannot pass in packets and netfront
>>> wrongly assumes that there is no more work to be done and it disables
>>> polling. This causes Rx to stall.
>>>
>>> The issue is with the retry logic which schedules the timer if the
>>> created slots are less than NET_RX_SLOTS_MIN. The count of new request
>>> slots to be pushed are calculated as a difference between new req_prod
>>> and rsp_cons which could be more than the actual slots, if there are
>>> unconsumed responses.
>>>
>>> The fix is to calculate the count of newly created slots as the
>>> difference between new req_prod and old req_prod.
>>>
>>> Signed-off-by: Vineeth Remanan Pillai 
>> Reviewed-by: Juergen Gross 
> Thanks Juergen.
> 
> David,
> 
> Could you please pick up this change for net-next if there no more
> concerns..

Why would I pick up "this change", if the author of the patch has
stated that he will resubmit the change implemented differently based
upon my feedback?

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Re: [Xen-devel] [PATCH v4 4/5] x86: add multiboot2 protocol support for EFI platforms

[Doug Goldstein]

On 1/18/17 2:51 PM, Andrew Cooper wrote:
> On 18/01/17 14:17, Doug Goldstein wrote:
>> diff --git a/xen/arch/x86/boot/head.S b/xen/arch/x86/boot/head.S
>> index d423fd8..ac93df0 100644
>> --- a/xen/arch/x86/boot/head.S
>> +++ b/xen/arch/x86/boot/head.S
>> @@ -89,6 +89,13 @@ multiboot2_header_start:
>> 0, /* Number of the lines - no preference. */ \
>> 0  /* Number of bits per pixel - no preference. */
>>  
>> +/* Inhibit bootloader from calling ExitBootServices(). */
> 
> /* Request that ExitBootServices() not be called. */
> 
> This tag doesn't make any guarantees.
>

Agreed. The multiboot2 spec is clear in that regard. I have tested the
case when the bootloader ignores this and it does work.

>> +.code64
>> +
>> +__efi64_start:
> 
> __mb2_efi64_start:
> 
> This entry point is distinct from the PE efi64 entry point in
> common/efi/boot.c

I agree here as well. It does need one other update however. On line 97.

/* EFI64 entry point. */
mb2ht_init MB2_HT(ENTRY_ADDRESS_EFI64), MB2_HT(OPTIONAL), \
   sym_phys(__efi64_start)

I can reroll the series or if people are comfortable with committing
this then the change can be done then.
-- 
Doug Goldstein



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Re: [Xen-devel] [PATCH v13 3/3] iommu: add rmrr Xen command line option for extra rmrrs

[Elena Ufimtseva]

On Thu, Jan 12, 2017 at 04:44:42AM -0700, Jan Beulich wrote:
> >>> On 10.01.17 at 23:57,  wrote:
> > Changes in v13:
> >  - Implement feedback from Kevin Tian.
> >
> > https://lists.xenproject.org/archives/html/xen-devel/2015-10/msg03169.html 
> >
> > https://lists.xenproject.org/archives/html/xen-devel/2015-10/msg03170.html 
> >
> > https://lists.xenproject.org/archives/html/xen-devel/2015-10/msg03171.html 
> 
> Any reason some of the review comments I had given were left
> un-addressed? I'll reproduce them in quotes below.
>

Hi Jan

Thanks for reminding!
That was my fault that I did not tell this to Venu when transferring
this patchset to him.
 
> > --- a/xen/drivers/passthrough/vtd/dmar.c
> > +++ b/xen/drivers/passthrough/vtd/dmar.c
> > @@ -859,6 +859,132 @@ out:
> >  return ret;
> >  }
> >  
> > +#define MAX_EXTRA_RMRR_PAGES 16
> > +#define MAX_EXTRA_RMRR 10
> > +
> > +/* RMRR units derived from command line rmrr option. */
> > +#define MAX_EXTRA_RMRR_DEV 20
> 
> So you've kept "extra" in these, but ...
> 
> > +struct user_rmrr {
> 
> ... switched to "user" here and below. Please be consistent.
> 
> > +static int __init add_user_rmrr(void)
> > +{
> > +struct acpi_rmrr_unit *rmrr, *rmrru;
> > +unsigned int idx, seg, i;
> > +unsigned long base, end;
> > +bool overlap;
> > +
> > +for ( i = 0; i < nr_rmrr; i++ )
> > +{
> > +base = user_rmrrs[i].base_pfn;
> > +end = user_rmrrs[i].end_pfn;
> > +
> > +if ( base > end )
> > +{
> > +printk(XENLOG_ERR VTDPREFIX
> > +   "Invalid RMRR Range "ERMRRU_FMT"\n",
> > +   ERMRRU_ARG(user_rmrrs[i]));
> > +continue;
> > +}
> > +
> > +if ( (end - base) >= MAX_EXTRA_RMRR_PAGES )
> > +{
> > +printk(XENLOG_ERR VTDPREFIX
> > +   "RMRR range "ERMRRU_FMT" exceeds "\
> > +   __stringify(MAX_EXTRA_RMRR_PAGES)" pages\n",
> > +   ERMRRU_ARG(user_rmrrs[i]));
> > +continue;
> > +}
> > +
> > +overlap = false;
> > +list_for_each_entry(rmrru, _rmrr_units, list)
> > +{
> > +if ( pfn_to_paddr(base) < rmrru->end_address &&
> > + rmrru->base_address < pfn_to_paddr(end + 1) )
> 
> "Aren't both ranges inclusive? I.e. shouldn't the first one be <= (and
>  the second one could be <= too when dropping the +1), matching
>  the check acpi_parse_one_rmrr() does?"

I agree. The ranges in acpu_rmrr_units and user_rmrrs are inclusive.
If this is fixed, then there is another part where I am not sure what
would be the better way to fix this. If fix is needed.

I am looking at rmrr_identity_mapping where the RMRR paddr get converted
to pfn and then mapped with iommu.
If ( rmrr->end_address & ~PAGE_SHIFT_MASK_4K ) == 0, the while loop
while ( base_pfn < end_pfn )
 will not map that inclusive end_address of rmrr.
Does it seem wrong?


> 
> > +{
> > +printk(XENLOG_ERR VTDPREFIX
> > +   "Overlapping RMRRs: "ERMRRU_FMT" and [%lx-%lx]\n",
> > +   ERMRRU_ARG(user_rmrrs[i]),
> > +   paddr_to_pfn(rmrru->base_address),
> > +   paddr_to_pfn(rmrru->end_address));
> > +overlap = true;
> > +break;
> > +}
> > +}
> > +/* Don't add overlapping RMRR. */
> > +if ( overlap )
> > +continue;
> > +
> > +do
> > +{
> > +if ( !mfn_valid(base) )
> > +{
> > +printk(XENLOG_ERR VTDPREFIX
> > +   "Invalid pfn in RMRR range "ERMRRU_FMT"\n",
> > +   ERMRRU_ARG(user_rmrrs[i]));
> > +break;
> > +}
> > +} while ( base++ < end );
> > +
> > +/* Invalid pfn in range as the loop ended before end_pfn was 
> > reached. */
> > +if ( base <= end )
> > +continue;
> > +
> > +rmrr = xzalloc(struct acpi_rmrr_unit);
> > +if ( !rmrr )
> > +return -ENOMEM;
> > +
> > +rmrr->scope.devices = xmalloc_array(u16, user_rmrrs[i].dev_count);
> > +if ( !rmrr->scope.devices )
> > +{
> > +xfree(rmrr);
> > +return -ENOMEM;
> > +}
> > +
> > +seg = 0;
> > +for ( idx = 0; idx < user_rmrrs[i].dev_count; idx++ )
> > +{
> > +rmrr->scope.devices[idx] = user_rmrrs[i].sbdf[idx];
> > +seg |= PCI_SEG(user_rmrrs[i].sbdf[idx]);
> > +}
> > +if ( seg != PCI_SEG(user_rmrrs[i].sbdf[0]) )
> > +{
> > +printk(XENLOG_ERR VTDPREFIX
> > +   "Segments are not equal for RMRR range "ERMRRU_FMT"\n",
> > +   ERMRRU_ARG(user_rmrrs[i]));
> > +scope_devices_free(>scope);
> > +xfree(rmrr);
> > +continue;
> > +

[Xen-devel] [PATCH RFC 6/8] tools/xenlight: Implement libxl_scheduler enumeration

[Ronald Rojas]

Include both constants and a Stringification for libxl_scheduler.

Signed-off-by: George Dunlap 
Signed-off-by: Ronald Rojas 
---
 tools/golang/xenlight/xenlight.go | 72 +++
 1 file changed, 72 insertions(+)

diff --git a/tools/golang/xenlight/xenlight.go 
b/tools/golang/xenlight/xenlight.go
index 8aaca6a..64e867a 100644
--- a/tools/golang/xenlight/xenlight.go
+++ b/tools/golang/xenlight/xenlight.go
@@ -211,6 +211,78 @@ type Dominfo struct {
 
 }
 
+// # Consistent with values defined in domctl.h
+// # Except unknown which we have made up
+// libxl_scheduler = Enumeration("scheduler", [
+// (0, "unknown"),
+// (4, "sedf"),
+// (5, "credit"),
+// (6, "credit2"),
+// (7, "arinc653"),
+// (8, "rtds"),
+// ])
+type Scheduler int
+
+var (
+   SchedulerUnknown  Scheduler = C.LIBXL_SCHEDULER_UNKNOWN
+   SchedulerSedf Scheduler = C.LIBXL_SCHEDULER_SEDF
+   SchedulerCredit   Scheduler = C.LIBXL_SCHEDULER_CREDIT
+   SchedulerCredit2  Scheduler = C.LIBXL_SCHEDULER_CREDIT2
+   SchedulerArinc653 Scheduler = C.LIBXL_SCHEDULER_ARINC653
+   SchedulerRTDS Scheduler = C.LIBXL_SCHEDULER_RTDS
+)
+
+// const char *libxl_scheduler_to_string(libxl_scheduler p);
+func (s Scheduler) String() string {
+   cs := C.libxl_scheduler_to_string(C.libxl_scheduler(s))
+   // No need to free const return value
+
+   return C.GoString(cs)
+}
+
+// int libxl_scheduler_from_string(const char *s, libxl_scheduler *e);
+func (s *Scheduler) FromString(gstr string) (err error) {
+   cstr := C.CString(gstr)
+   defer C.free(unsafe.Pointer(cstr))
+
+   var cs C.libxl_scheduler
+   ret := C.libxl_scheduler_from_string(cstr, )
+   if ret != 0 {
+   err = Errorxl(ret)
+   return
+   }
+
+   *s = Scheduler(cs)
+   return
+}
+
+func translateCpupoolInfoCToGo(cci C.libxl_cpupoolinfo) (gci CpupoolInfo) {
+   gci.Poolid = uint32(cci.poolid)
+   gci.PoolName = C.GoString(cci.pool_name)
+   gci.Scheduler = Scheduler(cci.sched)
+   gci.DomainCount = int(cci.n_dom)
+   gci.Cpumap = bitmapCToGo(cci.cpumap)
+
+   return
+}
+
+func SchedulerFromString(name string) (s Scheduler, err error) {
+   cname := C.CString(name)
+   defer C.free(unsafe.Pointer(cname))
+
+   var cs C.libxl_scheduler
+
+   ret := C.libxl_scheduler_from_string(cname, )
+   if ret != 0 {
+   err = Errorxl(ret)
+   return
+   }
+
+   s = Scheduler(cs)
+
+   return
+}
+
 /*
  * Bitmap operations
  */
-- 
2.7.4


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[Xen-devel] [PATCH RFC 2/8] golang/xenlight: Add error constants and standard handling

[Ronald Rojas]

Create error type Errorxl for throwing proper xenlight
errors.

Update Ctx functions to throw Errorxl errors.

Signed-off-by: Ronald Rojas 
---
 tools/golang/xenlight/xenlight.go | 77 +--
 1 file changed, 73 insertions(+), 4 deletions(-)

diff --git a/tools/golang/xenlight/xenlight.go 
b/tools/golang/xenlight/xenlight.go
index 1f10e51..d58f8b8 100644
--- a/tools/golang/xenlight/xenlight.go
+++ b/tools/golang/xenlight/xenlight.go
@@ -32,6 +32,77 @@ import (
 )
 
 /*
+ * Errors
+ */
+type Errorxl int
+
+const (
+   ErrorNonspecific  = Errorxl(-C.ERROR_NONSPECIFIC)
+   ErrorVersion  = Errorxl(-C.ERROR_VERSION)
+   ErrorFail = Errorxl(-C.ERROR_FAIL)
+   ErrorNi   = Errorxl(-C.ERROR_NI)
+   ErrorNomem= Errorxl(-C.ERROR_NOMEM)
+   ErrorInval= Errorxl(-C.ERROR_INVAL)
+   ErrorBadfail  = Errorxl(-C.ERROR_BADFAIL)
+   ErrorGuestTimedout= Errorxl(-C.ERROR_GUEST_TIMEDOUT)
+   ErrorTimedout = Errorxl(-C.ERROR_TIMEDOUT)
+   ErrorNoparavirt   = Errorxl(-C.ERROR_NOPARAVIRT)
+   ErrorNotReady = Errorxl(-C.ERROR_NOT_READY)
+   ErrorOseventRegFail   = Errorxl(-C.ERROR_OSEVENT_REG_FAIL)
+   ErrorBufferfull   = Errorxl(-C.ERROR_BUFFERFULL)
+   ErrorUnknownChild = Errorxl(-C.ERROR_UNKNOWN_CHILD)
+   ErrorLockFail = Errorxl(-C.ERROR_LOCK_FAIL)
+   ErrorJsonConfigEmpty  = Errorxl(-C.ERROR_JSON_CONFIG_EMPTY)
+   ErrorDeviceExists = Errorxl(-C.ERROR_DEVICE_EXISTS)
+   ErrorCheckpointDevopsDoesNotMatch = 
Errorxl(-C.ERROR_CHECKPOINT_DEVOPS_DOES_NOT_MATCH)
+   ErrorCheckpointDeviceNotSupported = 
Errorxl(-C.ERROR_CHECKPOINT_DEVICE_NOT_SUPPORTED)
+   ErrorVnumaConfigInvalid   = 
Errorxl(-C.ERROR_VNUMA_CONFIG_INVALID)
+   ErrorDomainNotfound   = Errorxl(-C.ERROR_DOMAIN_NOTFOUND)
+   ErrorAborted  = Errorxl(-C.ERROR_ABORTED)
+   ErrorNotfound = Errorxl(-C.ERROR_NOTFOUND)
+   ErrorDomainDestroyed  = Errorxl(-C.ERROR_DOMAIN_DESTROYED)
+   ErrorFeatureRemoved   = Errorxl(-C.ERROR_FEATURE_REMOVED)
+)
+
+var errors = [...]string{
+   ErrorNonspecific:  "Non-specific error",
+   ErrorVersion:  "Wrong version",
+   ErrorFail: "Failed",
+   ErrorNi:   "Null",
+   ErrorNomem:"No memory",
+   ErrorInval:"Invalid",
+   ErrorBadfail:  "Bad Fail",
+   ErrorGuestTimedout:"Guest timed out",
+   ErrorTimedout: "Timed out",
+   ErrorNoparavirt:   "No Paravirtualization",
+   ErrorNotReady: "Not ready",
+   ErrorOseventRegFail:   "OS event failed",
+   ErrorBufferfull:   "Buffer full",
+   ErrorUnknownChild: "Unknown child",
+   ErrorLockFail: "Lock failed",
+   ErrorJsonConfigEmpty:  "JSON config empyt",
+   ErrorDeviceExists: "Device exists",
+   ErrorCheckpointDevopsDoesNotMatch: "Checkpoint devops does not match",
+   ErrorCheckpointDeviceNotSupported: "Checkpoint device not supported",
+   ErrorVnumaConfigInvalid:   "VNUMA config invalid",
+   ErrorDomainNotfound:   "Domain not found",
+   ErrorAborted:  "Aborted",
+   ErrorNotfound: "Not found",
+   ErrorDomainDestroyed:  "Domain destroyed",
+   ErrorFeatureRemoved:   "Feature removed",
+}
+
+func (e Errorxl) Error() string {
+   if 0 <= -int(e) && -int(e) < len(errors) {
+   s := errors[-e]
+   if s != "" {
+   return s
+   }
+   }
+   return "errorxl " + strconv.Itoa(int(e))
+}
+
+/*
  * Types: Builtins
  */
 type Context struct {
@@ -55,8 +126,7 @@ func (Ctx *Context) Open() (err error) {
ret := C.libxl_ctx_alloc(unsafe.Pointer(), C.LIBXL_VERSION, 0, 
nil)
 
if ret != 0 {
-   //FIXME: proper error
-   err = createError("Allocating libxl context: ", ret)
+   err = Errorxl(ret)
}
return
 }
@@ -66,8 +136,7 @@ func (Ctx *Context) Close() (err error) {
Ctx.ctx = nil
 
if ret != 0 {
-   //FIXME: proper error
-   err = createError("Freeing libxl context: ", ret)
+   err = Errorxl(ret)
}
return
 }
-- 
2.7.4


___

[Xen-devel] [PATCH RFC 1/8] golang/xenlight: Create stub package

[Ronald Rojas]

Create a basic Makefile to build and install libxenlight Golang
bindings. Also add a stub package which only opens libxl context.

Include a global xenlight.Ctx variable which can be used as the
default context by the entire program if desired.

For now, return simple errors. Proper error handling will be
added in next patch.

Signed-off-by: Ronald Rojas 
---
 tools/Makefile| 15 +++-
 tools/golang/xenlight/Makefile| 29 ++
 tools/golang/xenlight/xenlight.go | 80 +++
 3 files changed, 123 insertions(+), 1 deletion(-)
 create mode 100644 tools/golang/xenlight/Makefile
 create mode 100644 tools/golang/xenlight/xenlight.go

diff --git a/tools/Makefile b/tools/Makefile
index 77e0723..fd49e7f 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -6,12 +6,13 @@ SUBDIRS-y += include
 SUBDIRS-y += libs
 SUBDIRS-y += libxc
 SUBDIRS-y += flask
-SUBDIRS-y += fuzz
 SUBDIRS-y += xenstore
 SUBDIRS-y += misc
 SUBDIRS-y += examples
 SUBDIRS-y += hotplug
 SUBDIRS-y += xentrace
+#Uncomment line to build Golang libxl
+#SUBDIRS-y += golang/xenlight
 SUBDIRS-$(CONFIG_XCUTILS) += xcutils
 SUBDIRS-$(CONFIG_X86) += firmware
 SUBDIRS-y += console
@@ -322,6 +323,18 @@ subdir-install-debugger/kdd: .phony
 subdir-all-debugger/kdd: .phony
$(MAKE) -C debugger/kdd all
 
+subdir-clean-golang/xenlight: .phony
+   $(MAKE) -C golang/xenlight clean
+
+subdir-distclean-golang/xenlight: .phony
+   $(MAKE) -C golang/xenlight distclean
+
+subdir-install-golang/xenlight: .phony
+   $(MAKE) -C golang/xenlight install
+
+subdir-all-golang/xenlight: .phony
+   $(MAKE) -C golang/xenlight all
+
 subdir-distclean-firmware: .phony
$(MAKE) -C firmware distclean
 
diff --git a/tools/golang/xenlight/Makefile b/tools/golang/xenlight/Makefile
new file mode 100644
index 000..a45336b
--- /dev/null
+++ b/tools/golang/xenlight/Makefile
@@ -0,0 +1,29 @@
+XEN_ROOT=$(CURDIR)/../../..
+include $(XEN_ROOT)/tools/Rules.mk
+
+BINARY = xenlightgo
+GO = go
+
+.PHONY: all
+all: build
+
+.PHONY: build
+build: xenlight
+
+.PHONY: install
+install: build
+   ! [ -f $(BINARY) ] || $(INSTALL_PROG) xenlight.go $(DESTDIR)$(bindir)
+
+.PHONY: clean
+clean:
+   $(RM) $(BINARY)
+
+.PHONY: distclean
+distclean: clean
+
+
+xenlight: xenlight.go
+   $(GO) build -o $(BINARY) xenlight.go
+
+
+-include $(DEPS)
diff --git a/tools/golang/xenlight/xenlight.go 
b/tools/golang/xenlight/xenlight.go
new file mode 100644
index 000..1f10e51
--- /dev/null
+++ b/tools/golang/xenlight/xenlight.go
@@ -0,0 +1,80 @@
+/*
+ * Copyright (C) 2016 George W. Dunlap, Citrix Systems UK Ltd
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the
+ * License only.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+package xenlight
+
+/*
+#cgo LDFLAGS: -lxenlight -lyajl
+#include 
+#include 
+*/
+import "C"
+
+import (
+   "fmt"
+   "time"
+   "unsafe"
+)
+
+/*
+ * Types: Builtins
+ */
+type Context struct {
+   ctx *C.libxl_ctx
+}
+
+/*
+ * Context
+ */
+var Ctx Context
+
+func (Ctx *Context) IsOpen() bool {
+   return Ctx.ctx != nil
+}
+
+func (Ctx *Context) Open() (err error) {
+   if Ctx.ctx != nil {
+   return
+   }
+
+   ret := C.libxl_ctx_alloc(unsafe.Pointer(), C.LIBXL_VERSION, 0, 
nil)
+
+   if ret != 0 {
+   //FIXME: proper error
+   err = createError("Allocating libxl context: ", ret)
+   }
+   return
+}
+
+func (Ctx *Context) Close() (err error) {
+   ret := C.libxl_ctx_free(unsafe.Pointer(Ctx.ctx))
+   Ctx.ctx = nil
+
+   if ret != 0 {
+   //FIXME: proper error
+   err = createError("Freeing libxl context: ", ret)
+   }
+   return
+}
+
+func (Ctx *Context) CheckOpen() (err error) {
+   if Ctx.ctx == nil {
+   err = fmt.Errorf("Context not opened")
+   }
+   return
+}
-- 
2.7.4


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[Xen-devel] [PATCH RFC 5/8] golang/xenlight: Implement libxl_bitmap and helper operations

[Ronald Rojas]

Implement Bitmap type, along with helper functions.

The Bitmap type is implemented interllay in a way which makes it
easy to copy into and out of the C libxl_bitmap type.

Signed-off-by: George Dunlap 
Signed-off-by: Ronald Rojas 
---
 tools/golang/xenlight/xenlight.go | 167 ++
 1 file changed, 167 insertions(+)

diff --git a/tools/golang/xenlight/xenlight.go 
b/tools/golang/xenlight/xenlight.go
index 1e25413..8aaca6a 100644
--- a/tools/golang/xenlight/xenlight.go
+++ b/tools/golang/xenlight/xenlight.go
@@ -131,6 +131,20 @@ func hwcapCToGo(chwcap C.libxl_hwcap) (ghwcap Hwcap) {
return
 }
 
+// typedef struct {
+// uint32_t size;  /* number of bytes in map */
+// uint8_t *map;
+// } libxl_bitmap;
+
+// Implement the Go bitmap type such that the underlying data can
+// easily be copied in and out.  NB that we still have to do copies
+// both directions, because cgo runtime restrictions forbid passing to
+// a C function a pointer to a Go-allocated structure which contains a
+// pointer.
+type Bitmap struct {
+   bitmap []C.uint8_t
+}
+
 /*
  * Types: IDL
  *
@@ -198,6 +212,159 @@ type Dominfo struct {
 }
 
 /*
+ * Bitmap operations
+ */
+
+// Return a Go bitmap which is a copy of the referred C bitmap.
+func bitmapCToGo(cbm C.libxl_bitmap) (gbm Bitmap) {
+   // Alloc a Go slice for the bytes
+   size := int(cbm.size)
+   gbm.bitmap = make([]C.uint8_t, size)
+
+   // Make a slice pointing to the C array
+   mapslice := (*[1 << 30]C.uint8_t)(unsafe.Pointer(cbm._map))[:size:size]
+
+   // And copy the C array into the Go array
+   copy(gbm.bitmap, mapslice)
+
+   return
+}
+
+// Must be C.libxl_bitmap_dispose'd of afterwards
+func bitmapGotoC(gbm Bitmap) (cbm C.libxl_bitmap) {
+   C.libxl_bitmap_init()
+
+   size := len(gbm.bitmap)
+   cbm._map = (*C.uint8_t)(C.malloc(C.size_t(size)))
+   cbm.size = C.uint32_t(size)
+   if cbm._map == nil {
+   panic("C.calloc failed!")
+   }
+
+   // Make a slice pointing to the C array
+   mapslice := (*[1 << 30]C.uint8_t)(unsafe.Pointer(cbm._map))[:size:size]
+
+   // And copy the Go array into the C array
+   copy(mapslice, gbm.bitmap)
+
+   return
+}
+
+func (bm *Bitmap) Test(bit int) bool {
+   ubit := uint(bit)
+   if bit > bm.Max() || bm.bitmap == nil {
+   return false
+   }
+
+   return (bm.bitmap[bit/8] & (1 << (ubit & 7))) != 0
+}
+
+func (bm *Bitmap) Set(bit int) {
+   ibit := bit / 8
+   if ibit+1 > len(bm.bitmap) {
+   bm.bitmap = append(bm.bitmap, make([]C.uint8_t, 
ibit+1-len(bm.bitmap))...)
+   }
+
+   bm.bitmap[ibit] |= 1 << (uint(bit) & 7)
+}
+
+func (bm *Bitmap) SetRange(start int, end int) {
+   for i := start; i <= end; i++ {
+   bm.Set(i)
+   }
+}
+
+func (bm *Bitmap) Clear(bit int) {
+   ubit := uint(bit)
+   if bit > bm.Max() || bm.bitmap == nil {
+   return
+   }
+
+   bm.bitmap[bit/8] &= ^(1 << (ubit & 7))
+}
+
+func (bm *Bitmap) ClearRange(start int, end int) {
+   for i := start; i <= end; i++ {
+   bm.Clear(i)
+   }
+}
+
+func (bm *Bitmap) Max() int {
+   return len(bm.bitmap)*8 - 1
+}
+
+func (bm *Bitmap) IsEmpty() bool {
+   for i := 0; i < len(bm.bitmap); i++ {
+   if bm.bitmap[i] != 0 {
+   return false
+   }
+   }
+   return true
+}
+
+func (a Bitmap) And(b Bitmap) (c Bitmap) {
+   var max, min int
+   if len(a.bitmap) > len(b.bitmap) {
+   max = len(a.bitmap)
+   min = len(b.bitmap)
+   } else {
+   max = len(b.bitmap)
+   min = len(a.bitmap)
+   }
+   c.bitmap = make([]C.uint8_t, max)
+
+   for i := 0; i < min; i++ {
+   c.bitmap[i] = a.bitmap[i] & b.bitmap[i]
+   }
+   return
+}
+
+func (bm Bitmap) String() (s string) {
+   lastOnline := false
+   crange := false
+   printed := false
+   var i int
+   /// --x-x-x -> 2,4-8,10
+   /// --x-xxx -> 2,4-10
+   for i = 0; i <= bm.Max(); i++ {
+   if bm.Test(i) {
+   if !lastOnline {
+   // Switching offline -> online, print this cpu
+   if printed {
+   s += ","
+   }
+   s += fmt.Sprintf("%d", i)
+   printed = true
+   } else if !crange {
+   // last was online, but we're not in a range; 
print -
+   crange = true
+   s += "-"
+   } else {
+   // last was online, we're in a range,  nothing 
else to do
+   }
+

[Xen-devel] [PATCH RFC 4/8] golang/xenlight: Implement libxl_domain_info and libxl_domain_unpause

[Ronald Rojas]

Add calls for the following host-related functionality:
- libxl_domain_info
- libxl_domain_unpause

Include Golang version for the libxl_domain_info as
DomainInfo.

Signed-off-by: George Dunlap 
Signed-off-by: Ronald Rojas 
---
 tools/golang/xenlight/xenlight.go | 91 +++
 1 file changed, 91 insertions(+)

diff --git a/tools/golang/xenlight/xenlight.go 
b/tools/golang/xenlight/xenlight.go
index 6b04850..1e25413 100644
--- a/tools/golang/xenlight/xenlight.go
+++ b/tools/golang/xenlight/xenlight.go
@@ -105,6 +105,12 @@ func (e Errorxl) Error() string {
 /*
  * Types: Builtins
  */
+type Domid uint32
+
+type MemKB uint64
+
+type Uuid C.libxl_uuid
+
 type Context struct {
ctx *C.libxl_ctx
 }
@@ -165,6 +171,32 @@ type VersionInfo struct {
BuildId string
 }
 
+type Dominfo struct {
+   Uuid  Uuid
+   Domid Domid
+   Ssidref   uint32
+   SsidLabel string
+   Running   bool
+   Blocked   bool
+   Pausedbool
+   Shutdown  bool
+   Dying bool
+   NeverStop bool
+
+   ShutdownReason   int32 // FIXME shutdown_reason enumeration
+   OutstandingMemkb MemKB
+   CurrentMemkb MemKB
+   SharedMemkb  MemKB
+   PagedMemkb   MemKB
+   MaxMemkb MemKB
+   CpuTime  time.Duration
+   VcpuMaxIduint32
+   VcpuOnline   uint32
+   Cpupool  uint32
+   DomainType   int32 //FIXME libxl_domain_type enumeration
+
+}
+
 /*
  * Context
  */
@@ -332,3 +364,62 @@ func (Ctx *Context) GetVersionInfo() (info *VersionInfo, 
err error) {
 
return
 }
+
+func (Ctx *Context) DomainInfo(Id Domid) (di *Dominfo, err error) {
+   err = Ctx.CheckOpen()
+   if err != nil {
+   return
+   }
+
+   var cdi C.libxl_dominfo
+
+   ret := C.libxl_domain_info(Ctx.ctx, unsafe.Pointer(), 
C.uint32_t(Id))
+
+   if ret != 0 {
+   err = Errorxl(ret)
+   return
+   }
+
+   // We could consider having this boilerplate generated by the
+   // idl, in a function like this:
+   //
+   // di = translateCdomaininfoToGoDomaininfo(cdi)
+   di = {}
+   di.Uuid = Uuid(cdi.uuid)
+   di.Domid = Domid(cdi.domid)
+   di.Ssidref = uint32(cdi.ssidref)
+   di.SsidLabel = C.GoString(cdi.ssid_label)
+   di.Running = bool(cdi.running)
+   di.Blocked = bool(cdi.blocked)
+   di.Paused = bool(cdi.paused)
+   di.Shutdown = bool(cdi.shutdown)
+   di.Dying = bool(cdi.dying)
+   di.NeverStop = bool(cdi.never_stop)
+   di.ShutdownReason = int32(cdi.shutdown_reason)
+   di.OutstandingMemkb = MemKB(cdi.outstanding_memkb)
+   di.CurrentMemkb = MemKB(cdi.current_memkb)
+   di.SharedMemkb = MemKB(cdi.shared_memkb)
+   di.PagedMemkb = MemKB(cdi.paged_memkb)
+   di.MaxMemkb = MemKB(cdi.max_memkb)
+   di.CpuTime = time.Duration(cdi.cpu_time)
+   di.VcpuMaxId = uint32(cdi.vcpu_max_id)
+   di.VcpuOnline = uint32(cdi.vcpu_online)
+   di.Cpupool = uint32(cdi.cpupool)
+   di.DomainType = int32(cdi.domain_type)
+
+   return
+}
+
+func (Ctx *Context) DomainUnpause(Id Domid) (err error) {
+   err = Ctx.CheckOpen()
+   if err != nil {
+   return
+   }
+
+   ret := C.libxl_domain_unpause(Ctx.ctx, C.uint32_t(Id))
+
+   if ret != 0 {
+   err = Errorxl(ret)
+   }
+   return
+}
-- 
2.7.4


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Re: [Xen-devel] [PATCH v4 5/5] fix: add multiboot2 protocol support for EFI platforms

[Andrew Cooper]

On 18/01/17 14:17, Doug Goldstein wrote:
> This should be squashed into the 4/4 patch 'x86: add multiboot2 protocol
> support for EFI platforms'.
>
> - fix incorrect assembly (identified by Andrew Cooper)
> - fix issue where the trampoline size was left as 0 and the
>   way the memory is allocated for the trampolines we would go to
>   the end of an available section and then subtract off the size
>   to decide where to place it. The end result was that we would
>   always copy the trampolines and the 32-bit stack into some
>   form of reserved memory after the conventional region we
>   wanted to put things into. On some systems this did not
>   manifest as a crash while on others it did. Reworked the
>   changes to always reserve 64kb for both the stack and the size
>   of the trampolines. Added a build time assert to make sure we have
>   enough room always.
>
> Signed-off-by: Doug Goldstein 

LGTM, but this really does want squashing.

~Andrew

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Re: [Xen-devel] [PATCH v4 4/5] x86: add multiboot2 protocol support for EFI platforms

[Andrew Cooper]

On 18/01/17 14:17, Doug Goldstein wrote:
> diff --git a/xen/arch/x86/boot/head.S b/xen/arch/x86/boot/head.S
> index d423fd8..ac93df0 100644
> --- a/xen/arch/x86/boot/head.S
> +++ b/xen/arch/x86/boot/head.S
> @@ -89,6 +89,13 @@ multiboot2_header_start:
> 0, /* Number of the lines - no preference. */ \
> 0  /* Number of bits per pixel - no preference. */
>  
> +/* Inhibit bootloader from calling ExitBootServices(). */

/* Request that ExitBootServices() not be called. */

This tag doesn't make any guarantees.

> +.code64
> +
> +__efi64_start:

__mb2_efi64_start:

This entry point is distinct from the PE efi64 entry point in
common/efi/boot.c

> +cld
> +
> +/* VGA is not available on EFI platforms. */
> +movl   $0,vga_text_buffer(%rip)
> +
> +/* Check for Multiboot2 bootloader. */
> +cmp $MULTIBOOT2_BOOTLOADER_MAGIC,%eax
> +je  .Lefi_multiboot2_proto
> +
> +/* Jump to not_multiboot after switching CPU to x86_32 mode. */
> +lea not_multiboot(%rip),%edi
> +jmp x86_32_switch
> +
> +.Lefi_multiboot2_proto:
> +/* Zero EFI SystemTable and EFI ImageHandle addresses. */
> +xor %esi,%esi
> +xor %edi,%edi
> +
> +/* Skip Multiboot2 information fixed part. */
> +lea (MB2_fixed_sizeof+MULTIBOOT2_TAG_ALIGN-1)(%rbx),%ecx
> +and $~(MULTIBOOT2_TAG_ALIGN-1),%ecx

Are we strictly guaranteed to have the entire image, including multiboot
tags, loaded below 4GB virtual even in the 64bit case? Even on non-EFI
capable grub2's ?

~Andrew

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[Xen-devel] [PATCH 2/6] x86/cpuid: Remove BUG_ON() condition from guest_cpuid()

[Andrew Cooper]

Include a min() against the appropriate ARRAY_SIZE(), and ASSERT() that
max_subleaf is within ARRAY_SIZE().

This is more robust to unexpected problems in a release build of Xen.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
---
 xen/arch/x86/cpuid.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/xen/arch/x86/cpuid.c b/xen/arch/x86/cpuid.c
index 7b9af1b..076fab3 100644
--- a/xen/arch/x86/cpuid.c
+++ b/xen/arch/x86/cpuid.c
@@ -856,10 +856,11 @@ void guest_cpuid(const struct vcpu *v, uint32_t leaf,
 switch ( leaf )
 {
 case 0x7:
-if ( subleaf > p->feat.max_subleaf )
+ASSERT(p->feat.max_subleaf < ARRAY_SIZE(p->feat.raw));
+if ( subleaf > min_t(uint32_t, p->feat.max_subleaf,
+ ARRAY_SIZE(p->feat.raw) - 1) )
 return;
 
-BUG_ON(subleaf >= ARRAY_SIZE(p->feat.raw));
 *res = p->feat.raw[subleaf];
 break;
 
-- 
2.1.4


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[Xen-devel] [PATCH 3/6] x86/cpuid: Handle leaf 0 in guest_cpuid()

[Andrew Cooper]

Calculate a domains x86_vendor early in recalculate_cpuid_policy(); subsequent
patches need to make other recalculation decisions based on it.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
---
 xen/arch/x86/cpuid.c| 13 -
 xen/arch/x86/domctl.c   | 10 ++
 xen/include/asm-x86/cpuid.h |  4 +++-
 3 files changed, 17 insertions(+), 10 deletions(-)

diff --git a/xen/arch/x86/cpuid.c b/xen/arch/x86/cpuid.c
index 076fab3..85c829d 100644
--- a/xen/arch/x86/cpuid.c
+++ b/xen/arch/x86/cpuid.c
@@ -355,6 +355,9 @@ void recalculate_cpuid_policy(struct domain *d)
 uint32_t fs[FSCAPINTS], max_fs[FSCAPINTS];
 unsigned int i;
 
+p->x86_vendor = get_cpu_vendor(p->basic.vendor_ebx, p->basic.vendor_ecx,
+   p->basic.vendor_edx, gcv_guest);
+
 p->basic.max_leaf   = min(p->basic.max_leaf,   max->basic.max_leaf);
 p->feat.max_subleaf = min(p->feat.max_subleaf, max->feat.max_subleaf);
 p->extd.max_leaf= min(p->extd.max_leaf,max->extd.max_leaf);
@@ -677,6 +680,7 @@ static void pv_cpuid(uint32_t leaf, uint32_t subleaf, 
struct cpuid_leaf *res)
 *res = EMPTY_LEAF;
 break;
 
+case 0x0:
 case 0x7:
 case XSTATE_CPUID:
 ASSERT_UNREACHABLE();
@@ -825,6 +829,7 @@ static void hvm_cpuid(uint32_t leaf, uint32_t subleaf, 
struct cpuid_leaf *res)
 res->a = 0;
 break;
 
+case 0x0:
 case 0x7:
 case XSTATE_CPUID:
 ASSERT_UNREACHABLE();
@@ -850,7 +855,9 @@ void guest_cpuid(const struct vcpu *v, uint32_t leaf,
 switch ( leaf )
 {
 case 0 ... CPUID_GUEST_NR_BASIC - 1:
-if ( leaf > p->basic.max_leaf )
+ASSERT(p->basic.max_leaf < ARRAY_SIZE(p->basic.raw));
+if ( leaf > min_t(uint32_t, p->basic.max_leaf,
+  ARRAY_SIZE(p->basic.raw) - 1) )
 return;
 
 switch ( leaf )
@@ -873,6 +880,10 @@ void guest_cpuid(const struct vcpu *v, uint32_t leaf,
 
 default:
 goto legacy;
+
+case 0x0:
+*res = p->basic.raw[leaf];
+break;
 }
 break;
 
diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c
index a3f51f3..8e5259f 100644
--- a/xen/arch/x86/domctl.c
+++ b/xen/arch/x86/domctl.c
@@ -92,7 +92,7 @@ static int update_domain_cpuid_info(struct domain *d,
 {
 struct cpuid_policy *p = d->arch.cpuid;
 const struct cpuid_leaf leaf = { ctl->eax, ctl->ebx, ctl->ecx, ctl->edx };
-int rc;
+int rc, old_vendor = p->x86_vendor;
 
 /*
  * Skip update for leaves we don't care about.  This avoids the overhead
@@ -155,11 +155,7 @@ static int update_domain_cpuid_info(struct domain *d,
 
 switch ( ctl->input[0] )
 {
-case 0: {
-int old_vendor = p->x86_vendor;
-
-p->x86_vendor = get_cpu_vendor(ctl->ebx, ctl->ecx, ctl->edx, 
gcv_guest);
-
+case 0:
 if ( is_hvm_domain(d) && (p->x86_vendor != old_vendor) )
 {
 struct vcpu *v;
@@ -167,9 +163,7 @@ static int update_domain_cpuid_info(struct domain *d,
 for_each_vcpu( d, v )
 hvm_update_guest_vendor(v);
 }
-
 break;
-}
 
 case 1:
 if ( is_pv_domain(d) && ((levelling_caps & LCAP_1cd) == LCAP_1cd) )
diff --git a/xen/include/asm-x86/cpuid.h b/xen/include/asm-x86/cpuid.h
index e5140ca..299a026 100644
--- a/xen/include/asm-x86/cpuid.h
+++ b/xen/include/asm-x86/cpuid.h
@@ -81,6 +81,7 @@ struct cpuid_policy
  *   - All of the feat and xstate unions
  *   - max_{,sub}leaf
  *   - All FEATURESET_* words
+ *   - Low short vendor infomation
  *
  * Per-domain objects:
  *
@@ -88,6 +89,7 @@ struct cpuid_policy
  *   - All of the feat and xstate unions
  *   - max_{,sub}leaf
  *   - All FEATURESET_* words
+ *   - Low short vendor infomation
  *
  * Everything else should be considered inaccurate, and not necesserily 0.
  */
@@ -101,7 +103,7 @@ struct cpuid_policy
 struct cpuid_leaf raw[CPUID_GUEST_NR_BASIC];
 struct {
 /* Leaf 0x0 - Max and vendor. */
-uint32_t max_leaf, /* b */:32, /* c */:32, /* d */:32;
+uint32_t max_leaf, vendor_ebx, vendor_ecx, vendor_edx;
 
 /* Leaf 0x1 - Family/model/stepping and features. */
 uint32_t raw_fms, /* b */:32;
-- 
2.1.4


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[Xen-devel] [PATCH 1/6] x86/cpuid: Hide VT-x/SVM from HVM-based control domains

[Andrew Cooper]

The VT-x/SVM features are hidden from PV dom0 by the pv_featureset[] upper
mask, but nothing thusfar has prevented the features being visible in
HVM-based control domains (where there is no toolstack decision to hide the
features).

As a side effect of calling nestedhvm_enabled() earlier during domain
creation, it needs to cope with the params[] array array not having been
allocated.

Reported-by: Roger Pau Monné 
Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 
---
 xen/arch/x86/cpuid.c | 25 ++---
 xen/arch/x86/hvm/nestedhvm.c |  3 ++-
 2 files changed, 20 insertions(+), 8 deletions(-)

diff --git a/xen/arch/x86/cpuid.c b/xen/arch/x86/cpuid.c
index eb829d7..7b9af1b 100644
--- a/xen/arch/x86/cpuid.c
+++ b/xen/arch/x86/cpuid.c
@@ -3,6 +3,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -361,14 +362,24 @@ void recalculate_cpuid_policy(struct domain *d)
 cpuid_policy_to_featureset(p, fs);
 cpuid_policy_to_featureset(max, max_fs);
 
-/*
- * HVM domains using Shadow paging have further restrictions on their
- * available paging features.
- */
-if ( is_hvm_domain(d) && !hap_enabled(d) )
+if ( is_hvm_domain(d) )
 {
-for ( i = 0; i < ARRAY_SIZE(max_fs); i++ )
-max_fs[i] &= hvm_shadow_featuremask[i];
+/*
+ * HVM domains using Shadow paging have further restrictions on their
+ * available paging features.
+ */
+if ( !hap_enabled(d) )
+{
+for ( i = 0; i < ARRAY_SIZE(max_fs); i++ )
+max_fs[i] &= hvm_shadow_featuremask[i];
+}
+
+/* Hide nested-virt if it hasn't been explicitly configured. */
+if ( !nestedhvm_enabled(d) )
+{
+__clear_bit(X86_FEATURE_VMX, max_fs);
+__clear_bit(X86_FEATURE_SVM, max_fs);
+}
 }
 
 /*
diff --git a/xen/arch/x86/hvm/nestedhvm.c b/xen/arch/x86/hvm/nestedhvm.c
index a400d55..f2f7469 100644
--- a/xen/arch/x86/hvm/nestedhvm.c
+++ b/xen/arch/x86/hvm/nestedhvm.c
@@ -29,7 +29,8 @@ static unsigned long *shadow_io_bitmap[3];
 /* Nested HVM on/off per domain */
 bool nestedhvm_enabled(const struct domain *d)
 {
-return is_hvm_domain(d) && d->arch.hvm_domain.params[HVM_PARAM_NESTEDHVM];
+return is_hvm_domain(d) && d->arch.hvm_domain.params &&
+d->arch.hvm_domain.params[HVM_PARAM_NESTEDHVM];
 }
 
 /* Nested VCPU */
-- 
2.1.4


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[Xen-devel] [PATCH 5/6] x86/cpuid: Handle the long vendor string in guest_cpuid()

[Andrew Cooper]

Leaves 0x8002 through 0x8004 are plain ASCII text, and require no
specific recalculation.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
---
 xen/arch/x86/cpuid.c| 3 +++
 xen/include/asm-x86/cpuid.h | 4 ++--
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/xen/arch/x86/cpuid.c b/xen/arch/x86/cpuid.c
index dc76cf4..7926d0b 100644
--- a/xen/arch/x86/cpuid.c
+++ b/xen/arch/x86/cpuid.c
@@ -706,6 +706,7 @@ static void pv_cpuid(uint32_t leaf, uint32_t subleaf, 
struct cpuid_leaf *res)
 case 0x7:
 case XSTATE_CPUID:
 case 0x8000:
+case 0x8002 ... 0x8004:
 ASSERT_UNREACHABLE();
 /* Now handled in guest_cpuid(). */
 }
@@ -856,6 +857,7 @@ static void hvm_cpuid(uint32_t leaf, uint32_t subleaf, 
struct cpuid_leaf *res)
 case 0x7:
 case XSTATE_CPUID:
 case 0x8000:
+case 0x8002 ... 0x8004:
 ASSERT_UNREACHABLE();
 /* Now handled in guest_cpuid(). */
 }
@@ -936,6 +938,7 @@ void guest_cpuid(const struct vcpu *v, uint32_t leaf,
 goto legacy;
 
 case 0x8000:
+case 0x8002 ... 0x8004:
 *res = p->extd.raw[leaf & 0x];
 break;
 }
diff --git a/xen/include/asm-x86/cpuid.h b/xen/include/asm-x86/cpuid.h
index 4712b73..d181e9a 100644
--- a/xen/include/asm-x86/cpuid.h
+++ b/xen/include/asm-x86/cpuid.h
@@ -81,7 +81,7 @@ struct cpuid_policy
  *   - All of the feat and xstate unions
  *   - max_{,sub}leaf
  *   - All FEATURESET_* words
- *   - Short vendor infomation
+ *   - Short and long vendor infomation
  *
  * Per-domain objects:
  *
@@ -89,7 +89,7 @@ struct cpuid_policy
  *   - All of the feat and xstate unions
  *   - max_{,sub}leaf
  *   - All FEATURESET_* words
- *   - Short vendor infomation
+ *   - Short and long vendor infomation
  *
  * Everything else should be considered inaccurate, and not necesserily 0.
  */
-- 
2.1.4


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[Xen-devel] [PATCH 0/6] x86/cpuid: Handling of simple leaves in guest_cpuid()

[Andrew Cooper]

The following series (with any luck) is sufficient to allow PVH-dom0's to
function without any CPUID policy hackary during construction.

Andrew Cooper (6):
  x86/cpuid: Hide VT-x/SVM from HVM-based control domains
  x86/cpuid: Remove BUG_ON() condition from guest_cpuid()
  x86/cpuid: Handle leaf 0 in guest_cpuid()
  x86/cpuid: Handle leaf 0x8000 in guest_cpuid()
  x86/cpuid: Handle the long vendor string in guest_cpuid()
  x86/cpuid: Only recalculate the shared feature bits once

 tools/libxc/xc_cpuid_x86.c   |  19 ---
 xen/arch/x86/cpuid.c | 119 ++-
 xen/arch/x86/domctl.c|  10 +---
 xen/arch/x86/hvm/nestedhvm.c |   3 +-
 xen/include/asm-x86/cpuid.h  |   6 ++-
 xen/tools/gen-cpuid.py   |  29 ---
 6 files changed, 101 insertions(+), 85 deletions(-)

-- 
2.1.4


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[Xen-devel] [PATCH 4/6] x86/cpuid: Handle leaf 0x80000000 in guest_cpuid()

[Andrew Cooper]

The calculations for p->extd.max_leaf are reworked to force a value of at
least 0x8000, and to take the domains chosen vendor into account when
clamping maximum value.

The high short vendor information is clobbered or duplicated according to the
chosen vendor.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
---
 xen/arch/x86/cpuid.c| 48 +++--
 xen/include/asm-x86/cpuid.h |  6 +++---
 2 files changed, 45 insertions(+), 9 deletions(-)

diff --git a/xen/arch/x86/cpuid.c b/xen/arch/x86/cpuid.c
index 85c829d..dc76cf4 100644
--- a/xen/arch/x86/cpuid.c
+++ b/xen/arch/x86/cpuid.c
@@ -163,6 +163,24 @@ static void recalculate_xstate(struct cpuid_policy *p)
 }
 }
 
+static void recalculate_common(struct cpuid_policy *p)
+{
+switch ( p->x86_vendor )
+{
+case X86_VENDOR_INTEL:
+p->extd.vendor_ebx = 0;
+p->extd.vendor_ecx = 0;
+p->extd.vendor_edx = 0;
+break;
+
+case X86_VENDOR_AMD:
+p->extd.vendor_ebx = p->basic.vendor_ebx;
+p->extd.vendor_ecx = p->basic.vendor_ecx;
+p->extd.vendor_edx = p->basic.vendor_edx;
+break;
+}
+}
+
 static void __init calculate_raw_policy(void)
 {
 struct cpuid_policy *p = _policy;
@@ -227,12 +245,12 @@ static void __init calculate_host_policy(void)
 min_t(uint32_t, p->basic.max_leaf,   ARRAY_SIZE(p->basic.raw) - 1);
 p->feat.max_subleaf =
 min_t(uint32_t, p->feat.max_subleaf, ARRAY_SIZE(p->feat.raw) - 1);
-p->extd.max_leaf =
-min_t(uint32_t, p->extd.max_leaf,
-  0x8000u + ARRAY_SIZE(p->extd.raw) - 1);
+p->extd.max_leaf = 0x8000 | min_t(uint32_t, p->extd.max_leaf & 0x,
+  ARRAY_SIZE(p->extd.raw) - 1);
 
 cpuid_featureset_to_policy(boot_cpu_data.x86_capability, p);
 recalculate_xstate(p);
+recalculate_common(p);
 }
 
 static void __init calculate_pv_max_policy(void)
@@ -360,7 +378,10 @@ void recalculate_cpuid_policy(struct domain *d)
 
 p->basic.max_leaf   = min(p->basic.max_leaf,   max->basic.max_leaf);
 p->feat.max_subleaf = min(p->feat.max_subleaf, max->feat.max_subleaf);
-p->extd.max_leaf= min(p->extd.max_leaf,max->extd.max_leaf);
+p->extd.max_leaf= 0x8000 | min(p->extd.max_leaf & 0x,
+   (p->x86_vendor == X86_VENDOR_AMD
+? CPUID_GUEST_NR_EXTD_AMD
+: CPUID_GUEST_NR_EXTD_INTEL) - 1);
 
 cpuid_policy_to_featureset(p, fs);
 cpuid_policy_to_featureset(max, max_fs);
@@ -428,6 +449,7 @@ void recalculate_cpuid_policy(struct domain *d)
 
 cpuid_featureset_to_policy(fs, p);
 recalculate_xstate(p);
+recalculate_common(p);
 }
 
 int init_domain_cpuid_policy(struct domain *d)
@@ -683,6 +705,7 @@ static void pv_cpuid(uint32_t leaf, uint32_t subleaf, 
struct cpuid_leaf *res)
 case 0x0:
 case 0x7:
 case XSTATE_CPUID:
+case 0x8000:
 ASSERT_UNREACHABLE();
 /* Now handled in guest_cpuid(). */
 }
@@ -832,6 +855,7 @@ static void hvm_cpuid(uint32_t leaf, uint32_t subleaf, 
struct cpuid_leaf *res)
 case 0x0:
 case 0x7:
 case XSTATE_CPUID:
+case 0x8000:
 ASSERT_UNREACHABLE();
 /* Now handled in guest_cpuid(). */
 }
@@ -901,9 +925,21 @@ void guest_cpuid(const struct vcpu *v, uint32_t leaf,
 return cpuid_hypervisor_leaves(v, leaf, subleaf, res);
 
 case 0x8000 ... 0x8000 + CPUID_GUEST_NR_EXTD - 1:
-if ( leaf > p->extd.max_leaf )
+ASSERT((p->extd.max_leaf & 0x) < ARRAY_SIZE(p->extd.raw));
+if ( (leaf & 0x) > min_t(uint32_t, p->extd.max_leaf & 0x,
+ ARRAY_SIZE(p->extd.raw) - 1) )
 return;
-goto legacy;
+
+switch ( leaf )
+{
+default:
+goto legacy;
+
+case 0x8000:
+*res = p->extd.raw[leaf & 0x];
+break;
+}
+break;
 
 default:
 return;
diff --git a/xen/include/asm-x86/cpuid.h b/xen/include/asm-x86/cpuid.h
index 299a026..4712b73 100644
--- a/xen/include/asm-x86/cpuid.h
+++ b/xen/include/asm-x86/cpuid.h
@@ -81,7 +81,7 @@ struct cpuid_policy
  *   - All of the feat and xstate unions
  *   - max_{,sub}leaf
  *   - All FEATURESET_* words
- *   - Low short vendor infomation
+ *   - Short vendor infomation
  *
  * Per-domain objects:
  *
@@ -89,7 +89,7 @@ struct cpuid_policy
  *   - All of the feat and xstate unions
  *   - max_{,sub}leaf
  *   - All FEATURESET_* words
- *   - Low short vendor infomation
+ *   - Short vendor infomation
  *
  * Everything else should be considered inaccurate, and not necesserily 0.
  */
@@ -168,7 +168,7 @@ struct cpuid_policy
 struct cpuid_leaf 

Re: [Xen-devel] [PATCH 1/2] xen/kbdif: update protocol documentation

[Oleksandr Andrushchenko]

On 01/12/2017 08:36 AM, Oleksandr Andrushchenko wrote:

On 01/12/2017 12:50 AM, Dario Faggioli wrote:

On Wed, 2017-01-11 at 20:40 +0200, Oleksandr Andrushchenko wrote:

On 01/11/2017 07:35 PM, Dario Faggioli wrote:

  It's indeed a repetition, but a good one, IMO: it helps the reader,
as
she won't have to go back to figure out how big the struct was, how
the
macro was call and to what value it was defined).

I am still not convinced that we should put it.
Probably we can go the way other RFCs do, like TCP [1], 802.11 [2]
etc:
those do not define any reserved fields at the bottom of structures,
(which are effectively padding?) but are limited to only those fields
which are defined.


In principle, I like the idea of following the example of those RFCs.
However, I'd say that what we should value most is consistency within
our own source tree.

But, TBH, there aren't many binary diagram already committed in
include/public/io, so it's hard to tell.

FWIW, I still think that providing a clue to the reader about the size
--even if already specified somewhere else-- would be beneficial, but
it's a rather minor thing, and I certainly can leave with whatever you
and the maintainer(s) agree upon.

fair enough

Regards,
Dario

Konrad, could you please define what that ASCII box
notation should look like?


Stefano, Konrad
As per my understanding this is the only thing blocking multi-touch
and updated kbdif protocol from being upgraded/extended )
Could you please make some decision on this any time soon?

Thank you,
Oleksandr



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[Xen-devel] [PATCH 6/6] x86/cpuid: Only recalculate the shared feature bits once

[Andrew Cooper]

With accurate vendor information available, the shared bits can be sorted out
during recalculation, rather than at query time in the legacy cpuid path.

This means that:
 * Duplication can be dropped from the automatically generated cpuid data.
 * The toolstack need not worry about setting them appropriately.
 * They can be dropped from the system maximum featuresets.

While editing gen-cpuid.py, reflow some comments which exceeded the expected
line length.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Ian Jackson 
CC: Wei Liu 
---
 tools/libxc/xc_cpuid_x86.c | 19 ---
 xen/arch/x86/cpuid.c   | 25 +
 xen/tools/gen-cpuid.py | 29 ++---
 3 files changed, 15 insertions(+), 58 deletions(-)

diff --git a/tools/libxc/xc_cpuid_x86.c b/tools/libxc/xc_cpuid_x86.c
index 96d6025..918590f 100644
--- a/tools/libxc/xc_cpuid_x86.c
+++ b/tools/libxc/xc_cpuid_x86.c
@@ -41,7 +41,6 @@ enum {
 #define DEF_MAX_BASE 0x000du
 #define DEF_MAX_INTELEXT  0x8008u
 #define DEF_MAX_AMDEXT0x801cu
-#define COMMON_1D CPUID_COMMON_1D_FEATURES
 
 int xc_get_cpu_levelling_caps(xc_interface *xch, uint32_t *caps)
 {
@@ -712,24 +711,6 @@ static void sanitise_featureset(struct cpuid_domain_info 
*info)
 disabled_features[i] &= ~dfs[i];
 }
 }
-
-switch ( info->vendor )
-{
-case VENDOR_INTEL:
-/* Intel clears the common bits in e1d. */
-info->featureset[featureword_of(X86_FEATURE_SYSCALL)] &= ~COMMON_1D;
-break;
-
-case VENDOR_AMD:
-/* AMD duplicates the common bits between 1d and e1d. */
-info->featureset[featureword_of(X86_FEATURE_SYSCALL)] =
-((info->featureset[featureword_of(X86_FEATURE_FPU)] & COMMON_1D) |
- (info->featureset[featureword_of(X86_FEATURE_SYSCALL)] & 
~COMMON_1D));
-break;
-
-default:
-break;
-}
 }
 
 int xc_cpuid_apply_policy(xc_interface *xch, domid_t domid,
diff --git a/xen/arch/x86/cpuid.c b/xen/arch/x86/cpuid.c
index 7926d0b..a27a8d6 100644
--- a/xen/arch/x86/cpuid.c
+++ b/xen/arch/x86/cpuid.c
@@ -67,18 +67,6 @@ static void sanitise_featureset(uint32_t *fs)
 disabled_features[j] &= ~dfs[j];
 }
 }
-
-/*
- * Sort out shared bits.  We are constructing a featureset which needs to
- * be applicable to a cross-vendor case.  Intel strictly clears the common
- * bits in e1d, while AMD strictly duplicates them.
- *
- * We duplicate them here to be compatible with AMD while on Intel, and
- * rely on logic closer to the guest to make the featureset stricter if
- * emulating Intel.
- */
-fs[FEATURESET_e1d] = ((fs[FEATURESET_1d]  &  CPUID_COMMON_1D_FEATURES) |
-  (fs[FEATURESET_e1d] & ~CPUID_COMMON_1D_FEATURES));
 }
 
 static void recalculate_xstate(struct cpuid_policy *p)
@@ -165,6 +153,8 @@ static void recalculate_xstate(struct cpuid_policy *p)
 
 static void recalculate_common(struct cpuid_policy *p)
 {
+p->extd.e1d &= ~CPUID_COMMON_1D_FEATURES;
+
 switch ( p->x86_vendor )
 {
 case X86_VENDOR_INTEL:
@@ -177,6 +167,8 @@ static void recalculate_common(struct cpuid_policy *p)
 p->extd.vendor_ebx = p->basic.vendor_ebx;
 p->extd.vendor_ecx = p->basic.vendor_ecx;
 p->extd.vendor_edx = p->basic.vendor_edx;
+
+p->extd.e1d |= p->basic._1d & CPUID_COMMON_1D_FEATURES;
 break;
 }
 }
@@ -665,10 +657,6 @@ static void pv_cpuid(uint32_t leaf, uint32_t subleaf, 
struct cpuid_leaf *res)
 res->c = p->extd.e1c;
 res->d = p->extd.e1d;
 
-/* If not emulating AMD, clear the duplicated features in e1d. */
-if ( p->x86_vendor != X86_VENDOR_AMD )
-res->d &= ~CPUID_COMMON_1D_FEATURES;
-
 /*
  * MTRR used to unconditionally leak into PV guests.  They cannot MTRR
  * infrastructure at all, and shouldn't be able to see the feature.
@@ -790,11 +778,8 @@ static void hvm_cpuid(uint32_t leaf, uint32_t subleaf, 
struct cpuid_leaf *res)
 res->c = p->extd.e1c;
 res->d = p->extd.e1d;
 
-/* If not emulating AMD, clear the duplicated features in e1d. */
-if ( p->x86_vendor != X86_VENDOR_AMD )
-res->d &= ~CPUID_COMMON_1D_FEATURES;
 /* fast-forward MSR_APIC_BASE.EN if it hasn't already been clobbered. 
*/
-else if ( vlapic_hw_disabled(vcpu_vlapic(v)) )
+if ( vlapic_hw_disabled(vcpu_vlapic(v)) )
 res->d &= ~cpufeat_bit(X86_FEATURE_APIC);
 
 /*
diff --git a/xen/tools/gen-cpuid.py b/xen/tools/gen-cpuid.py
index 6212e4f..5cab6db 100755
--- a/xen/tools/gen-cpuid.py
+++ b/xen/tools/gen-cpuid.py
@@ -129,16 +129,7 @@ def crunch_numbers(state):
 common_1d = (FPU, VME, DE, PSE, TSC, MSR, PAE, MCE, CX8, APIC,
  MTRR, PGE, MCA, CMOV, PAT, PSE36, MMX, 

Re: [Xen-devel] PV audio drivers for Linux

[Oleksandr Andrushchenko]

On 01/18/2017 08:52 PM, Stefano Stabellini wrote:

On Wed, 18 Jan 2017, Ughreja, Rakesh A wrote:

-Original Message-
From: Stefano Stabellini [mailto:sstabell...@kernel.org]
Sent: Wednesday, January 18, 2017 5:41 AM
To: Ughreja, Rakesh A 
Cc: xen-devel@lists.xen.org; oleksandr_andrushche...@epam.com;
oleksandr_gryt...@epam.com; oleksandr.dmytrys...@globallogic.com;
iurii.konovale...@globallogic.com; konrad.w...@oracle.com
Subject: Re: [Xen-devel] PV audio drivers for Linux

On Tue, 17 Jan 2017, Ughreja, Rakesh A wrote:

Hi,

I am trying to develop PV audio drivers and facing one issue to
achieve zero copy of the buffers between Front End (DOM1) and
Back End (DOM0) drivers.

You might want to take a look at the existing PV sound proposal:

http://marc.info/?l=xen-devel=148094319010445


Sure, let me look into this.
Thank you very much for the quick reply and the reference.


When the buffer is allocated using __get_free_pages() on the DOM0
OS, I am able to grant the access using gnttab_grant_foreign_access()
to DOM1 as well as I am able to map it in the DOM1 virtual space
using xenbus_map_ring_valloc().

However the existing audio driver allocates buffer using
dma_alloc_coherent(). In that case I am able to grant the access using
gnttab_grant_foreign_access() to DOM1 but when I try to map in the
DOM1 virtual space using xenbus_map_ring_valloc(), it returns an error.

[1] Code returns from here.

507 xenbus_dev_fatal(dev, map[i].status,
508  "mapping in shared page %d from domain 
%d",
509  gnt_refs[i], dev->otherend_id);

gnttab_batch_map(map, i) is unable to map the page, but I am unable to
understand why. May be its due to the difference in the way buffers
are allocated dma_alloc_coherent() vs __get_free_pages().

Since I don't want to touch existing audio driver, I need to figure out
how to map buffer to DOM1 space with dma_alloc_coherent().

Any pointers would be really helpful. Thank you in advance.

Pages allocated by dma_alloc_coherent can be a bit special. Are you
going through the swiotlb-xen
(drivers/xen/swiotlb-xen.c:xen_swiotlb_alloc_coherent) in Dom0?


No, I am not using this.

Keep in mind that when swiotlb-xen is used, it is transparent from the
device driver point of view. You might be using it without knowing. I
suggest you add a printk in there to be sure.



Actually I am trying to reuse the existing
HDA driver and just opening the ALSA streams at kernel level in
PV Backend driver.

Buffers are allocated by the existing HDA driver.
http://lxr.free-electrons.com/source/sound/core/memalloc.c#L83


I would probably add a few printks to Xen in
xen/common/grant_table.c:do_grant_table_op to understand what is the
error exactly.

In the gnttab_retry_eagain_gop function, when it tries to
get the status it always receives status as GNTST_eagain. After the retries
the status is marked as GNTST_bad_page.

I am unable to figure out what properties of dma_alloc_coherent allocated
buffers makes it un-mappable at Dom1.

Nothing comes to mind, but maybe the x86 maintainers (CC'ed) know.

just a guess. please check [1]. I had problems mapping

dma_alloc_coherent pages in DomU because of

vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);

which cannot be done in unprivileged domain

Regards,
Oleksandr


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[1] https://lists.xen.org/archives/html/xen-devel/2016-11/msg02882.html

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Re: [Xen-devel] [PATCH v4 3/8] dm_op: convert HVMOP_track_dirty_vram

[Daniel De Graaf]

On 01/17/2017 12:29 PM, Paul Durrant wrote:

The handle type passed to the underlying shadow and hap functions is
changed for compatibility with the new hypercall buffer.

NOTE: This patch also modifies the type of the 'nr' parameter of
  xc_hvm_track_dirty_vram() from uint64_t to uint32_t. In practice
  the value passed was always truncated to 32 bits.

Suggested-by: Jan Beulich 
Signed-off-by: Paul Durrant 


Acked-by: Daniel De Graaf 

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Re: [Xen-devel] xennet_start_xmit assumptions

[Konrad Rzeszutek Wilk]

On Wed, Jan 18, 2017 at 10:31:32AM -0500, Sowmini Varadhan wrote:
> As I was playing around with pf_packet, I accidentally wrote
> a buggy application program that bzero'ed the msghdr, then set
> up the msg_name, msg_namelen correctly, and then did a sendmsg
> on the pf_packet/SOCK_RAW fd.
> 
> This causes packet_snd to set up an skb with a lot of issues,
> e.g., skb->len = 0, skb_headlen(skb) is 0, etc. I think we can/should
> drop the packet in packet_snd if the skb->len is 0, but there
> may be other driver bugs going on:
> 
> Turns out that ixgbe and sunvnet handle this problematic
> skb correctly (they drop it and system remains stable), 
> but it creates a panic in xen_netfront (xennet_start_xmit()
> hits a null pointer deref when xennet_make_first_txreq() returns 
> NULL)
> 
> I'm new to the xen driver code, so I'm hoping that
> the experts can comment here: reading the code in xennet_start_xmit,
> it seems like it mandatorily requires the skb_headlen() to be
> non-zero in order to create the first_tx? That may not always be
> true, how does the code recover for purely non-linear skbs?
> 
> --Sowmini

CC-ing the two folks from the MAINTAINERS file.

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Re: [Xen-devel] [PATCH v2 2/2] swiotlb-xen: implement xen_swiotlb_get_sgtable callback

[Stefano Stabellini]

On Wed, 18 Jan 2017, Andrii Anisov wrote:
> Stefano,
> 
> About this piece:
> 
> >
> > -   if (__generic_dma_ops(dev)->get_sgtable)
> > +
> > +   if (__generic_dma_ops(dev)->get_sgtable) {
> > +   /* We can't handle foreign pages here. */
> > +#ifdef CONFIG_ARM
> > +   unsigned long bfn = dma_to_pfn(dev, handle);
> > +#else
> > +   unsigned long bfn = handle >> PAGE_SHIFT;
> > +#endif
> > +   BUG_ON (!page_is_ram(bfn));
> > return __generic_dma_ops(dev)->get_sgtable(dev, sgt, 
> > cpu_addr, handle,
> >  size, 
> > attrs);
> > +   }
> > return dma_common_get_sgtable(dev, sgt, cpu_addr, handle, size);
> >  }
> 
> 
> Would it be in drivers/xen/swiotlb-xen.c as you suggested, the whole
> "if (__generic_dma_ops(dev)->get_sgtable) {}" should be under ifdef.
> 
> IMO it would be better to avoid ifdefs in drivers/xen/swiotlb-xen.c,
> but I haven't find out how to do that.

Yes, I dislike ifdef like everybody else, but sometimes they are
unavoidable.

But please test this code because I only compile tested it :-)

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Re: [Xen-devel] [PATCH v4 7/8] dm_op: convert HVMOP_inject_trap and HVMOP_inject_msi

[Daniel De Graaf]

On 01/17/2017 12:29 PM, Paul Durrant wrote:

NOTE: This patch also modifies the types of the 'vector', 'type' and
  'insn_len' arguments of xc_hvm_inject_trap() from uint32_t to
  uint8_t. In practice the values passed were always truncated to
  8 bits.

Suggested-by: Jan Beulich 
Signed-off-by: Paul Durrant 


Acked-by: Daniel De Graaf 


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Re: [Xen-devel] [PATCH v4 6/8] dm_op: convert HVMOP_set_mem_type

[Daniel De Graaf]

On 01/17/2017 12:29 PM, Paul Durrant wrote:

This patch removes the need for handling HVMOP restarts, so that
infrastructure is removed.

NOTE: This patch also modifies the type of the 'nr' argument of
  xc_hvm_set_mem_type() from uint64_t to uint32_t. In practice the
  value passed was always truncated to 32 bits.

Suggested-by: Jan Beulich 
Signed-off-by: Paul Durrant 


Acked-by: Daniel De Graaf 

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Re: [Xen-devel] [PATCH v4 5/8] dm_op: convert HVMOP_modified_memory

[Daniel De Graaf]

On 01/17/2017 12:29 PM, Paul Durrant wrote:

This patch introduces code to handle DMOP continuations.

NOTE: This patch also modifies the type of the 'nr' argument of
  xc_hvm_modified_memory() from uint64_t to uint32_t. In practice the
  value passed was always truncated to 32 bits.

Suggested-by: Jan Beulich 
Signed-off-by: Paul Durrant 


Acked-by: Daniel De Graaf 

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Re: [Xen-devel] [PATCH v4 4/8] dm_op: convert HVMOP_set_pci_intx_level, HVMOP_set_isa_irq_level, and...

[Daniel De Graaf]

On 01/17/2017 12:29 PM, Paul Durrant wrote:

... HVMOP_set_pci_link_route

These HVMOPs were exposed to guests so their definitions need to be
preserved for compatibility. This patch therefore updates
__XEN_LATEST_INTERFACE_VERSION__ to 0x00040900 and makes the HVMOP
defintions conditional on __XEN_INTERFACE_VERSION__ less than that value.

NOTE: This patch also widens the 'domain' parameter of
  xc_hvm_set_pci_intx_level() from a uint8_t to a uint16_t.

Suggested-by: Jan Beulich 
Signed-off-by: Paul Durrant 
---
Reviewed-by: Jan Beulich 
Cc: Daniel De Graaf 
Cc: Ian Jackson 
Acked-by: Wei Liu 
Cc: Andrew Cooper 


Acked-by: Daniel De Graaf 

This patch (and the previous one) remove some of the permissions from
the create_domain_common macro without adding the replacement permission.
This would be a problem if the domain builder code used them, but a quick
grep seems to say that they're not actually used by the domain builder.
It looks like this ended up as a bonus improvement from this change.

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Re: [Xen-devel] [PATCH v4 2/8] dm_op: convert HVMOP_*ioreq_server*

[Daniel De Graaf]

On 01/17/2017 12:29 PM, Paul Durrant wrote:

The definitions of HVM_IOREQSRV_BUFIOREQ_* have to persist as they are
already in use by callers of the libxc interface.

Suggested-by: Jan Beulich 
Signed-off-by: Paul Durrant 


Acked-by: Daniel De Graaf 

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Re: [Xen-devel] [PATCH v4 1/8] public / x86: Introduce __HYPERCALL_dm_op...

[Daniel De Graaf]

On 01/17/2017 12:29 PM, Paul Durrant wrote:

...as a set of hypercalls to be used by a device model.

As stated in the new docs/designs/dm_op.markdown:

"The aim of DMOP is to prevent a compromised device model from
compromising domains other then the one it is associated with. (And is
therefore likely already compromised)."

See that file for further information.

This patch simply adds the boilerplate for the hypercall.

Signed-off-by: Paul Durrant 
Suggested-by: Ian Jackson 
Suggested-by: Jennifer Herbert 


Acked-by: Daniel De Graaf 

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