[Xen-devel] [xen-unstable test] 107085: tolerable FAIL - PUSHED
flight 107085 xen-unstable real [real] http://logs.test-lab.xenproject.org/osstest/logs/107085/ Failures :-/ but no regressions. Tests which are failing intermittently (not blocking): test-armhf-armhf-libvirt-xsm 7 host-ping-check-xen fail in 107069 pass in 107085 test-amd64-i386-xl-qemut-debianhvm-amd64 15 guest-localmigrate/x10 fail pass in 107069 test-armhf-armhf-xl-vhd 10 guest-startfail pass in 107069 Regressions which are regarded as allowable (not blocking): test-armhf-armhf-libvirt-xsm 13 saverestore-support-checkfail like 107034 test-armhf-armhf-libvirt 13 saverestore-support-checkfail like 107034 test-amd64-amd64-xl-qemut-win7-amd64 16 guest-stopfail like 107034 test-amd64-i386-xl-qemuu-win7-amd64 16 guest-stop fail like 107034 test-amd64-i386-xl-qemut-win7-amd64 16 guest-stop fail like 107034 test-amd64-amd64-xl-qemuu-win7-amd64 16 guest-stopfail like 107034 test-armhf-armhf-libvirt-raw 12 saverestore-support-checkfail like 107034 test-amd64-amd64-xl-rtds 9 debian-install fail like 107034 Tests which did not succeed, but are not blocking: test-arm64-arm64-libvirt-xsm 1 build-check(1) blocked n/a test-arm64-arm64-xl 1 build-check(1) blocked n/a build-arm64-libvirt 1 build-check(1) blocked n/a test-arm64-arm64-libvirt-qcow2 1 build-check(1) blocked n/a test-arm64-arm64-libvirt 1 build-check(1) blocked n/a test-arm64-arm64-xl-credit2 1 build-check(1) blocked n/a test-arm64-arm64-xl-rtds 1 build-check(1) blocked n/a test-arm64-arm64-xl-multivcpu 1 build-check(1) blocked n/a test-arm64-arm64-xl-xsm 1 build-check(1) blocked n/a test-armhf-armhf-xl-vhd 11 migrate-support-check fail in 107069 never pass test-armhf-armhf-xl-vhd 12 saverestore-support-check fail in 107069 never pass test-amd64-i386-libvirt 12 migrate-support-checkfail never pass test-amd64-i386-libvirt-xsm 12 migrate-support-checkfail never pass test-amd64-amd64-libvirt-xsm 12 migrate-support-checkfail never pass test-amd64-amd64-libvirt 12 migrate-support-checkfail never pass build-arm64 5 xen-buildfail never pass build-arm64-xsm 5 xen-buildfail never pass test-amd64-amd64-libvirt-qemuu-debianhvm-amd64-xsm 10 migrate-support-check fail never pass test-amd64-i386-libvirt-qemuu-debianhvm-amd64-xsm 10 migrate-support-check fail never pass build-arm64-pvops 5 kernel-build fail never pass test-armhf-armhf-xl-arndale 12 migrate-support-checkfail never pass test-armhf-armhf-xl-arndale 13 saverestore-support-checkfail never pass test-amd64-amd64-libvirt-vhd 11 migrate-support-checkfail never pass test-armhf-armhf-xl-xsm 12 migrate-support-checkfail never pass test-armhf-armhf-xl-xsm 13 saverestore-support-checkfail never pass test-armhf-armhf-xl-multivcpu 12 migrate-support-checkfail never pass test-armhf-armhf-xl-multivcpu 13 saverestore-support-checkfail never pass test-amd64-amd64-qemuu-nested-amd 16 debian-hvm-install/l1/l2 fail never pass test-armhf-armhf-libvirt-xsm 12 migrate-support-checkfail never pass test-armhf-armhf-libvirt 12 migrate-support-checkfail never pass test-armhf-armhf-xl 12 migrate-support-checkfail never pass test-armhf-armhf-xl 13 saverestore-support-checkfail never pass test-armhf-armhf-xl-credit2 12 migrate-support-checkfail never pass test-armhf-armhf-xl-credit2 13 saverestore-support-checkfail never pass test-armhf-armhf-xl-cubietruck 12 migrate-support-checkfail never pass test-armhf-armhf-xl-cubietruck 13 saverestore-support-checkfail never pass test-armhf-armhf-xl-rtds 12 migrate-support-checkfail never pass test-armhf-armhf-xl-rtds 13 saverestore-support-checkfail never pass test-armhf-armhf-libvirt-raw 11 migrate-support-checkfail never pass version targeted for testing: xen 41630eb1b615158af42f4468236457fd3f8a6819 baseline version: xen 35673d2419af4fde4f235414937bec38864db295 Last test of basis 107034 2017-03-31 14:13:27 Z1 days Testing same since 107069 2017-04-01 07:21:25 Z0 days2 attempts People who touched revisions under test: Andrew Cooper Wei Chen jobs: build-amd64-xsm pass build-arm64-xsm fail build-armhf-xsm pass build-i386-xsm
[Xen-devel] [xen-4.6-testing bisection] complete test-xtf-amd64-amd64-3
branch xen-4.6-testing
xenbranch xen-4.6-testing
job test-xtf-amd64-amd64-3
testid xtf-fep
Tree: linux git://xenbits.xen.org/linux-pvops.git
Tree: linuxfirmware git://xenbits.xen.org/osstest/linux-firmware.git
Tree: qemu git://xenbits.xen.org/qemu-xen-traditional.git
Tree: qemuu git://xenbits.xen.org/qemu-xen.git
Tree: xen git://xenbits.xen.org/xen.git
Tree: xtf git://xenbits.xen.org/xtf.git
*** Found and reproduced problem changeset ***
Bug is in tree: xen git://xenbits.xen.org/xen.git
Bug introduced: 7ff6d9fc19ef88d2ca3304a312c0e8a46b61f546
Bug not present: 7017321d9b7b23adb50cad66d55ae526ab5d9fe1
Last fail repro: http://logs.test-lab.xenproject.org/osstest/logs/107099/
commit 7ff6d9fc19ef88d2ca3304a312c0e8a46b61f546
Author: Dario Faggioli
Date: Fri Mar 31 09:03:32 2017 +0200
xen: sched: don't call hooks of the wrong scheduler via VCPU2OP
Within context_saved(), we call the context_saved hook,
and we use VCPU2OP() to determine from what scheduler.
VCPU2OP uses DOM2OP, which uses d->cpupool, which is
NULL when d is the idle domain. And in that case,
DOM2OP just returns ops, the scheduler of cpupool0.
Therefore, if:
- cpupool0's scheduler defines context_saved (like
Credit2 and RTDS do),
- we are not in cpupool0 (i.e., our scheduler is
not ops),
- we are context switching from idle,
we call VCPU2OP(idle_vcpu), which means
DOM2OP(idle->cpupool), which is ops.
Therefore, we both:
- check if context_saved is defined in the wrong
scheduler;
- if yes, call the wrong one.
When using Credit2 at boot, and also Credit2 in
the other cpupool, this is wrong but innocuous,
because it only involves the idle vcpus.
When using Credit2 at boot, and Credit1 in the
other cpupool, this is *totally* wrong, and
it's by chance it does not explode!
When using Credit2 and other schedulers I'm
developping, I hit the following assert (in
sched_credit2.c, on a CPU inside a cpupool that
does not use Credit2):
csched2_context_saved()
{
...
ASSERT(!vcpu_on_runq(svc));
...
}
Fix this by dealing explicitly, in VCPU2OP, with
idle vcpus, returning the scheduler of the pCPU
they (always) run on.
Signed-off-by: Dario Faggioli
Reviewed-by: Juergen Gross
Reviewed-by: George Dunlap
master commit: a3653e6a279213ba4e883b2252415dc98633106a
master date: 2017-03-27 14:28:05 +0100
For bisection revision-tuple graph see:
http://logs.test-lab.xenproject.org/osstest/results/bisect/xen-4.6-testing/test-xtf-amd64-amd64-3.xtf-fep.html
Revision IDs in each graph node refer, respectively, to the Trees above.
Running cs-bisection-step
--graph-out=/home/logs/results/bisect/xen-4.6-testing/test-xtf-amd64-amd64-3.xtf-fep
--summary-out=tmp/107099.bisection-summary --basis-template=106819
--blessings=real,real-bisect xen-4.6-testing test-xtf-amd64-amd64-3 xtf-fep
Searching for failure / basis pass:
107076 fail [host=huxelrebe0] / 106819 [host=baroque1] 106663 [host=godello1]
106529 [host=chardonnay0] 105991 [host=godello1] 105936 [host=italia0] 105831
[host=elbling1] 105816 [host=elbling0] 105685 [host=fiano0] 105673
[host=merlot1] 105664 [host=chardonnay0] 104570 [host=nobling1] 104308
[host=baroque0] 104278 [host=baroque1] 104251 [host=godello1] 103795
[host=godello1] 103407 ok.
Failure / basis pass flights: 107076 / 103407
(tree with no url: minios)
(tree with no url: ovmf)
(tree with no url: seabios)
Tree: linux git://xenbits.xen.org/linux-pvops.git
Tree: linuxfirmware git://xenbits.xen.org/osstest/linux-firmware.git
Tree: qemu git://xenbits.xen.org/qemu-xen-traditional.git
Tree: qemuu git://xenbits.xen.org/qemu-xen.git
Tree: xen git://xenbits.xen.org/xen.git
Tree: xtf git://xenbits.xen.org/xtf.git
Latest b65f2f457c49b2cfd7967c34b7a0b04c25587f13
c530a75c1e6a472b0eb9558310b518f0dfcd8860
57ca3f4a3092695dd553d3ff4540f5559b1c8fc7
44f3d4e6448e37588248db784193b7a047add65a
7ff6d9fc19ef88d2ca3304a312c0e8a46b61f546
2b62f68c373159b0b4b0c24512ebfbc8fb02f58e
Basis pass b65f2f457c49b2cfd7967c34b7a0b04c25587f13
c530a75c1e6a472b0eb9558310b518f0dfcd8860
a7fd3717d99944530b04130f050e83402e64afed
ba9175c5bde6796851d3b9d888ee488fd0257d05
ac699ed4c45a4ea4f93d366b9185d62795ffdf48
1f021c88130b4d2d818ba4f269b3929339c00a88
Generating revisions with ./adhoc-revtuple-generator
git://xenbits.xen.org/linux-pvops.git#b65f2f457c49b2cfd7967c34b7a0b04c25587f13-b65f2f457c49b2cfd7967c34b7a0b04c25587f13
git://xenbits.xen.org/osstest/linux-firmware.git#c530a75c1e6a472b0eb9558310b518f0dfcd8860-c530a75c1e6a472b0eb9558310b518f0dfcd8860
git://xenbits.xen.org/qemu-xen-traditional.git#a7fd3717d99944530b04130f050e83402e64afed-57ca3f4a3092695dd553d3ff4540f5559b1c8fc7
git://xenb
[Xen-devel] [xen-4.6-testing test] 107076: regressions - trouble: broken/fail/pass
flight 107076 xen-4.6-testing real [real] http://logs.test-lab.xenproject.org/osstest/logs/107076/ Regressions :-( Tests which did not succeed and are blocking, including tests which could not be run: test-amd64-i386-rumprun-i386 12 guest-destroyfail REGR. vs. 106819 test-xtf-amd64-amd64-3 10 xtf-fep fail REGR. vs. 106819 test-xtf-amd64-amd64-3 11 xtf-run fail REGR. vs. 106819 test-xtf-amd64-amd64-5 11 xtf-run fail REGR. vs. 106819 test-xtf-amd64-amd64-1 10 xtf-fep fail REGR. vs. 106819 test-xtf-amd64-amd64-2 11 xtf-run fail REGR. vs. 106819 test-amd64-amd64-rumprun-amd64 12 guest-destroy fail REGR. vs. 106819 test-xtf-amd64-amd64-1 11 xtf-run fail REGR. vs. 106819 test-xtf-amd64-amd64-4 10 xtf-fep fail REGR. vs. 106819 test-amd64-amd64-xl-xsm 14 guest-saverestorefail REGR. vs. 106819 test-amd64-amd64-libvirt 14 guest-saverestorefail REGR. vs. 106819 test-amd64-i386-libvirt-xsm 14 guest-saverestorefail REGR. vs. 106819 test-amd64-amd64-migrupgrade 24 leak-check/check/dst_host fail REGR. vs. 106819 test-xtf-amd64-amd64-4 11 xtf-run fail REGR. vs. 106819 test-amd64-i386-qemuu-rhel6hvm-intel 9 redhat-install fail REGR. vs. 106819 test-amd64-i386-xl-xsm 14 guest-saverestorefail REGR. vs. 106819 test-amd64-amd64-xl 14 guest-saverestorefail REGR. vs. 106819 test-amd64-i386-xl 14 guest-saverestorefail REGR. vs. 106819 test-amd64-i386-xl-qemuu-ovmf-amd64 9 debian-hvm-install fail REGR. vs. 106819 test-amd64-i386-freebsd10-i386 13 guest-saverestore fail REGR. vs. 106819 test-amd64-i386-qemuu-rhel6hvm-amd 9 redhat-install fail REGR. vs. 106819 test-amd64-amd64-xl-multivcpu 14 guest-saverestore fail REGR. vs. 106819 test-amd64-i386-freebsd10-amd64 13 guest-saverestore fail REGR. vs. 106819 test-amd64-amd64-xl-qemut-debianhvm-amd64 9 debian-hvm-install fail REGR. vs. 106819 test-amd64-amd64-qemuu-nested-intel 9 debian-hvm-install fail REGR. vs. 106819 test-amd64-i386-libvirt 14 guest-saverestorefail REGR. vs. 106819 test-amd64-amd64-libvirt-pair 21 guest-migrate/src_host/dst_host fail REGR. vs. 106819 test-amd64-amd64-libvirt-qemuu-debianhvm-amd64-xsm 9 debian-hvm-install fail REGR. vs. 106819 test-amd64-amd64-xl-qemut-stubdom-debianhvm-amd64-xsm 9 debian-hvm-install fail REGR. vs. 106819 test-amd64-amd64-xl-credit2 14 guest-saverestorefail REGR. vs. 106819 test-amd64-i386-migrupgrade 24 leak-check/check/dst_host fail REGR. vs. 106819 test-amd64-i386-qemut-rhel6hvm-intel 9 redhat-install fail REGR. vs. 106819 test-amd64-amd64-pygrub 9 debian-di-installfail REGR. vs. 106819 test-amd64-amd64-amd64-pvgrub 9 debian-di-install fail REGR. vs. 106819 test-amd64-amd64-pair 21 guest-migrate/src_host/dst_host fail REGR. vs. 106819 test-amd64-i386-qemut-rhel6hvm-amd 9 redhat-install fail REGR. vs. 106819 test-amd64-amd64-xl-qcow2 9 debian-di-installfail REGR. vs. 106819 test-amd64-i386-xl-qemut-debianhvm-amd64-xsm 9 debian-hvm-install fail REGR. vs. 106819 test-amd64-amd64-xl-qemuu-debianhvm-amd64 9 debian-hvm-install fail REGR. vs. 106819 test-amd64-amd64-xl-qemuu-debianhvm-amd64-xsm 9 debian-hvm-install fail REGR. vs. 106819 test-amd64-i386-pair 21 guest-migrate/src_host/dst_host fail REGR. vs. 106819 test-amd64-amd64-libvirt-xsm 14 guest-saverestorefail REGR. vs. 106819 test-amd64-i386-xl-qemut-debianhvm-amd64 9 debian-hvm-install fail REGR. vs. 106819 test-amd64-i386-libvirt-pair 21 guest-migrate/src_host/dst_host fail REGR. vs. 106819 test-amd64-amd64-i386-pvgrub 9 debian-di-installfail REGR. vs. 106819 test-amd64-i386-xl-qemuu-debianhvm-amd64 9 debian-hvm-install fail REGR. vs. 106819 test-amd64-amd64-xl-qemut-debianhvm-amd64-xsm 9 debian-hvm-install fail REGR. vs. 106819 test-amd64-i386-libvirt-qemuu-debianhvm-amd64-xsm 9 debian-hvm-install fail REGR. vs. 106819 test-amd64-i386-xl-qemut-stubdom-debianhvm-amd64-xsm 9 debian-hvm-install fail REGR. vs. 106819 test-amd64-amd64-xl-qemuu-ovmf-amd64 9 debian-hvm-install fail REGR. vs. 106819 test-amd64-i386-xl-qemuu-debianhvm-amd64-xsm 9 debian-hvm-install fail REGR. vs. 106819 test-amd64-amd64-libvirt-vhd 9 debian-di-installfail REGR. vs. 106819 test-armhf-armhf-libvirt-xsm 14 guest-stop fail REGR. vs. 106819 test-amd64-i386-xl-raw9 debian-di-installfail REGR. vs. 106819 test-armhf-armhf-xl-arndale 15 guest-start/debian.repeat fail REGR. vs. 106819 test-armhf-armhf-libvirt 14 guest-stop fail REGR. vs. 106819 test-armhf-armhf-xl-credit2 15 guest-start/debian.repeat fail REGR. vs. 106819 test-armhf-armhf-xl-xsm 15 guest-start/debian.repeat fail REGR. vs. 106819
[Xen-devel] [ovmf baseline-only test] 71141: all pass
This run is configured for baseline tests only. flight 71141 ovmf real [real] http://osstest.xs.citrite.net/~osstest/testlogs/logs/71141/ Perfect :-) All tests in this flight passed as required version targeted for testing: ovmf 12b04866af2c348bf7e28e17b4ddc1eaf410211c baseline version: ovmf 4ef6c3850e66617df1ed35a4a390567d2bbf6b76 Last test of basis71139 2017-04-01 07:48:15 Z0 days Testing same since71141 2017-04-01 16:47:07 Z0 days1 attempts People who touched revisions under test: Jeff Fan Jiaxin Wu Ruiyu Ni Wu Jiaxin Yonghong Zhu Zhang Lubo Zhang, Lubo jobs: build-amd64-xsm pass build-i386-xsm pass build-amd64 pass build-i386 pass build-amd64-libvirt pass build-i386-libvirt pass build-amd64-pvopspass build-i386-pvops pass test-amd64-amd64-xl-qemuu-ovmf-amd64 pass test-amd64-i386-xl-qemuu-ovmf-amd64 pass sg-report-flight on osstest.xs.citrite.net logs: /home/osstest/logs images: /home/osstest/images Logs, config files, etc. are available at http://osstest.xs.citrite.net/~osstest/testlogs/logs Test harness code can be found at http://xenbits.xensource.com/gitweb?p=osstest.git;a=summary Push not applicable. commit 12b04866af2c348bf7e28e17b4ddc1eaf410211c Author: Zhang, Lubo Date: Fri Mar 24 16:43:04 2017 +0800 NetworkPkg: Fix some bugs related to iSCSI keyword configuration. Add check logic and error message for some keywords validity. show target address in URL format and MAC address correctly. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Zhang Lubo Cc: Ye Ting Cc: Fu Siyuan Cc: Wu Jiaxin Reviewed-by: Ye Ting commit e2d662c3135a5d420d6050f42e969e78f6bb19f1 Author: Jiaxin Wu Date: Sat Apr 1 08:21:03 2017 +0800 MdeModulePkg/DxeHttpLib: Avoid the pointless comparison of UINTN with zero UINTN is unsigned integer, so it's pointless to compare it with zero. Cc: Bi Dandan Cc: Zhang Lubo Cc: Ye Ting Cc: Fu Siyuan Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Wu Jiaxin Reviewed-by: Zhang Lubo commit bc7d95c00d9682ca96d8cee9a0be929c2e61a299 Author: Yonghong Zhu Date: Fri Mar 31 22:05:28 2017 +0800 BaseTools: Enhance StrDefs.h to include ImageDefs.h Enhance StrDefs.h to include ImageDefs.h for VfrCompiler to support IMAGE_TOKEN usage. Cc: Liming Gao Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Yonghong Zhu Reviewed-by: Liming Gao commit 5e06f1a00b5c325d3ced69ccfe4d307ad63975cf Author: Yonghong Zhu Date: Fri Mar 31 21:47:59 2017 +0800 BaseTools: Enhance expression to support some more operation Enhance expression to support some more operation that allowed in the spec, eg: *, /, %, <<, >>, ~. Cc: Liming Gao Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Yonghong Zhu Reviewed-by: Liming Gao commit 3edd7719299934b21fea56d564c3e3e3c2e0f493 Author: Ruiyu Ni Date: Sat Apr 1 13:14:57 2017 +0800 Vlv2TbltDevicePkg: Fix build failure by adding UefiBootManagerLib Recent ConPlatformDxe driver change depends on UefiBootManagerLib. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni commit 45f87893daa394e3eea3ce3ff1b520c8c8795aec Author: Ruiyu Ni Date: Fri Mar 31 22:23:13 2017 +0800 MdePkg/Shell.h: Update Shell version from 2.1 to 2.2 All the Shell 2.2 features are implemented except DMEM/MM changes which are pending on spec change. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni Cc: Kinney D Michael Cc: Jaben Carsey Reviewed-by: Liming Gao commit ee58438970c13329fe35d04e2432e0b7d2703190 Author: Jeff Fan Date: Tue Mar 28 14:01:24 2017 +0800 UefiCpuPkg/PiSmmCpuDxeSmm: Update saved SMM ranges check in SmmProfile SmmProfile feature required to protect all SMM ranges by structure mProtectionMemRangeTemplate. This update is to add additonal save SMM ranges into mProtectionMemRangeTemplate besides the range specified by mCpuHotPlugData.SmrrBase/mCpuHotPlugData.SmrrSiz. Cc: Jiewen Yao Cc: Michael Kinney Cc: Feng Tian
[Xen-devel] [qemu-mainline baseline-only test] 71140: tolerable trouble: blocked/broken/fail/pass
This run is configured for baseline tests only. flight 71140 qemu-mainline real [real] http://osstest.xs.citrite.net/~osstest/testlogs/logs/71140/ Failures :-/ but no regressions. Regressions which are regarded as allowable (not blocking): test-armhf-armhf-libvirt-xsm 13 saverestore-support-checkfail like 71136 test-armhf-armhf-libvirt 13 saverestore-support-checkfail like 71136 test-armhf-armhf-libvirt-raw 12 saverestore-support-checkfail like 71136 test-amd64-amd64-qemuu-nested-intel 16 debian-hvm-install/l1/l2 fail like 71136 test-amd64-i386-xl-qemuu-winxpsp3-vcpus1 9 windows-installfail like 71136 Tests which did not succeed, but are not blocking: test-arm64-arm64-libvirt-xsm 1 build-check(1) blocked n/a test-arm64-arm64-xl 1 build-check(1) blocked n/a build-arm64-libvirt 1 build-check(1) blocked n/a test-arm64-arm64-libvirt-qcow2 1 build-check(1) blocked n/a test-arm64-arm64-libvirt 1 build-check(1) blocked n/a test-arm64-arm64-xl-credit2 1 build-check(1) blocked n/a test-arm64-arm64-xl-rtds 1 build-check(1) blocked n/a test-arm64-arm64-xl-multivcpu 1 build-check(1) blocked n/a test-arm64-arm64-xl-xsm 1 build-check(1) blocked n/a build-arm64 2 hosts-allocate broken never pass build-arm64-pvops 2 hosts-allocate broken never pass build-arm64 3 capture-logs broken never pass build-arm64-pvops 3 capture-logs broken never pass build-arm64-xsm 2 hosts-allocate broken never pass build-arm64-xsm 3 capture-logs broken never pass test-armhf-armhf-libvirt-xsm 12 migrate-support-checkfail never pass test-armhf-armhf-xl-xsm 12 migrate-support-checkfail never pass test-armhf-armhf-xl-xsm 13 saverestore-support-checkfail never pass test-armhf-armhf-xl-midway 12 migrate-support-checkfail never pass test-armhf-armhf-xl-multivcpu 12 migrate-support-checkfail never pass test-armhf-armhf-xl-midway 13 saverestore-support-checkfail never pass test-armhf-armhf-xl-multivcpu 13 saverestore-support-checkfail never pass test-armhf-armhf-xl-credit2 12 migrate-support-checkfail never pass test-armhf-armhf-libvirt 12 migrate-support-checkfail never pass test-armhf-armhf-xl-credit2 13 saverestore-support-checkfail never pass test-armhf-armhf-xl 12 migrate-support-checkfail never pass test-armhf-armhf-xl 13 saverestore-support-checkfail never pass test-armhf-armhf-xl-rtds 12 migrate-support-checkfail never pass test-armhf-armhf-xl-rtds 13 saverestore-support-checkfail never pass test-amd64-amd64-libvirt 12 migrate-support-checkfail never pass test-amd64-i386-libvirt-xsm 12 migrate-support-checkfail never pass test-amd64-i386-libvirt 12 migrate-support-checkfail never pass test-amd64-amd64-libvirt-xsm 12 migrate-support-checkfail never pass test-armhf-armhf-libvirt-raw 11 migrate-support-checkfail never pass test-amd64-amd64-libvirt-qemuu-debianhvm-amd64-xsm 10 migrate-support-check fail never pass test-amd64-i386-libvirt-qemuu-debianhvm-amd64-xsm 10 migrate-support-check fail never pass test-armhf-armhf-xl-vhd 11 migrate-support-checkfail never pass test-armhf-armhf-xl-vhd 12 saverestore-support-checkfail never pass test-amd64-amd64-qemuu-nested-amd 16 debian-hvm-install/l1/l2 fail never pass test-amd64-amd64-libvirt-vhd 11 migrate-support-checkfail never pass test-amd64-amd64-xl-qemuu-win7-amd64 16 guest-stop fail never pass test-amd64-i386-xl-qemuu-win7-amd64 16 guest-stop fail never pass version targeted for testing: qemuu95b31d709ba343ad237c3630047ee7438bac4065 baseline version: qemuua0ee3797bf4917b1b7a4554a4dffbb45f387f087 Last test of basis71136 2017-04-01 04:17:56 Z0 days Testing same since71140 2017-04-01 16:17:38 Z0 days1 attempts People who touched revisions under test: Alex Williamson Alexander Graf Dr. David Alan Gilbert Eric Auger Iwona Kotlarska Michael Roth Peter Maydell Sameeh Jubran Xiong Zhang jobs: build-amd64-xsm pass build-arm64-xsm broken build-armhf-xsm pass build-i386-xsm pass build-amd64 pass build-arm64
[Xen-devel] [linux-linus test] 107075: regressions - FAIL
flight 107075 linux-linus real [real] http://logs.test-lab.xenproject.org/osstest/logs/107075/ Regressions :-( Tests which did not succeed and are blocking, including tests which could not be run: test-armhf-armhf-xl-credit2 11 guest-start fail REGR. vs. 59254 test-armhf-armhf-xl-arndale 11 guest-start fail REGR. vs. 59254 test-armhf-armhf-libvirt-xsm 11 guest-start fail REGR. vs. 59254 test-armhf-armhf-xl-cubietruck 11 guest-start fail REGR. vs. 59254 test-armhf-armhf-libvirt 11 guest-start fail REGR. vs. 59254 test-armhf-armhf-xl 11 guest-start fail REGR. vs. 59254 test-armhf-armhf-xl-xsm 11 guest-start fail REGR. vs. 59254 test-armhf-armhf-xl-multivcpu 11 guest-start fail REGR. vs. 59254 Regressions which are regarded as allowable (not blocking): test-armhf-armhf-xl-rtds 11 guest-start fail REGR. vs. 59254 test-amd64-amd64-xl-rtds 9 debian-installfail REGR. vs. 59254 test-amd64-i386-rumprun-i386 16 rumprun-demo-xenstorels/xenstorels.repeat fail baseline untested test-armhf-armhf-xl-vhd 9 debian-di-install fail baseline untested test-armhf-armhf-libvirt-raw 9 debian-di-install fail baseline untested test-amd64-i386-xl-qemuu-win7-amd64 16 guest-stop fail like 59254 test-amd64-amd64-xl-qemut-win7-amd64 16 guest-stop fail like 59254 test-amd64-amd64-xl-qemuu-win7-amd64 16 guest-stop fail like 59254 test-amd64-i386-xl-qemut-win7-amd64 16 guest-stop fail like 59254 Tests which did not succeed, but are not blocking: test-arm64-arm64-libvirt-xsm 1 build-check(1) blocked n/a test-arm64-arm64-xl 1 build-check(1) blocked n/a build-arm64-libvirt 1 build-check(1) blocked n/a test-arm64-arm64-libvirt-qcow2 1 build-check(1) blocked n/a test-arm64-arm64-libvirt 1 build-check(1) blocked n/a test-arm64-arm64-xl-credit2 1 build-check(1) blocked n/a test-arm64-arm64-xl-rtds 1 build-check(1) blocked n/a test-arm64-arm64-xl-multivcpu 1 build-check(1) blocked n/a test-arm64-arm64-xl-xsm 1 build-check(1) blocked n/a test-amd64-i386-libvirt-xsm 12 migrate-support-checkfail never pass test-amd64-amd64-libvirt-xsm 12 migrate-support-checkfail never pass build-arm64-xsm 5 xen-buildfail never pass test-amd64-amd64-libvirt 12 migrate-support-checkfail never pass test-amd64-amd64-libvirt-qemuu-debianhvm-amd64-xsm 10 migrate-support-check fail never pass test-amd64-i386-libvirt-qemuu-debianhvm-amd64-xsm 10 migrate-support-check fail never pass test-amd64-amd64-libvirt-vhd 11 migrate-support-checkfail never pass test-amd64-amd64-qemuu-nested-amd 16 debian-hvm-install/l1/l2 fail never pass test-amd64-i386-libvirt 12 migrate-support-checkfail never pass build-arm64 5 xen-buildfail never pass version targeted for testing: linuxf9799ad21b5e4a41633f54dfab407ebb37abbd8a baseline version: linux45820c294fe1b1a9df495d57f40585ef2d069a39 Last test of basis59254 2015-07-09 04:20:48 Z 632 days Failing since 59348 2015-07-10 04:24:05 Z 631 days 369 attempts Testing same since 107053 2017-04-01 03:47:46 Z0 days2 attempts 8119 people touched revisions under test, not listing them all jobs: build-amd64-xsm pass build-arm64-xsm fail build-armhf-xsm pass build-i386-xsm pass build-amd64 pass build-arm64 fail build-armhf pass build-i386 pass build-amd64-libvirt pass build-arm64-libvirt blocked build-armhf-libvirt pass build-i386-libvirt pass build-amd64-pvopspass build-arm64-pvopspass build-armhf-pvopspass build-i386-pvops pass build-amd64-rumprun pass build-i386-rumprun pass test-
Re: [Xen-devel] [PATCH v3 00/26] arm64: Dom0 ITS emulation
On 31/03/2017 19:04, Andre Przywara wrote:
Hi,
Hi Andre,
The time I planned for the indirect device table was spent on the above two
items, so I will write this now while the reviewers are on it.
I tried to check every error return and kick out every signed int.
Also the bug that Vijay reported has been fixed (I hope).
While the two command line parameters are still around, the Kconfig
options have been removed.
I tried to separate functions between the existing VGIC and the LPI
and ITS code parts. However there is always some connection which prevents
a clean separation (I tried several approaches).
I checked using the vgic_ops structure, but that feels like abuse for some
functions, also has issues since a GICv3 and a GICv3 with ITS are not
really separate (both could have LPIs), and the latter would always be a
superset of the former, which duplicates code and makes a separate
vgic_ops questionable.
There are reasons why I asked no direct call to {,v}GICv3 specific
functions in the common code. As you may know common code is very
generic and here to abstract the implementation of a specific GIC
controller. It will become quickly unmaintainable if we start to do that.
Do you think the irqchip Linux maintainers will accept direct GICv3 call
in the generic code? They will clearly say no and probably not in a very
politely way, this is similar here.
Regarding the vgic_ops, I asked to have separate vgic ops for vGICv3 and
vGICv3 with ITS because some code path differs. For instance we don't
support LPIs without ITS yet. So it makes sense to avoid LPIs code to be
called by mistake without ITS. Duplicating a vgic_ops (at max 10 lines)
is not much compare to the potential issues.
You also seem to assume that Xen compiled with ITS will only run on
GICv3 ITS platform. This is not true at all. The same binary can run on
a wide range of platform.
This is not the first time I asked that. So let me be clear, I will not
accept any call to specific functions nor #ifdef CONFIG_HAS_ITS in
common code. It is a direct NAck from me.
Cheers,
--
Julien Grall
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[Xen-devel] [xen-unstable test] 107069: regressions - FAIL
flight 107069 xen-unstable real [real] http://logs.test-lab.xenproject.org/osstest/logs/107069/ Regressions :-( Tests which did not succeed and are blocking, including tests which could not be run: test-armhf-armhf-libvirt-xsm 7 host-ping-check-xen fail REGR. vs. 107034 Regressions which are regarded as allowable (not blocking): test-armhf-armhf-libvirt 13 saverestore-support-checkfail like 107034 test-amd64-amd64-xl-qemut-win7-amd64 16 guest-stopfail like 107034 test-amd64-i386-xl-qemuu-win7-amd64 16 guest-stop fail like 107034 test-amd64-i386-xl-qemut-win7-amd64 16 guest-stop fail like 107034 test-amd64-amd64-xl-qemuu-win7-amd64 16 guest-stopfail like 107034 test-armhf-armhf-libvirt-raw 12 saverestore-support-checkfail like 107034 test-amd64-amd64-xl-rtds 9 debian-install fail like 107034 Tests which did not succeed, but are not blocking: test-arm64-arm64-libvirt-xsm 1 build-check(1) blocked n/a test-arm64-arm64-xl 1 build-check(1) blocked n/a build-arm64-libvirt 1 build-check(1) blocked n/a test-arm64-arm64-libvirt-qcow2 1 build-check(1) blocked n/a test-arm64-arm64-libvirt 1 build-check(1) blocked n/a test-arm64-arm64-xl-credit2 1 build-check(1) blocked n/a test-arm64-arm64-xl-rtds 1 build-check(1) blocked n/a test-arm64-arm64-xl-multivcpu 1 build-check(1) blocked n/a test-arm64-arm64-xl-xsm 1 build-check(1) blocked n/a test-amd64-i386-libvirt 12 migrate-support-checkfail never pass test-amd64-i386-libvirt-xsm 12 migrate-support-checkfail never pass test-amd64-amd64-libvirt-xsm 12 migrate-support-checkfail never pass test-amd64-amd64-libvirt 12 migrate-support-checkfail never pass build-arm64 5 xen-buildfail never pass build-arm64-xsm 5 xen-buildfail never pass test-amd64-amd64-libvirt-qemuu-debianhvm-amd64-xsm 10 migrate-support-check fail never pass test-amd64-i386-libvirt-qemuu-debianhvm-amd64-xsm 10 migrate-support-check fail never pass build-arm64-pvops 5 kernel-build fail never pass test-armhf-armhf-xl-arndale 12 migrate-support-checkfail never pass test-armhf-armhf-xl-arndale 13 saverestore-support-checkfail never pass test-amd64-amd64-libvirt-vhd 11 migrate-support-checkfail never pass test-armhf-armhf-xl-xsm 12 migrate-support-checkfail never pass test-armhf-armhf-xl-xsm 13 saverestore-support-checkfail never pass test-armhf-armhf-xl-multivcpu 12 migrate-support-checkfail never pass test-armhf-armhf-xl-multivcpu 13 saverestore-support-checkfail never pass test-amd64-amd64-qemuu-nested-amd 16 debian-hvm-install/l1/l2 fail never pass test-armhf-armhf-libvirt 12 migrate-support-checkfail never pass test-armhf-armhf-xl 12 migrate-support-checkfail never pass test-armhf-armhf-xl 13 saverestore-support-checkfail never pass test-armhf-armhf-xl-credit2 12 migrate-support-checkfail never pass test-armhf-armhf-xl-credit2 13 saverestore-support-checkfail never pass test-armhf-armhf-xl-cubietruck 12 migrate-support-checkfail never pass test-armhf-armhf-xl-cubietruck 13 saverestore-support-checkfail never pass test-armhf-armhf-xl-rtds 12 migrate-support-checkfail never pass test-armhf-armhf-xl-rtds 13 saverestore-support-checkfail never pass test-armhf-armhf-libvirt-raw 11 migrate-support-checkfail never pass test-armhf-armhf-xl-vhd 11 migrate-support-checkfail never pass test-armhf-armhf-xl-vhd 12 saverestore-support-checkfail never pass version targeted for testing: xen 41630eb1b615158af42f4468236457fd3f8a6819 baseline version: xen 35673d2419af4fde4f235414937bec38864db295 Last test of basis 107034 2017-03-31 14:13:27 Z1 days Testing same since 107069 2017-04-01 07:21:25 Z0 days1 attempts People who touched revisions under test: Andrew Cooper Wei Chen jobs: build-amd64-xsm pass build-arm64-xsm fail build-armhf-xsm pass build-i386-xsm pass build-amd64-xtf pass build-amd64 pass build-arm64 fail build-armhf pass b
[Xen-devel] [xen-unstable baseline-only test] 71138: tolerable trouble: blocked/broken/fail/pass
This run is configured for baseline tests only. flight 71138 xen-unstable real [real] http://osstest.xs.citrite.net/~osstest/testlogs/logs/71138/ Failures :-/ but no regressions. Regressions which are regarded as allowable (not blocking): test-armhf-armhf-libvirt13 saverestore-support-check fail blocked in 71133 test-armhf-armhf-libvirt-xsm 13 saverestore-support-check fail blocked in 71133 test-armhf-armhf-libvirt-raw 12 saverestore-support-check fail blocked in 71133 test-amd64-i386-xl-qemuu-debianhvm-amd64 14 guest-saverestore.2 fail blocked in 71133 test-amd64-amd64-qemuu-nested-intel 16 debian-hvm-install/l1/l2 fail blocked in 71133 test-amd64-i386-xl-qemuu-win7-amd64 16 guest-stopfail blocked in 71133 test-amd64-i386-xl-qemut-winxpsp3-vcpus1 9 windows-install fail blocked in 71133 test-amd64-i386-xl-qemuu-winxpsp3-vcpus1 9 windows-install fail blocked in 71133 test-amd64-amd64-xl-qemut-winxpsp3 9 windows-installfail blocked in 71133 Tests which did not succeed, but are not blocking: test-arm64-arm64-libvirt-xsm 1 build-check(1) blocked n/a test-arm64-arm64-xl 1 build-check(1) blocked n/a build-arm64-libvirt 1 build-check(1) blocked n/a test-arm64-arm64-libvirt-qcow2 1 build-check(1) blocked n/a test-arm64-arm64-libvirt 1 build-check(1) blocked n/a test-arm64-arm64-xl-credit2 1 build-check(1) blocked n/a test-arm64-arm64-xl-rtds 1 build-check(1) blocked n/a test-arm64-arm64-xl-multivcpu 1 build-check(1) blocked n/a test-arm64-arm64-xl-xsm 1 build-check(1) blocked n/a build-arm64 2 hosts-allocate broken never pass build-arm64-pvops 2 hosts-allocate broken never pass build-arm64-xsm 2 hosts-allocate broken never pass build-arm64-xsm 3 capture-logs broken never pass build-arm64 3 capture-logs broken never pass build-arm64-pvops 3 capture-logs broken never pass test-armhf-armhf-xl-xsm 12 migrate-support-checkfail never pass test-armhf-armhf-xl-xsm 13 saverestore-support-checkfail never pass test-armhf-armhf-xl-midway 12 migrate-support-checkfail never pass test-armhf-armhf-xl-midway 13 saverestore-support-checkfail never pass test-armhf-armhf-xl-credit2 12 migrate-support-checkfail never pass test-armhf-armhf-xl-credit2 13 saverestore-support-checkfail never pass test-armhf-armhf-xl-multivcpu 12 migrate-support-checkfail never pass test-armhf-armhf-xl-multivcpu 13 saverestore-support-checkfail never pass test-armhf-armhf-libvirt 12 migrate-support-checkfail never pass test-armhf-armhf-libvirt-xsm 12 migrate-support-checkfail never pass test-armhf-armhf-xl 12 migrate-support-checkfail never pass test-armhf-armhf-xl 13 saverestore-support-checkfail never pass test-amd64-amd64-libvirt 12 migrate-support-checkfail never pass test-amd64-amd64-libvirt-xsm 12 migrate-support-checkfail never pass test-armhf-armhf-xl-rtds 12 migrate-support-checkfail never pass test-armhf-armhf-xl-rtds 13 saverestore-support-checkfail never pass test-amd64-i386-libvirt 12 migrate-support-checkfail never pass test-armhf-armhf-libvirt-raw 11 migrate-support-checkfail never pass test-amd64-i386-libvirt-xsm 12 migrate-support-checkfail never pass test-amd64-i386-libvirt-qemuu-debianhvm-amd64-xsm 10 migrate-support-check fail never pass test-armhf-armhf-xl-vhd 11 migrate-support-checkfail never pass test-armhf-armhf-xl-vhd 12 saverestore-support-checkfail never pass test-amd64-amd64-libvirt-qemuu-debianhvm-amd64-xsm 10 migrate-support-check fail never pass test-amd64-amd64-libvirt-vhd 11 migrate-support-checkfail never pass test-amd64-amd64-qemuu-nested-amd 16 debian-hvm-install/l1/l2 fail never pass test-amd64-i386-xl-qemut-win7-amd64 16 guest-stop fail never pass test-amd64-amd64-xl-qemuu-win7-amd64 16 guest-stop fail never pass test-amd64-amd64-xl-qemut-win7-amd64 16 guest-stop fail never pass version targeted for testing: xen 35673d2419af4fde4f235414937bec38864db295 baseline version: xen 3bdb14004b9fe8c35e4961f8a7c73c19f0fb4365 Last test of basis71133 2017-03-31 12:15:13 Z1 days Testing same since71138 2017-04-01 07:19:18 Z0 days1 attempts People who touched revisions under test: Al Stone Bob Moore Jan Beulich Lv Zheng Rafael J. Wysocki Sameer Goel jobs: build-amd64-xsm
Re: [Xen-devel] raisin and minios stubdom
2017-04-01 08:19 keltezéssel, Géza Gémes írta:
2017. márc. 31. 16:15 ezt írta ("Juergen Gross" >):
On 31/03/17 16:05, Konrad Rzeszutek Wilk wrote:
> On Thu, Mar 30, 2017 at 07:42:48PM +0200, Gémes Géza wrote:
>>
>>> On Mon, Mar 27, 2017 at 09:28:14PM +0200, Gémes Géza wrote:
Hi,
Currently the xen build system has optional support for
building a minios
(+needed libraries and tools) based stubdom.
What is your opinion about moving support for building this
into raisin and
once that is stable drop support in the xen build system?
>>> Why? I do like doing 'make' and 'make install' and it doing
everything
>>> for me.
>>>
Cheers,
Geza
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>>
>> Because it means that xen build needs to download and build a
lot of 3PP
>> components. Raisin is already designed to do so (it already
builds qemu-xen,
>
> If you do 'make src-tarball' it will do that for you - and you
can package
> all of that in a tarball.
>
>> qemu-traditional, libvirt and a few others). I think building
anything
>> besides xen proper would fit its scope better.
>
> OK, but that does not square well with RPM build systems. Those
are interested
> in building just one component (xen+toolstack+its extra pieces).
Using
> raisin to build everything is not going to fly.
>
> (Also distros like to seperate componets out - so they build
qemu-upstream
> seperate - which is used by Xen - and they could also do it for
MiniOS
> if they were spec files for it and such).
There are only few stubdoms you can build without the Xen tree. How
would you do so for e.g. xenstore-stubdom needing the Xenstore sources
to be built? Several stubdoms need libxc built for stubdom included.
And you want to have a build error if e.g. a libxc modification is
breaking stubdom build.
Juergen
Hi,
Raisin already builds xen too, so it has all the dependencies ready.
Regarding the problem of breaking stubdom build by libxc changes I
think those can be prevented if we introduce osstests for raisin
build. Maybe we should start with that, adding raisin to the osstest
framework.
Opinions?
Cheers
Géza
Regarding building distro rpms or debs with raisin that was never the
scope of it. Raisin intends to be a quick method of building xen + a set
of tools related to it, primarily for development purposes
(https://wiki.xenproject.org/wiki/Raisin and
https://blog.xenproject.org/2015/06/28/project-raisin-raise-xen/)
Cheers,
Géza
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[Xen-devel] [xen-4.6-testing bisection] complete test-amd64-i386-rumprun-i386
branch xen-4.6-testing
xenbranch xen-4.6-testing
job test-amd64-i386-rumprun-i386
testid guest-destroy
Tree: linux git://xenbits.xen.org/linux-pvops.git
Tree: linuxfirmware git://xenbits.xen.org/osstest/linux-firmware.git
Tree: qemu git://xenbits.xen.org/qemu-xen-traditional.git
Tree: qemuu git://xenbits.xen.org/qemu-xen.git
Tree: rumprun git://xenbits.xen.org/osstest/rumprun.git
Tree: rumprun_buildrumpsh https://github.com/rumpkernel/buildrump.sh
Tree: rumprun_netbsdsrc https://github.com/rumpkernel/src-netbsd
Tree: xen git://xenbits.xen.org/xen.git
*** Found and reproduced problem changeset ***
Bug is in tree: xen git://xenbits.xen.org/xen.git
Bug introduced: 7ff6d9fc19ef88d2ca3304a312c0e8a46b61f546
Bug not present: 7017321d9b7b23adb50cad66d55ae526ab5d9fe1
Last fail repro: http://logs.test-lab.xenproject.org/osstest/logs/107080/
commit 7ff6d9fc19ef88d2ca3304a312c0e8a46b61f546
Author: Dario Faggioli
Date: Fri Mar 31 09:03:32 2017 +0200
xen: sched: don't call hooks of the wrong scheduler via VCPU2OP
Within context_saved(), we call the context_saved hook,
and we use VCPU2OP() to determine from what scheduler.
VCPU2OP uses DOM2OP, which uses d->cpupool, which is
NULL when d is the idle domain. And in that case,
DOM2OP just returns ops, the scheduler of cpupool0.
Therefore, if:
- cpupool0's scheduler defines context_saved (like
Credit2 and RTDS do),
- we are not in cpupool0 (i.e., our scheduler is
not ops),
- we are context switching from idle,
we call VCPU2OP(idle_vcpu), which means
DOM2OP(idle->cpupool), which is ops.
Therefore, we both:
- check if context_saved is defined in the wrong
scheduler;
- if yes, call the wrong one.
When using Credit2 at boot, and also Credit2 in
the other cpupool, this is wrong but innocuous,
because it only involves the idle vcpus.
When using Credit2 at boot, and Credit1 in the
other cpupool, this is *totally* wrong, and
it's by chance it does not explode!
When using Credit2 and other schedulers I'm
developping, I hit the following assert (in
sched_credit2.c, on a CPU inside a cpupool that
does not use Credit2):
csched2_context_saved()
{
...
ASSERT(!vcpu_on_runq(svc));
...
}
Fix this by dealing explicitly, in VCPU2OP, with
idle vcpus, returning the scheduler of the pCPU
they (always) run on.
Signed-off-by: Dario Faggioli
Reviewed-by: Juergen Gross
Reviewed-by: George Dunlap
master commit: a3653e6a279213ba4e883b2252415dc98633106a
master date: 2017-03-27 14:28:05 +0100
For bisection revision-tuple graph see:
http://logs.test-lab.xenproject.org/osstest/results/bisect/xen-4.6-testing/test-amd64-i386-rumprun-i386.guest-destroy.html
Revision IDs in each graph node refer, respectively, to the Trees above.
Running cs-bisection-step
--graph-out=/home/logs/results/bisect/xen-4.6-testing/test-amd64-i386-rumprun-i386.guest-destroy
--summary-out=tmp/107080.bisection-summary --basis-template=106819
--blessings=real,real-bisect xen-4.6-testing test-amd64-i386-rumprun-i386
guest-destroy
Searching for failure / basis pass:
107042 fail [host=huxelrebe0] / 106819 [host=italia1] 106663 [host=italia0]
106529 [host=elbling0] 105991 [host=pinot1] 105936 [host=italia0] 105831
[host=rimava1] 105816 [host=fiano0] 105685 ok.
Failure / basis pass flights: 107042 / 105685
(tree with no url: minios)
(tree with no url: ovmf)
(tree with no url: seabios)
Tree: linux git://xenbits.xen.org/linux-pvops.git
Tree: linuxfirmware git://xenbits.xen.org/osstest/linux-firmware.git
Tree: qemu git://xenbits.xen.org/qemu-xen-traditional.git
Tree: qemuu git://xenbits.xen.org/qemu-xen.git
Tree: rumprun git://xenbits.xen.org/osstest/rumprun.git
Tree: rumprun_buildrumpsh https://github.com/rumpkernel/buildrump.sh
Tree: rumprun_netbsdsrc https://github.com/rumpkernel/src-netbsd
Tree: xen git://xenbits.xen.org/xen.git
Latest b65f2f457c49b2cfd7967c34b7a0b04c25587f13
c530a75c1e6a472b0eb9558310b518f0dfcd8860
57ca3f4a3092695dd553d3ff4540f5559b1c8fc7
44f3d4e6448e37588248db784193b7a047add65a
c7f2f016becc1cd0e85da6e1b25a8e7f9fb2aa74
9c9b022cb2115734935e50600c867a3bc230b32c
b8b951e911a2fc555848a2785a9998bc128530b6
7ff6d9fc19ef88d2ca3304a312c0e8a46b61f546
Basis pass b65f2f457c49b2cfd7967c34b7a0b04c25587f13
c530a75c1e6a472b0eb9558310b518f0dfcd8860
a7fd3717d99944530b04130f050e83402e64afed
ba9175c5bde6796851d3b9d888ee488fd0257d05
39a97f37a85e44c69b662f6b97b688fbe892603b
21c6286247478dd186426b7be0c36534525ad6c9
b8b951e911a2fc555848a2785a9998bc128530b6
576f319a804bce8c9a7fb70a042f873f5eaf0151
Generating revisions with ./adhoc-revtuple-generator
git://xenbits.xen.org/linux-pvops.git#b65f2f457c49b2cfd7967c34b7a0b04c25587f
Re: [Xen-devel] [PATCH RFC] x86/emulate: implement hvmemul_cmpxchg() with an actual CMPXCHG
On 03/31/2017 06:04 PM, Jan Beulich wrote:
On 31.03.17 at 17:01, wrote:
>> On 03/31/2017 05:46 PM, Jan Beulich wrote:
>> On 31.03.17 at 11:56, wrote:
On 03/31/2017 10:34 AM, Jan Beulich wrote:
On 31.03.17 at 08:17, wrote:
>> On 03/30/2017 06:47 PM, Jan Beulich wrote:
Speaking of emulated MMIO, I've got this when the guest was crashing
immediately (pre RETRY loop):
MMIO emulation failed: d3v8 32bit @ 0008:82679f3c -> f0 0f ba 30 00 72
07 8b cb e8 da 4b ff ff 8b 45
>>>
>>> That's a BTR, which we should be emulating fine. More information
>>> would need to be collected to have a chance to understand what
>>> might be going one (first of all the virtual and physical memory
>>> address this was trying to act on).
>>
>> Right, the BTR part should be fine, but I think the LOCK part is what's
>> causing the issue. I've done a few more test runs to see what return
>> RETRY (dumping the instruction with an "(r)" prefix to distinguish from
>> the UNHANDLEABLE dump), and a couple of instructions return RETRY (BTR
>> and XADD, both LOCK-prefixed, which means they now involve CMPXCHG
>> handler, which presumably now fails - possibly simply because it's
>> always LOCKed in my patch):
>
> Well, all of that looks to be expected behavior. I'm afraid I don't see
> how this information helps understanding the MMIO emulation failure
> above.
I've managed to obtain this log of emulation errors:
https://pastebin.com/Esy1SkHx
The "virtual address" lines that are not followed by any "Mem event"
line correspond to CMXCHG_FAILED return codes.
The very last line is a MMIO emulation failed.
It's probably important that this happens with the model where
hvm_emulate_one_vm_event() does _not_ re-try the emulation until it
succeeds. The other model allows me to go further with the guest, but
eventually I get timeout-related BSODs or the guest becomes unresponsive.
>>>
>>> Interesting. You didn't clarify what the printed "offset" values are,
>>> and it doesn't look like these have any correlation with the underlying
>>> (guest) physical address, which we would also want to see. And then
>>> it strikes me as odd that in these last lines
>>>
>>> (XEN) Mem event (RETRY) emulation failed: d5v8 32bit @ 0008:826bb861 -> f0
>>> 0f
>> ba 30 00 72 07 8b cb e8 da 4b ff ff 8b 45
>>> (XEN) virtual address: 0xffd080f0, offset: 4291854576
>>> (XEN) MMIO emulation failed: d5v8 32bit @ 0008:82655f3c -> f0 0f ba 30 00
>>> 72
>> 07 8b cb e8 da 4b ff ff 8b 45
>>>
>>> the instruction pointers and virtual addresses are different, but the
>>> code bytes are exactly the same. This doesn't seem very likely, so I
>>> wonder whether there's an issue with us wrongly re-using previously
>>> fetched insn bytes. (Of course I'd be happy to be proven wrong with
>>> this guessing, by you checking the involved binary/ies.)
>>
>> Offset is the actual value of the "offset" parameter of
>> hvmemul_cmpxchg().
>
> That's not very useful then, as for flat segments "offset" ==
> "virtual address" (i.e. you merely re-print in decimal what you've
> already printed in hex).
The attached patch (a combination of your patch and mine) produces the
following output when booting a Windows 7 32-bit guest with monitoring:
https://pastebin.com/ayiFmj1N
The failed MMIO emulation is caused by a mapping failure due to the
"!nestedhvm_vcpu_in_guestmode(curr) && hvm_mmio_internal(gpa)" condition
being true in hvmemul_vaddr_to_mfn(). I've ripped that off from
__hvm_copy() but it looks like that might not be the right way to use it.
Thanks,
Razvan
diff --git a/xen/arch/x86/hvm/emulate.c b/xen/arch/x86/hvm/emulate.c
index 2d92957..f6244af 100644
--- a/xen/arch/x86/hvm/emulate.c
+++ b/xen/arch/x86/hvm/emulate.c
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -1029,6 +1030,86 @@ static int hvmemul_wbinvd_discard(
return X86EMUL_OKAY;
}
+static int hvmemul_vaddr_to_mfn(
+unsigned long addr,
+mfn_t *mfn,
+uint32_t pfec,
+struct x86_emulate_ctxt *ctxt)
+{
+paddr_t gpa = addr & ~PAGE_MASK;
+struct page_info *page;
+p2m_type_t p2mt;
+unsigned long gfn;
+struct vcpu *curr = current;
+struct hvm_emulate_ctxt *hvmemul_ctxt =
+container_of(ctxt, struct hvm_emulate_ctxt, ctxt);
+
+gfn = paging_gva_to_gfn(curr, addr, &pfec);
+
+printk("gfn: 0x%lx\n", gfn);
+
+if ( gfn == gfn_x(INVALID_GFN) )
+{
+pagefault_info_t pfinfo = {};
+
+if ( ( pfec & PFEC_page_paged ) || ( pfec & PFEC_page_shared ) )
+return X86EMUL_RETRY;
+
+pfinfo.linear = addr;
+pfinfo.ec = pfec;
+
+x86_emul_pagefault(pfinfo.ec, pfinfo.linear, &hvmemul_ctxt->ctxt);
+return X86EMUL_EXCEPTION;
+}
+
+gpa |= (paddr_t)gfn << PAGE_SHIFT;
+
+/*
+ *
[Xen-devel] [ovmf baseline-only test] 71139: all pass
This run is configured for baseline tests only. flight 71139 ovmf real [real] http://osstest.xs.citrite.net/~osstest/testlogs/logs/71139/ Perfect :-) All tests in this flight passed as required version targeted for testing: ovmf 4ef6c3850e66617df1ed35a4a390567d2bbf6b76 baseline version: ovmf de87f23291620d36d69ec55ea53a1c38b8780f0b Last test of basis71131 2017-03-31 09:18:57 Z1 days Testing same since71139 2017-04-01 07:48:15 Z0 days1 attempts People who touched revisions under test: Ard Biesheuvel Chen A Chen Laszlo Ersek Marc Zyngier Ruiyu Ni jobs: build-amd64-xsm pass build-i386-xsm pass build-amd64 pass build-i386 pass build-amd64-libvirt pass build-i386-libvirt pass build-amd64-pvopspass build-i386-pvops pass test-amd64-amd64-xl-qemuu-ovmf-amd64 pass test-amd64-i386-xl-qemuu-ovmf-amd64 pass sg-report-flight on osstest.xs.citrite.net logs: /home/osstest/logs images: /home/osstest/images Logs, config files, etc. are available at http://osstest.xs.citrite.net/~osstest/testlogs/logs Test harness code can be found at http://xenbits.xensource.com/gitweb?p=osstest.git;a=summary Push not applicable. commit 4ef6c3850e66617df1ed35a4a390567d2bbf6b76 Author: Ruiyu Ni Date: Fri Mar 31 22:04:17 2017 +0800 UefiCpuPkg/MtrrLib: Fix GCC build failure Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni commit 47454e238cf9d716af728ca9b85ad314a4adcfc9 Author: Chen A Chen Date: Wed Mar 29 10:23:09 2017 +0800 ShellPkg/setvar: Support data format in Shell 2.2 spec Shell 2.2 spec defines =0x/=0X, =H/=h, =S, =L and =P for hex number, hex array, ascii string, unicode string and device path data. The patch adds such support. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chen A Chen Reviewed-by: Ruiyu Ni Cc: Michael D Kinney Cc: Jaben Carsey Cc: Jeff Fan commit 12c71010b84ac910972f738eb5fd0dfd7b688413 Author: Ard Biesheuvel Date: Wed Mar 29 12:05:01 2017 +0100 EmbeddedPkg/DtPlatformDxe: load platform DTB via new library To give platforms some room to decide which DTB is suitable and where to load it from, load the DTB image indirectly via the new DtPlatformDtbLoaderLib library class. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-by: Laszlo Ersek commit 4c725c8959900794533c6055bedfcc153a1a6a5e Author: Ard Biesheuvel Date: Fri Mar 31 11:35:13 2017 +0100 EmbeddedPkg: add base DtPlatformDtbLoaderLib implementation Introduce an implementation of the new DtPlatformDtbLoaderLib library class that simply retrieves the first raw section of an FV file named 'gDtPlatformDefaultDtbFileGuid'. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-by: Laszlo Ersek commit 449a5df455ed74cdaa9a95e318388531dc073948 Author: Ard Biesheuvel Date: Fri Mar 31 11:32:36 2017 +0100 EmbeddedPkg: add DtPlatformDtbLoaderLib library class To abstract the way a platform reasons about which DTB is appropriate, and the way it ultimately supplies the DTB image, introduce a new library class to encapsulate this functionality. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-by: Laszlo Ersek commit f07cc45883d0562a7edaf57023e71a2ad601cf2e Author: Ard Biesheuvel Date: Fri Mar 31 13:16:40 2017 +0100 EmbeddedPkg: add DtPlatformDxe to .dsc file Add the new DtPlatformDxe driver to EmbeddedPkg's .dsc file so that we can build it outside the context of a platform. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-by: Laszlo Ersek commit 7e5f1b673870897eeb1a9fba1c2b006ca366579c Author: Ard Biesheuvel Date: Wed Mar 29 18:50:39 2017 +0100 ArmVirtPkg/PlatformHasAcpiDtDxe: allow guest level ACPI disable override In general, we should not present two separate (and inevitably different) hardware descriptions to the OS, in the form of ACPI tables and a device tree blob. For this reason, we recently added the logic to ArmVirtQemu to only expose t
[Xen-devel] [qemu-mainline test] 107055: tolerable FAIL - PUSHED
flight 107055 qemu-mainline real [real] http://logs.test-lab.xenproject.org/osstest/logs/107055/ Failures :-/ but no regressions. Regressions which are regarded as allowable (not blocking): test-amd64-i386-xl-qemuu-win7-amd64 16 guest-stop fail like 107025 test-armhf-armhf-libvirt-raw 12 saverestore-support-checkfail like 107025 test-amd64-amd64-xl-qemuu-win7-amd64 16 guest-stopfail like 107025 test-armhf-armhf-libvirt-xsm 13 saverestore-support-checkfail like 107025 test-amd64-amd64-xl-rtds 9 debian-install fail like 107025 test-armhf-armhf-libvirt 13 saverestore-support-checkfail like 107025 Tests which did not succeed, but are not blocking: test-arm64-arm64-libvirt-xsm 1 build-check(1) blocked n/a test-arm64-arm64-xl 1 build-check(1) blocked n/a build-arm64-libvirt 1 build-check(1) blocked n/a test-arm64-arm64-libvirt-qcow2 1 build-check(1) blocked n/a test-arm64-arm64-libvirt 1 build-check(1) blocked n/a test-arm64-arm64-xl-credit2 1 build-check(1) blocked n/a test-arm64-arm64-xl-rtds 1 build-check(1) blocked n/a test-arm64-arm64-xl-multivcpu 1 build-check(1) blocked n/a test-arm64-arm64-xl-xsm 1 build-check(1) blocked n/a build-arm64-xsm 5 xen-buildfail never pass test-amd64-i386-libvirt 12 migrate-support-checkfail never pass test-amd64-amd64-libvirt-xsm 12 migrate-support-checkfail never pass test-amd64-i386-libvirt-xsm 12 migrate-support-checkfail never pass build-arm64 5 xen-buildfail never pass test-amd64-amd64-libvirt-qemuu-debianhvm-amd64-xsm 10 migrate-support-check fail never pass test-amd64-i386-libvirt-qemuu-debianhvm-amd64-xsm 10 migrate-support-check fail never pass build-arm64-pvops 5 kernel-build fail never pass test-amd64-amd64-libvirt-vhd 11 migrate-support-checkfail never pass test-amd64-amd64-qemuu-nested-amd 16 debian-hvm-install/l1/l2 fail never pass test-armhf-armhf-xl-multivcpu 12 migrate-support-checkfail never pass test-armhf-armhf-xl 12 migrate-support-checkfail never pass test-armhf-armhf-xl-multivcpu 13 saverestore-support-checkfail never pass test-armhf-armhf-xl-xsm 12 migrate-support-checkfail never pass test-armhf-armhf-xl 13 saverestore-support-checkfail never pass test-armhf-armhf-xl-xsm 13 saverestore-support-checkfail never pass test-armhf-armhf-xl-credit2 12 migrate-support-checkfail never pass test-armhf-armhf-xl-credit2 13 saverestore-support-checkfail never pass test-armhf-armhf-xl-cubietruck 12 migrate-support-checkfail never pass test-armhf-armhf-xl-cubietruck 13 saverestore-support-checkfail never pass test-amd64-amd64-libvirt 12 migrate-support-checkfail never pass test-armhf-armhf-libvirt-raw 11 migrate-support-checkfail never pass test-armhf-armhf-xl-rtds 12 migrate-support-checkfail never pass test-armhf-armhf-xl-rtds 13 saverestore-support-checkfail never pass test-armhf-armhf-xl-vhd 11 migrate-support-checkfail never pass test-armhf-armhf-xl-vhd 12 saverestore-support-checkfail never pass test-armhf-armhf-xl-arndale 12 migrate-support-checkfail never pass test-armhf-armhf-xl-arndale 13 saverestore-support-checkfail never pass test-armhf-armhf-libvirt-xsm 12 migrate-support-checkfail never pass test-armhf-armhf-libvirt 12 migrate-support-checkfail never pass version targeted for testing: qemuu95b31d709ba343ad237c3630047ee7438bac4065 baseline version: qemuua0ee3797bf4917b1b7a4554a4dffbb45f387f087 Last test of basis 107025 2017-03-31 10:09:36 Z1 days Testing same since 107055 2017-04-01 04:15:35 Z0 days1 attempts People who touched revisions under test: Alex Williamson Alexander Graf Dr. David Alan Gilbert Eric Auger Iwona Kotlarska Michael Roth Peter Maydell Sameeh Jubran Xiong Zhang jobs: build-amd64-xsm pass build-arm64-xsm fail build-armhf-xsm pass build-i386-xsm pass build-amd64 pass build-arm64 fail build-armhf pass build-i386 pass build-amd64-libvir
Re: [Xen-devel] [RFC XEN PATCH v2 00/15] Add vNVDIMM support to HVM domains
On Sat, Apr 1, 2017 at 4:54 AM, Konrad Rzeszutek Wilk wrote: > ..snip.. >> >> Is there a resource I can read more about why the hypervisor needs to >> >> have this M2P mapping for nvdimm support? >> > >> > M2P is basically an array of frame numbers. It's indexed by the host >> > page frame number, or the machine frame number (MFN) in Xen's >> > definition. The n'th entry records the guest page frame number that is >> > mapped to MFN n. M2P is one of the core data structures used in Xen >> > memory management, and is used to convert MFN to guest PFN. A >> > read-only version of M2P is also exposed as part of ABI to guest. In >> > the previous design discussion, we decided to put the management of >> > NVDIMM in the existing Xen memory management as much as possible, so >> > we need to build M2P for NVDIMM as well. >> > >> >> Thanks, but what I don't understand is why this M2P lookup is needed? > > Xen uses it to construct the EPT page tables for the guests. > >> Does Xen establish this metadata for PCI mmio ranges as well? What Xen > > It doesn't have that (M2P) for PCI MMIO ranges. For those it has an > ranges construct (since those are usually contingous and given > in ranges to a guest). So, I'm confused again. This patchset / enabling requires both M2P and contiguous PMEM ranges. If the PMEM is contiguous it seems you don't need M2P and can just reuse the MMIO enabling, or am I missing something? ___ Xen-devel mailing list Xen-devel@lists.xen.org https://lists.xen.org/xen-devel
[Xen-devel] [ovmf test] 107070: all pass - PUSHED
flight 107070 ovmf real [real]
http://logs.test-lab.xenproject.org/osstest/logs/107070/
Perfect :-)
All tests in this flight passed as required
version targeted for testing:
ovmf 12b04866af2c348bf7e28e17b4ddc1eaf410211c
baseline version:
ovmf 4ef6c3850e66617df1ed35a4a390567d2bbf6b76
Last test of basis 107039 2017-03-31 17:15:10 Z0 days
Testing same since 107070 2017-04-01 07:28:49 Z0 days1 attempts
People who touched revisions under test:
Jeff Fan
Jiaxin Wu
Ruiyu Ni
Wu Jiaxin
Yonghong Zhu
Zhang Lubo
Zhang, Lubo
jobs:
build-amd64-xsm pass
build-i386-xsm pass
build-amd64 pass
build-i386 pass
build-amd64-libvirt pass
build-i386-libvirt pass
build-amd64-pvopspass
build-i386-pvops pass
test-amd64-amd64-xl-qemuu-ovmf-amd64 pass
test-amd64-i386-xl-qemuu-ovmf-amd64 pass
sg-report-flight on osstest.test-lab.xenproject.org
logs: /home/logs/logs
images: /home/logs/images
Logs, config files, etc. are available at
http://logs.test-lab.xenproject.org/osstest/logs
Explanation of these reports, and of osstest in general, is at
http://xenbits.xen.org/gitweb/?p=osstest.git;a=blob;f=README.email;hb=master
http://xenbits.xen.org/gitweb/?p=osstest.git;a=blob;f=README;hb=master
Test harness code can be found at
http://xenbits.xen.org/gitweb?p=osstest.git;a=summary
Pushing revision :
+ branch=ovmf
+ revision=12b04866af2c348bf7e28e17b4ddc1eaf410211c
+ . ./cri-lock-repos
++ . ./cri-common
+++ . ./cri-getconfig
+++ umask 002
+++ getrepos
getconfig Repos
perl -e '
use Osstest;
readglobalconfig();
print $c{"Repos"} or die $!;
'
+++ local repos=/home/osstest/repos
+++ '[' -z /home/osstest/repos ']'
+++ '[' '!' -d /home/osstest/repos ']'
+++ echo /home/osstest/repos
++ repos=/home/osstest/repos
++ repos_lock=/home/osstest/repos/lock
++ '[' x '!=' x/home/osstest/repos/lock ']'
++ OSSTEST_REPOS_LOCK_LOCKED=/home/osstest/repos/lock
++ exec with-lock-ex -w /home/osstest/repos/lock ./ap-push ovmf
12b04866af2c348bf7e28e17b4ddc1eaf410211c
+ branch=ovmf
+ revision=12b04866af2c348bf7e28e17b4ddc1eaf410211c
+ . ./cri-lock-repos
++ . ./cri-common
+++ . ./cri-getconfig
+++ umask 002
+++ getrepos
getconfig Repos
perl -e '
use Osstest;
readglobalconfig();
print $c{"Repos"} or die $!;
'
+++ local repos=/home/osstest/repos
+++ '[' -z /home/osstest/repos ']'
+++ '[' '!' -d /home/osstest/repos ']'
+++ echo /home/osstest/repos
++ repos=/home/osstest/repos
++ repos_lock=/home/osstest/repos/lock
++ '[' x/home/osstest/repos/lock '!=' x/home/osstest/repos/lock ']'
+ . ./cri-common
++ . ./cri-getconfig
++ umask 002
+ select_xenbranch
+ case "$branch" in
+ tree=ovmf
+ xenbranch=xen-unstable
+ '[' xovmf = xlinux ']'
+ linuxbranch=
+ '[' x = x ']'
+ qemuubranch=qemu-upstream-unstable
+ select_prevxenbranch
++ ./cri-getprevxenbranch xen-unstable
+ prevxenbranch=xen-4.8-testing
+ '[' x12b04866af2c348bf7e28e17b4ddc1eaf410211c = x ']'
+ : tested/2.6.39.x
+ . ./ap-common
++ : osst...@xenbits.xen.org
+++ getconfig OsstestUpstream
+++ perl -e '
use Osstest;
readglobalconfig();
print $c{"OsstestUpstream"} or die $!;
'
++ :
++ : git://xenbits.xen.org/xen.git
++ : osst...@xenbits.xen.org:/home/xen/git/xen.git
++ : git://xenbits.xen.org/qemu-xen-traditional.git
++ : git://git.kernel.org
++ : git://git.kernel.org/pub/scm/linux/kernel/git
++ : git
++ : git://xenbits.xen.org/xtf.git
++ : osst...@xenbits.xen.org:/home/xen/git/xtf.git
++ : git://xenbits.xen.org/xtf.git
++ : git://xenbits.xen.org/libvirt.git
++ : osst...@xenbits.xen.org:/home/xen/git/libvirt.git
++ : git://xenbits.xen.org/libvirt.git
++ : git://xenbits.xen.org/osstest/rumprun.git
++ : git
++ : git://xenbits.xen.org/osstest/rumprun.git
++ : osst...@xenbits.xen.org:/home/xen/git/osstest/rumprun.git
++ : git://git.seabios.org/seabios.git
++ : osst...@xenbits.xen.org:/home/xen/git/osstest/seabios.git
++ : git://xenbits.xen.org/osstest/seabios.git
++ : https://github.com/tianocore/edk2.git
++ : osst...@xenbits.xen.org:/home/xen/git/osstest/ovmf.git
++ : git://xenbits.xen.org/osstest/ovmf.git
++ : git://xenbits.xen.org/osstest/linux-firmware.git
++ : osst...@xenbits.xen.org:/home/osstest/ext/linux-firmware.git
++ : git://git.kernel.org/pub/scm/linux/kernel/git/fir
[Xen-devel] [PATCH v10 21/25] x86: L2 CAT: implement set value flow.
This patch implements L2 CAT set value related callback functions
and domctl interface.
Signed-off-by: Yi Sun
---
v10:
- check input data and remove cast in domctl.
(suggested by Jan Beulich)
- remove some hooks assignment due to previous patches changes.
(suggested by Jan Beulich)
- remove cast in 'l2_cat_write_msr'.
(suggested by Jan Beulich)
- remove 'return in 'l2_cat_write_msr'.
(suggested by Jan Beulich)
v9:
- reuse some CAT common functions for L2 CAT to reduce redundant codes.
(suggested by Roger Pau)
- remove parameter 'found' from 'cat_compare_val' and modify the return
values to let caller know if the id is found or not. These things are
done in patch "x86: refactor psr: set value: implement cos finding flow."
(suggested by Roger Pau and Dario Faggioli)
- remove 'get_cos_num' related codes.
(suggested by Jan Beulich)
- modify 'l2_cat_write_msr' according to previous patch change.
- changes about 'uint64_t' to 'uint32_t'.
(suggested by Jan Beulich)
v8:
- modify 'l2_cat_write_msr' to 'void'.
v5:
- remove type check in callback function.
(suggested by Jan Beulich)
- modify return value of callback functions because we do not need them
to return number of entries the feature uses. In caller, we call
'get_cos_num' to get the number of entries the feature uses.
(suggested by Jan Beulich)
- remove 'l2_cat_get_cos_max_from_type'.
(suggested by Jan Beulich)
- rename 'l2_cat_exceeds_cos_max' to 'l2_cat_fits_cos_max'.
(suggested by Jan Beulich)
v4:
- create this patch because of codes architecture change.
(suggested by Jan Beulich)
---
xen/arch/x86/domctl.c | 10 ++
xen/arch/x86/psr.c | 11 +++
xen/include/public/domctl.h | 1 +
3 files changed, 22 insertions(+)
diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c
index 59d472c..7eb5983 100644
--- a/xen/arch/x86/domctl.c
+++ b/xen/arch/x86/domctl.c
@@ -1466,6 +1466,16 @@ long arch_do_domctl(
PSR_CBM_TYPE_L3_DATA);
break;
+case XEN_DOMCTL_PSR_CAT_OP_SET_L2_CBM:
+if ( domctl->u.psr_cat_op.data !=
+ (uint32_t)domctl->u.psr_cat_op.data )
+return -EINVAL;
+
+ret = psr_set_val(d, domctl->u.psr_cat_op.target,
+ domctl->u.psr_cat_op.data,
+ PSR_CBM_TYPE_L2);
+break;
+
case XEN_DOMCTL_PSR_CAT_OP_GET_L3_CBM:
{
uint32_t val;
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index 426d725..a85ea99 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -467,10 +467,21 @@ static struct feat_props l3_cdp_props = {
};
/* L2 CAT ops */
+static void l2_cat_write_msr(unsigned int cos, uint32_t val,
+ enum cbm_type type, struct feat_node *feat)
+{
+if ( feat->cos_reg_val[cos] != val )
+{
+feat->cos_reg_val[cos] = val;
+wrmsrl(MSR_IA32_PSR_L2_MASK(cos), val);
+}
+}
+
static struct feat_props l2_cat_props = {
.cos_num = 1,
.get_feat_info = cat_get_feat_info,
.get_val = cat_get_val,
+.write_msr = l2_cat_write_msr,
};
static void __init parse_psr_bool(char *s, char *value, char *feature,
diff --git a/xen/include/public/domctl.h b/xen/include/public/domctl.h
index 8c183ba..523a2cd 100644
--- a/xen/include/public/domctl.h
+++ b/xen/include/public/domctl.h
@@ -1138,6 +1138,7 @@ struct xen_domctl_psr_cat_op {
#define XEN_DOMCTL_PSR_CAT_OP_SET_L3_DATA3
#define XEN_DOMCTL_PSR_CAT_OP_GET_L3_CODE4
#define XEN_DOMCTL_PSR_CAT_OP_GET_L3_DATA5
+#define XEN_DOMCTL_PSR_CAT_OP_SET_L2_CBM 6
#define XEN_DOMCTL_PSR_CAT_OP_GET_L2_CBM 7
uint32_t cmd; /* IN: XEN_DOMCTL_PSR_CAT_OP_* */
uint32_t target;/* IN */
--
1.9.1
___
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
[Xen-devel] [PATCH v10 20/25] x86: L2 CAT: implement get value flow.
This patch implements L2 CAT get value flow and interface in domctl.
Signed-off-by: Yi Sun
---
v10:
- remove cast in domctl.
(suggested by Jan Beulich)
v9:
- reuse 'cat_get_val' for L2 CAT to reduce redundant codes
(suggested by Roger Pau)
- changes about 'uint64_t' to 'uint32_t'.
(suggested by Jan Beulich)
v5:
- remove type check in callback function.
(suggested by Jan Beulich)
v4:
- create this patch because of codes architecture change.
(suggested by Jan Beulich)
---
xen/arch/x86/domctl.c | 11 +++
xen/arch/x86/psr.c | 1 +
xen/include/public/domctl.h | 1 +
3 files changed, 13 insertions(+)
diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c
index 6ed71e2..59d472c 100644
--- a/xen/arch/x86/domctl.c
+++ b/xen/arch/x86/domctl.c
@@ -1499,6 +1499,17 @@ long arch_do_domctl(
break;
}
+case XEN_DOMCTL_PSR_CAT_OP_GET_L2_CBM:
+{
+uint32_t val;
+
+ret = psr_get_val(d, domctl->u.psr_cat_op.target,
+ &val, PSR_CBM_TYPE_L2);
+domctl->u.psr_cat_op.data = val;
+copyback = 1;
+break;
+}
+
default:
ret = -EOPNOTSUPP;
break;
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index 8114bed..426d725 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -470,6 +470,7 @@ static struct feat_props l3_cdp_props = {
static struct feat_props l2_cat_props = {
.cos_num = 1,
.get_feat_info = cat_get_feat_info,
+.get_val = cat_get_val,
};
static void __init parse_psr_bool(char *s, char *value, char *feature,
diff --git a/xen/include/public/domctl.h b/xen/include/public/domctl.h
index 85cbb7c..8c183ba 100644
--- a/xen/include/public/domctl.h
+++ b/xen/include/public/domctl.h
@@ -1138,6 +1138,7 @@ struct xen_domctl_psr_cat_op {
#define XEN_DOMCTL_PSR_CAT_OP_SET_L3_DATA3
#define XEN_DOMCTL_PSR_CAT_OP_GET_L3_CODE4
#define XEN_DOMCTL_PSR_CAT_OP_GET_L3_DATA5
+#define XEN_DOMCTL_PSR_CAT_OP_GET_L2_CBM 7
uint32_t cmd; /* IN: XEN_DOMCTL_PSR_CAT_OP_* */
uint32_t target;/* IN */
uint64_t data; /* IN/OUT */
--
1.9.1
___
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Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
[Xen-devel] [PATCH v10 24/25] tools: L2 CAT: support set cbm for L2 CAT.
This patch implements the xl/xc changes to support set CBM
for L2 CAT.
The new level option is introduced to original CAT setting
command in order to set CBM for specified level CAT.
- 'xl psr-cat-set' is updated to set cache capacity bitmasks(CBM)
for a domain according to input cache level.
root@:~$ xl psr-cat-set -l2 1 0x7f
root@:~$ xl psr-cat-show -l2 1
Socket ID : 0
Default CBM : 0xff
ID NAME CBM
1 ubuntu140x7f
Signed-off-by: He Chen
Signed-off-by: Yi Sun
---
v10:
- fix comments.
(suggested by Wei Liu)
v9:
- handle the case to set both CODE and DATA for CDP at same time.
For such case, user does not input '-c' or '-d' to set CDP cbm.
- move xl_cmdimpl.c changes into xl/xl_psr.c.
- move xl_cmdtable.c changes into xl/xl_cmdtable.c.
v6:
- rename 'psr-cat-cbm-set' to 'psr-cat-set'.
(suggested by Kevin Tian)
- return 'EXIT_FAILURE' for error case.
(suggested by Dario Faggioli)
- print error info when input level is wrong.
v4:
- create this patch because of codes architecture change.
---
tools/libxc/xc_psr.c| 3 +++
tools/libxl/libxl_psr.c | 40
tools/xl/xl_cmdtable.c | 3 ++-
tools/xl/xl_psr.c | 33 +++--
4 files changed, 64 insertions(+), 15 deletions(-)
diff --git a/tools/libxc/xc_psr.c b/tools/libxc/xc_psr.c
index 04f5927..039b920 100644
--- a/tools/libxc/xc_psr.c
+++ b/tools/libxc/xc_psr.c
@@ -266,6 +266,9 @@ int xc_psr_cat_set_domain_data(xc_interface *xch, uint32_t
domid,
case XC_PSR_CAT_L3_CBM_DATA:
cmd = XEN_DOMCTL_PSR_CAT_OP_SET_L3_DATA;
break;
+case XC_PSR_CAT_L2_CBM:
+cmd = XEN_DOMCTL_PSR_CAT_OP_SET_L2_CBM;
+break;
default:
errno = EINVAL;
return -1;
diff --git a/tools/libxl/libxl_psr.c b/tools/libxl/libxl_psr.c
index f55ba1e..3598d84 100644
--- a/tools/libxl/libxl_psr.c
+++ b/tools/libxl/libxl_psr.c
@@ -317,6 +317,7 @@ int libxl_psr_cat_set_cbm(libxl_ctx *ctx, uint32_t domid,
GC_INIT(ctx);
int rc;
int socketid, nr_sockets;
+libxl_psr_cat_info cat_info;
rc = libxl__count_physical_sockets(gc, &nr_sockets);
if (rc) {
@@ -331,10 +332,41 @@ int libxl_psr_cat_set_cbm(libxl_ctx *ctx, uint32_t domid,
break;
xc_type = libxl__psr_cbm_type_to_libxc_psr_cat_type(type);
-if (xc_psr_cat_set_domain_data(ctx->xch, domid, xc_type,
- socketid, cbm)) {
-libxl__psr_cat_log_err_msg(gc, errno);
-rc = ERROR_FAIL;
+
+if (xc_type == XC_PSR_CAT_L3_CBM) {
+if (xc_psr_cat_get_info(ctx->xch, socketid, 3, &cat_info.cos_max,
+&cat_info.cbm_len, &cat_info.cdp_enabled))
{
+libxl__psr_cat_log_err_msg(gc, errno);
+rc = ERROR_FAIL;
+goto out;
+}
+}
+
+/*
+ * If cdp_enabled is true and type is XC_PSR_CAT_L3_CBM, we need set
+ * both CODE and DATA.
+ */
+if (xc_type == XC_PSR_CAT_L3_CBM && cat_info.cdp_enabled) {
+xc_type = XC_PSR_CAT_L3_CBM_CODE;
+if (xc_psr_cat_set_domain_data(ctx->xch, domid, xc_type,
+ socketid, cbm)) {
+libxl__psr_cat_log_err_msg(gc, errno);
+rc = ERROR_FAIL;
+}
+
+xc_type = XC_PSR_CAT_L3_CBM_DATA;
+if (rc != ERROR_FAIL &&
+xc_psr_cat_set_domain_data(ctx->xch, domid, xc_type,
+ socketid, cbm)) {
+libxl__psr_cat_log_err_msg(gc, errno);
+rc = ERROR_FAIL;
+}
+} else {
+if (xc_psr_cat_set_domain_data(ctx->xch, domid, xc_type,
+ socketid, cbm)) {
+libxl__psr_cat_log_err_msg(gc, errno);
+rc = ERROR_FAIL;
+}
}
}
diff --git a/tools/xl/xl_cmdtable.c b/tools/xl/xl_cmdtable.c
index ab7ad60..d332e1a 100644
--- a/tools/xl/xl_cmdtable.c
+++ b/tools/xl/xl_cmdtable.c
@@ -545,11 +545,12 @@ struct cmd_spec cmd_table[] = {
},
#endif
#ifdef LIBXL_HAVE_PSR_CAT
-{ "psr-cat-cbm-set",
+{ "psr-cat-set",
&main_psr_cat_cbm_set, 0, 1,
"Set cache capacity bitmasks(CBM) for a domain",
"[options] ",
"-sSpecify the socket to process, otherwise all sockets
are processed\n"
+ "-l Specify the cache level to process, otherwise L3
cache is processed\n"
"-cSet code CBM if CDP is supported\n"
"-dSet data CBM if CDP is supported\n"
},
diff --git a/tools/xl/xl_psr.c b/tools/xl/xl_psr.c
index 575f4a0..7309d4f 100644
--- a/tools/xl/xl_psr.c
+++ b/tools/xl/xl_psr.c
@@ -490,19 +490,21 @@ int main_psr_cat_cbm_set(int
[Xen-devel] [PATCH v10 25/25] docs: add L2 CAT description in docs.
This patch adds L2 CAT description in related documents. Signed-off-by: He Chen Signed-off-by: Yi Sun Acked-by: Wei Liu --- docs/man/xl.pod.1.in | 25 ++--- docs/misc/xl-psr.markdown | 18 -- 2 files changed, 34 insertions(+), 9 deletions(-) diff --git a/docs/man/xl.pod.1.in b/docs/man/xl.pod.1.in index 7caed08..5e7676e 100644 --- a/docs/man/xl.pod.1.in +++ b/docs/man/xl.pod.1.in @@ -1711,6 +1711,9 @@ occupancy monitoring share the same set of underlying monitoring service. Once a domain is attached to the monitoring service, monitoring data can be shown for any of these monitoring types. +There is no cache monitoring and memory bandwidth monitoring on L2 cache so +far. + =over 4 =item B [I] @@ -1735,7 +1738,7 @@ monitor types are: Intel Broadwell and later server platforms offer capabilities to configure and make use of the Cache Allocation Technology (CAT) mechanisms, which enable more -cache resources (i.e. L3 cache) to be made available for high priority +cache resources (i.e. L3/L2 cache) to be made available for high priority applications. In the Xen implementation, CAT is used to control cache allocation on VM basis. To enforce cache on a specific domain, just set capacity bitmasks (CBM) for the domain. @@ -1745,7 +1748,7 @@ Intel Broadwell and later server platforms also offer Code/Data Prioritization applications. CDP is used on a per VM basis in the Xen implementation. To specify code or data CBM for the domain, CDP feature must be enabled and CBM type options need to be specified when setting CBM, and the type options (code -and data) are mutually exclusive. +and data) are mutually exclusive. There is no CDP support on L2 so far. =over 4 @@ -1762,6 +1765,11 @@ B Specify the socket to process, otherwise all sockets are processed. +=item B<-l LEVEL>, B<--level=LEVEL> + +Specify the cache level to process, otherwise the last level cache (L3) is +processed. + =item B<-c>, B<--code> Set code CBM when CDP is enabled. @@ -1772,10 +1780,21 @@ Set data CBM when CDP is enabled. =back -=item B [I] +=item B [I] [I] Show CAT settings for a certain domain or all domains. +B + +=over 4 + +=item B<-l LEVEL>, B<--level=LEVEL> + +Specify the cache level to process, otherwise the last level cache (L3) is +processed. + +=back + =back =head1 IGNORED FOR COMPATIBILITY WITH XM diff --git a/docs/misc/xl-psr.markdown b/docs/misc/xl-psr.markdown index c3c1e8e..04dd957 100644 --- a/docs/misc/xl-psr.markdown +++ b/docs/misc/xl-psr.markdown @@ -70,7 +70,7 @@ total-mem-bandwidth instead of cache-occupancy). E.g. after a `xl psr-cmt-attach Cache Allocation Technology (CAT) is a new feature available on Intel Broadwell and later server platforms that allows an OS or Hypervisor/VMM to -partition cache allocation (i.e. L3 cache) based on application priority or +partition cache allocation (i.e. L3/L2 cache) based on application priority or Class of Service (COS). Each COS is configured using capacity bitmasks (CBM) which represent cache capacity and indicate the degree of overlap and isolation between classes. System cache resource is divided into numbers of @@ -107,7 +107,7 @@ System CAT information such as maximum COS and CBM length can be obtained by: The simplest way to change a domain's CBM from its default is running: -`xl psr-cat-cbm-set [OPTIONS] ` +`xl psr-cat-set [OPTIONS] ` where cbm is a number to represent the corresponding cache subset can be used. A cbm is valid only when: @@ -119,13 +119,19 @@ A cbm is valid only when: In a multi-socket system, the same cbm will be set on each socket by default. Per socket cbm can be specified with the `--socket SOCKET` option. +In different systems, the different cache level is supported, e.g. L3 cache or +L2 cache. Per cache level cbm can be specified with the `--level LEVEL` option. + Setting the CBM may not be successful if insufficient COS is available. In such case unused COS(es) may be freed by setting CBM of all related domains to its default value(all-ones). Per domain CBM settings can be shown by: -`xl psr-cat-show` +`xl psr-cat-show [OPTIONS] ` + +In different systems, the different cache level is supported, e.g. L3 cache or +L2 cache. Per cache level cbm can be specified with the `--level LEVEL` option. ## Code and Data Prioritization (CDP) @@ -172,13 +178,13 @@ options is invalid. Example: Setting code CBM for a domain: -`xl psr-cat-cbm-set -c ` +`xl psr-cat-set -c ` Setting data CBM for a domain: -`xl psr-cat-cbm-set -d ` +`xl psr-cat-set -d ` Setting the same code and data CBM for a domain: -`xl psr-cat-cbm-set ` +`xl psr-cat-set ` ## Reference -- 1.9.1 ___ Xen-devel mailing list Xen-devel@lists.xen.org https://lists.xen.org/xen-devel
[Xen-devel] [PATCH v10 22/25] tools: L2 CAT: support get HW info for L2 CAT.
This patch implements xl/xc changes to support get HW info
for L2 CAT.
'xl psr-hwinfo' is updated to show both L3 CAT and L2 CAT
info.
Example(on machine which only supports L2 CAT):
Cache Monitoring Technology (CMT):
Enabled : 0
Cache Allocation Technology (CAT): L2
Socket ID : 0
Maximum COS : 3
CBM length : 8
Default CBM : 0xff
Signed-off-by: He Chen
Signed-off-by: Yi Sun
---
v10:
- change macros names according to previous changes.
(suggested by Jan Beulich)
v9:
- add some cases to handle return error no.
- move xl_cmdimpl.c codes into xl/xl_psr.c.
- change 'l3_info' to 'cat_info' to cover both L3 and L2 CAT.
v6:
- adjust '{' position for 'switch'.
(suggested by Wei Liu)
- modify commit message to remove error log.
(suggested by Dario Faggioli)
v5:
- modify commit message to remove error log.
(suggested by Wei Liu and Jan Beulich)
- replace unnecessary 'return' to 'break'.
(suggested by Wei Liu)
- restore 'libxl_psr_cat_get_l3_info' to keep interface backward compatible
but change codes in it to call new function to get hw info.
(suggested by Wei Liu)
- add 'L2_CBM' into 'psr_cbm_type' because it is interface change which
should be in same patch with new 'LIBXL_HAVE_' macro.
(suggested by Wei Liu)
- addjust logs sentence to make unnecessary error logs not show.
(suggested by Wei Liu and Jan Beulich)
v4:
- create this patch to help reviewers better understand the codes.
---
tools/libxc/include/xenctrl.h | 6 ++---
tools/libxc/xc_psr.c | 39 +++-
tools/libxl/libxl.h | 9
tools/libxl/libxl_psr.c | 28 ++-
tools/libxl/libxl_types.idl | 1 +
tools/xl/xl_psr.c | 52 +--
xen/arch/x86/sysctl.c | 12 +-
xen/include/public/sysctl.h | 2 +-
8 files changed, 111 insertions(+), 38 deletions(-)
diff --git a/tools/libxc/include/xenctrl.h b/tools/libxc/include/xenctrl.h
index a48981a..99c6fa5 100644
--- a/tools/libxc/include/xenctrl.h
+++ b/tools/libxc/include/xenctrl.h
@@ -2442,9 +2442,9 @@ int xc_psr_cat_set_domain_data(xc_interface *xch,
uint32_t domid,
int xc_psr_cat_get_domain_data(xc_interface *xch, uint32_t domid,
xc_psr_cat_type type, uint32_t target,
uint64_t *data);
-int xc_psr_cat_get_l3_info(xc_interface *xch, uint32_t socket,
- uint32_t *cos_max, uint32_t *cbm_len,
- bool *cdp_enabled);
+int xc_psr_cat_get_info(xc_interface *xch, uint32_t socket, unsigned int lvl,
+uint32_t *cos_max, uint32_t *cbm_len,
+bool *cdp_enabled);
int xc_get_cpu_levelling_caps(xc_interface *xch, uint32_t *caps);
int xc_get_cpu_featureset(xc_interface *xch, uint32_t index,
diff --git a/tools/libxc/xc_psr.c b/tools/libxc/xc_psr.c
index 43b3286..84a08c4 100644
--- a/tools/libxc/xc_psr.c
+++ b/tools/libxc/xc_psr.c
@@ -317,24 +317,41 @@ int xc_psr_cat_get_domain_data(xc_interface *xch,
uint32_t domid,
return rc;
}
-int xc_psr_cat_get_l3_info(xc_interface *xch, uint32_t socket,
- uint32_t *cos_max, uint32_t *cbm_len,
- bool *cdp_enabled)
+int xc_psr_cat_get_info(xc_interface *xch, uint32_t socket, unsigned int lvl,
+uint32_t *cos_max, uint32_t *cbm_len, bool
*cdp_enabled)
{
-int rc;
+int rc = -1;
DECLARE_SYSCTL;
sysctl.cmd = XEN_SYSCTL_psr_cat_op;
-sysctl.u.psr_cat_op.cmd = XEN_SYSCTL_PSR_CAT_get_l3_info;
sysctl.u.psr_cat_op.target = socket;
-rc = xc_sysctl(xch, &sysctl);
-if ( !rc )
+switch ( lvl )
{
-*cos_max = sysctl.u.psr_cat_op.u.l3_info.cos_max;
-*cbm_len = sysctl.u.psr_cat_op.u.l3_info.cbm_len;
-*cdp_enabled = sysctl.u.psr_cat_op.u.l3_info.flags &
- XEN_SYSCTL_PSR_CAT_L3_CDP;
+case 2:
+sysctl.u.psr_cat_op.cmd = XEN_SYSCTL_PSR_CAT_get_l2_info;
+rc = xc_sysctl(xch, &sysctl);
+if ( !rc )
+{
+*cos_max = sysctl.u.psr_cat_op.u.cat_info.cos_max;
+*cbm_len = sysctl.u.psr_cat_op.u.cat_info.cbm_len;
+*cdp_enabled = false;
+}
+break;
+case 3:
+sysctl.u.psr_cat_op.cmd = XEN_SYSCTL_PSR_CAT_get_l3_info;
+rc = xc_sysctl(xch, &sysctl);
+if ( !rc )
+{
+*cos_max = sysctl.u.psr_cat_op.u.cat_info.cos_max;
+*cbm_len = sysctl.u.psr_cat_op.u.cat_info.cbm_len;
+*cdp_enabled = sysctl.u.psr_cat_op.u.cat_info.flags &
+ XEN_SYSCTL_PSR_CAT_L3_CDP;
+}
+break;
+default:
+errno = EOPNOTSUPP;
+break;
}
return rc;
diff --git a/tools/libxl/libxl.h b/tools/libxl/libxl.h
index 92f1751..6c6fb01 1006
[Xen-devel] [PATCH v10 23/25] tools: L2 CAT: support show cbm for L2 CAT.
This patch implements changes in xl/xc changes to support
showing CBM of L2 CAT.
The new level option is introduced to original CAT showing
command in order to show CBM for specified level CAT.
- 'xl psr-cat-show' is updated to show CBM of a domain
according to input cache level.
Examples:
root@:~$ xl psr-cat-show -l2 1
Socket ID : 0
Default CBM : 0xff
ID NAME CBM
1 ubuntu140x7f
Signed-off-by: He Chen
Signed-off-by: Yi Sun
---
v9:
- move xl_cmdimpl.c changes into xl/xl_psr.c.
- move xl_cmdtable.c changes into xl/xl_cmdtable.c.
v6:
- check if input level is correct.
- adjust '{' postion for 'if'.
(suggested by Wei Liu)
v5:
- remove 'L2_CBM' in idl because it has been moved to patch 21:
"tools: L2 CAT: support get HW info for L2 CAT".
(suggested by Wei Liu)
v4:
- create this patch because of codes architecture change.
---
tools/libxc/include/xenctrl.h | 1 +
tools/libxc/xc_psr.c | 3 ++
tools/xl/xl_cmdtable.c| 3 +-
tools/xl/xl_psr.c | 85 +--
4 files changed, 63 insertions(+), 29 deletions(-)
diff --git a/tools/libxc/include/xenctrl.h b/tools/libxc/include/xenctrl.h
index 99c6fa5..0fd9326 100644
--- a/tools/libxc/include/xenctrl.h
+++ b/tools/libxc/include/xenctrl.h
@@ -2418,6 +2418,7 @@ enum xc_psr_cat_type {
XC_PSR_CAT_L3_CBM = 1,
XC_PSR_CAT_L3_CBM_CODE = 2,
XC_PSR_CAT_L3_CBM_DATA = 3,
+XC_PSR_CAT_L2_CBM = 4,
};
typedef enum xc_psr_cat_type xc_psr_cat_type;
diff --git a/tools/libxc/xc_psr.c b/tools/libxc/xc_psr.c
index 84a08c4..04f5927 100644
--- a/tools/libxc/xc_psr.c
+++ b/tools/libxc/xc_psr.c
@@ -299,6 +299,9 @@ int xc_psr_cat_get_domain_data(xc_interface *xch, uint32_t
domid,
case XC_PSR_CAT_L3_CBM_DATA:
cmd = XEN_DOMCTL_PSR_CAT_OP_GET_L3_DATA;
break;
+case XC_PSR_CAT_L2_CBM:
+cmd = XEN_DOMCTL_PSR_CAT_OP_GET_L2_CBM;
+break;
default:
errno = EINVAL;
return -1;
diff --git a/tools/xl/xl_cmdtable.c b/tools/xl/xl_cmdtable.c
index 1219b33..ab7ad60 100644
--- a/tools/xl/xl_cmdtable.c
+++ b/tools/xl/xl_cmdtable.c
@@ -556,7 +556,8 @@ struct cmd_spec cmd_table[] = {
{ "psr-cat-show",
&main_psr_cat_show, 0, 1,
"Show Cache Allocation Technology information",
- "",
+ "[options] ",
+ "-l Specify the cache level to process, otherwise L3
cache is processed\n"
},
#endif
diff --git a/tools/xl/xl_psr.c b/tools/xl/xl_psr.c
index 271b88f..575f4a0 100644
--- a/tools/xl/xl_psr.c
+++ b/tools/xl/xl_psr.c
@@ -342,7 +342,7 @@ static void psr_cat_print_one_domain_cbm_type(uint32_t
domid, uint32_t socketid,
}
static void psr_cat_print_one_domain_cbm(uint32_t domid, uint32_t socketid,
- bool cdp_enabled)
+ bool cdp_enabled, unsigned int lvl)
{
char *domain_name;
@@ -350,27 +350,38 @@ static void psr_cat_print_one_domain_cbm(uint32_t domid,
uint32_t socketid,
printf("%5d%25s", domid, domain_name);
free(domain_name);
-if (!cdp_enabled) {
-psr_cat_print_one_domain_cbm_type(domid, socketid,
- LIBXL_PSR_CBM_TYPE_L3_CBM);
-} else {
-psr_cat_print_one_domain_cbm_type(domid, socketid,
- LIBXL_PSR_CBM_TYPE_L3_CBM_CODE);
+switch (lvl) {
+case 3:
+if (!cdp_enabled) {
+psr_cat_print_one_domain_cbm_type(domid, socketid,
+ LIBXL_PSR_CBM_TYPE_L3_CBM);
+} else {
+psr_cat_print_one_domain_cbm_type(domid, socketid,
+ LIBXL_PSR_CBM_TYPE_L3_CBM_CODE);
+psr_cat_print_one_domain_cbm_type(domid, socketid,
+ LIBXL_PSR_CBM_TYPE_L3_CBM_DATA);
+}
+break;
+case 2:
psr_cat_print_one_domain_cbm_type(domid, socketid,
- LIBXL_PSR_CBM_TYPE_L3_CBM_DATA);
+ LIBXL_PSR_CBM_TYPE_L2_CBM);
+break;
+default:
+printf("Input lvl %d is wrong!", lvl);
+break;
}
printf("\n");
}
static int psr_cat_print_domain_cbm(uint32_t domid, uint32_t socketid,
-bool cdp_enabled)
+bool cdp_enabled, unsigned int lvl)
{
int i, nr_domains;
libxl_dominfo *list;
if (domid != INVALID_DOMID) {
-psr_cat_print_one_domain_cbm(domid, socketid, cdp_enabled);
+psr_cat_print_one_domain_cbm(domid, socketid, cdp_enabled, lvl);
return 0;
}
@@ -380,49 +391,59 @@ static int psr_cat_print_domain_cbm(uint32_t domid,
uint32_t socketid,
}
for (i = 0; i < nr_domains; i++)
-psr_
[Xen-devel] [PATCH v10 18/25] x86: L2 CAT: implement CPU init and free flow.
This patch implements the CPU init and free flow for L2 CAT.
Signed-off-by: Yi Sun
---
v10:
- implement L2 CAT case in 'cat_init_feature'.
(suggested by Jan Beulich)
- changes about 'props'.
(suggested by Jan Beulich)
- introduce 'PSR_CBM_TYPE_L2'.
v9:
- modify error handling process in 'psr_cpu_prepare' to reduce redundant
codes.
- reuse 'cat_init_feature' and 'cat_get_cos_max' for L2 CAT to reduce
redundant codes.
(suggested by Roger Pau)
- remove unnecessary comment.
(suggested by Jan Beulich)
- move L2 CAT related codes from 'cpu_init_work' into 'psr_cpu_init'.
(suggested by Jan Beulich)
- do not free resource when allocation fails in 'psr_cpu_prepare'.
(suggested by Jan Beulich)
v7:
- initialize 'l2_cat'.
(suggested by Konrad Rzeszutek Wilk)
v6:
- use 'struct cpuid_leaf'.
(suggested by Konrad Rzeszutek Wilk and Jan Beulich)
v5:
- remove 'feat_l2_cat' free in 'free_feature'.
(suggested by Jan Beulich)
- encapsulate cpuid registers into 'struct cpuid_leaf_regs'.
(suggested by Jan Beulich)
- print socket info when 'opt_cpu_info' is true.
(suggested by Jan Beulich)
- rename 'l2_cat_get_max_cos_max' to 'l2_cat_get_cos_max'.
(suggested by Jan Beulich)
- rename 'dat[]' to 'data[]'
(suggested by Jan Beulich)
- move 'cpu_prepare_work' contents into 'psr_cpu_prepare'.
(suggested by Jan Beulich)
v4:
- create this patch because of codes architecture change.
(suggested by Jan Beulich)
---
xen/arch/x86/psr.c | 33 +++--
xen/include/asm-x86/msr-index.h | 1 +
xen/include/asm-x86/psr.h | 2 ++
3 files changed, 34 insertions(+), 2 deletions(-)
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index bfa1777..6a9cd88 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -160,6 +160,7 @@ static DEFINE_PER_CPU(struct psr_assoc, psr_assoc);
*/
static struct feat_node *feat_l3_cat;
static struct feat_node *feat_l3_cdp;
+static struct feat_node *feat_l2_cat;
/* Common functions */
#define cat_default_val(len) (0x >> (32 - (len)))
@@ -304,10 +305,14 @@ static void cat_init_feature(const struct cpuid_leaf
*regs,
switch ( type )
{
case PSR_SOCKET_L3_CAT:
+case PSR_SOCKET_L2_CAT:
/* cos=0 is reserved as default cbm(all bits within cbm_len are 1). */
feat->cos_reg_val[0] = cat_default_val(feat->props->cbm_len);
-feat->props->type[0] = PSR_CBM_TYPE_L3;
+if ( type == PSR_SOCKET_L3_CAT )
+feat->props->type[0] = PSR_CBM_TYPE_L3;
+else
+feat->props->type[0] = PSR_CBM_TYPE_L2;
/*
* To handle cpu offline and then online case, we need restore MSRs to
@@ -315,7 +320,11 @@ static void cat_init_feature(const struct cpuid_leaf *regs,
*/
for ( i = 1; i <= feat->props->cos_max; i++ )
{
-wrmsrl(MSR_IA32_PSR_L3_MASK(i), feat->cos_reg_val[0]);
+if ( type == PSR_SOCKET_L3_CAT )
+wrmsrl(MSR_IA32_PSR_L3_MASK(i), feat->cos_reg_val[0]);
+else
+wrmsrl(MSR_IA32_PSR_L2_MASK(i), feat->cos_reg_val[0]);
+
feat->cos_reg_val[i] = feat->cos_reg_val[0];
}
@@ -454,6 +463,11 @@ static struct feat_props l3_cdp_props = {
.write_msr = l3_cdp_write_msr,
};
+/* L2 CAT ops */
+static struct feat_props l2_cat_props = {
+.cos_num = 1,
+};
+
static void __init parse_psr_bool(char *s, char *value, char *feature,
unsigned int mask)
{
@@ -1393,6 +1407,10 @@ static int psr_cpu_prepare(void)
(feat_l3_cdp = xzalloc(struct feat_node)) == NULL )
return -ENOMEM;
+if ( feat_l2_cat == NULL &&
+ (feat_l2_cat = xzalloc(struct feat_node)) == NULL )
+return -ENOMEM;
+
return 0;
}
@@ -1442,6 +1460,17 @@ static void psr_cpu_init(void)
}
}
+cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 0, ®s);
+if ( regs.b & PSR_RESOURCE_TYPE_L2 )
+{
+cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 2, ®s);
+
+feat = feat_l2_cat;
+feat_l2_cat = NULL;
+feat->props = &l2_cat_props;
+cat_init_feature(®s, feat, info, PSR_SOCKET_L2_CAT);
+}
+
assoc_init:
psr_assoc_init();
}
diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index 771e750..6c49c6d 100644
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -345,6 +345,7 @@
#define MSR_IA32_PSR_L3_MASK(n)(0x0c90 + (n))
#define MSR_IA32_PSR_L3_MASK_CODE(n) (0x0c90 + (n) * 2 + 1)
#define MSR_IA32_PSR_L3_MASK_DATA(n) (0x0c90 + (n) * 2)
+#define MSR_IA32_PSR_L2_MASK(n)(0x0d10 + (n))
/* Intel Model 6 */
#define MSR_P6_PERFCTR(n) (0x00c1 + (n))
diff --git a/xen/include/asm-x86/psr.h b/xen/include/asm-x86/psr.h
index 66d5218..
[Xen-devel] [PATCH v10 19/25] x86: L2 CAT: implement get hw info flow.
This patch implements L2 CAT get HW info flow and interface in sysctl.
Signed-off-by: Yi Sun
---
v10:
- modify macro name according to previous patch change.
(suggested by Jan Beulich)
- modify commit message.
v9:
- reuse 'cat_get_feat_info' for L2 CAT to reduce redundant codes.
(suggested by Roger Pau)
- modify sysctl implementation of L2 CAT to input data[3] to use
'cat_get_feat_info'.
(suggested by Roger Pau)
- modify macros names to newly defined ones.
(suggested by Jan Beulich)
- remove 'l2_info' to reuse 'l3_info'.
(suggested by Jan Beulich)
- modify macro name according to previous patch change.
(suggested by Jan Beulich)
v5:
- rename 'dat[]' to 'data[]'
(suggested by Jan Beulich)
- remove type check in callback function.
(suggested by Jan Beulich)
v4:
- create this patch because of codes architecture change.
(suggested by Jan Beulich)
---
xen/arch/x86/psr.c | 4
xen/arch/x86/sysctl.c | 21 +
xen/include/public/sysctl.h | 1 +
3 files changed, 26 insertions(+)
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index 6a9cd88..8114bed 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -257,6 +257,9 @@ static enum psr_feat_type psr_cbm_type_to_feat_type(enum
cbm_type type)
case PSR_CBM_TYPE_L3_CODE:
feat_type = PSR_SOCKET_L3_CDP;
break;
+case PSR_CBM_TYPE_L2:
+feat_type = PSR_SOCKET_L2_CAT;
+break;
default:
ASSERT_UNREACHABLE();
}
@@ -466,6 +469,7 @@ static struct feat_props l3_cdp_props = {
/* L2 CAT ops */
static struct feat_props l2_cat_props = {
.cos_num = 1,
+.get_feat_info = cat_get_feat_info,
};
static void __init parse_psr_bool(char *s, char *value, char *feature,
diff --git a/xen/arch/x86/sysctl.c b/xen/arch/x86/sysctl.c
index c23270d..ba6b6a6 100644
--- a/xen/arch/x86/sysctl.c
+++ b/xen/arch/x86/sysctl.c
@@ -195,6 +195,27 @@ long arch_do_sysctl(
break;
}
+case XEN_SYSCTL_PSR_CAT_get_l2_info:
+{
+uint32_t data[PSR_INFO_ARRAY_SIZE];
+
+ret = psr_get_info(sysctl->u.psr_cat_op.target,
+ PSR_CBM_TYPE_L2, data, ARRAY_SIZE(data));
+if ( ret )
+break;
+
+sysctl->u.psr_cat_op.u.l3_info.cos_max =
+ data[PSR_INFO_IDX_COS_MAX];
+sysctl->u.psr_cat_op.u.l3_info.cbm_len =
+ data[PSR_INFO_IDX_CAT_CBM_LEN];
+sysctl->u.psr_cat_op.u.l3_info.flags =
+ data[PSR_INFO_IDX_CAT_FLAG];
+
+if ( !ret && __copy_field_to_guest(u_sysctl, sysctl, u.psr_cat_op)
)
+ret = -EFAULT;
+break;
+}
+
default:
ret = -EOPNOTSUPP;
break;
diff --git a/xen/include/public/sysctl.h b/xen/include/public/sysctl.h
index 00f5e77..1fe8fe4 100644
--- a/xen/include/public/sysctl.h
+++ b/xen/include/public/sysctl.h
@@ -744,6 +744,7 @@ typedef struct xen_sysctl_pcitopoinfo
xen_sysctl_pcitopoinfo_t;
DEFINE_XEN_GUEST_HANDLE(xen_sysctl_pcitopoinfo_t);
#define XEN_SYSCTL_PSR_CAT_get_l3_info 0
+#define XEN_SYSCTL_PSR_CAT_get_l2_info 1
struct xen_sysctl_psr_cat_op {
uint32_t cmd; /* IN: XEN_SYSCTL_PSR_CAT_* */
uint32_t target;/* IN */
--
1.9.1
___
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Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
[Xen-devel] [PATCH v10 01/25] docs: create Cache Allocation Technology (CAT) and Code and Data Prioritization (CDP) feature document
This patch creates CAT and CDP feature document in doc/features/. It describes key points to implement L3 CAT/CDP and L2 CAT which is described in details in Intel SDM "INTEL® RESOURCE DIRECTOR TECHNOLOGY (INTEL® RDT) ALLOCATION FEATURES". Signed-off-by: Yi Sun Reviewed-by: Konrad Rzeszutek Wilk Reviewed-by: Wei Liu --- v9: - add 'CMT' to the list of acronyms. (suggested by Wei Liu) - change feature list to feature array. - modify data structure descriptions according to latest codes. - modify revision. v8: - change revision info. (suggested by Konrad Rzeszutek Wilk) - add content int 'Areas for improvement'. (suggested by Konrad Rzeszutek Wilk) v7: - correct typo. (suggested by Konrad Rzeszutek Wilk) - replace application/VM to domain. (suggested by Konrad Rzeszutek Wilk) - amend description of `feat_mask` to make it clearer. (suggested by Konrad Rzeszutek Wilk) - update revision. (suggested by Konrad Rzeszutek Wilk) - other minor fixes. (suggested by Konrad Rzeszutek Wilk) v6: - write a new feature document to cover L3 CAT/CDP and L2 CAT. (suggested by Kevin Tian) - adjust 'Terminology' position in document. (suggested by Dario Faggioli) - fix wordings. (suggested by Dario Faggioli, Kevin Tian and Konrad Rzeszutek Wilk) - add SDM chapter title in commit message. (suggested by Konrad Rzeszutek Wilk) - add more explanations. (suggested by Kevin Tian) v4: - change file name to be more descriptive, 'intel_psr_l2_cat.pandoc'. (suggested by Dario Faggioli) - remove 'Ext' and 'New' prefixes. (suggested by Dario Faggioli) - remove change log in Revison part. (suggested by Dario Faggioli) - adjust Xen release number to 4.9 to show this feature targets 4.9. (suggested by Dario Faggioli) - provide 'Terminology' and more sections. (suggested by Dario Faggioli) - fix wordings. (suggested by Konrad Rzeszutek Wilk) - remove chapter number. (suggested by Konrad Rzeszutek Wilk) v3: - make design document be a patch. (suggested by Konrad Rzeszutek Wilk) v2: - provide chapter for the L2 CAT. (suggested by Meng Xu) --- docs/features/intel_psr_cat_cdp.pandoc | 469 + 1 file changed, 469 insertions(+) create mode 100644 docs/features/intel_psr_cat_cdp.pandoc diff --git a/docs/features/intel_psr_cat_cdp.pandoc b/docs/features/intel_psr_cat_cdp.pandoc new file mode 100644 index 000..022fbdc --- /dev/null +++ b/docs/features/intel_psr_cat_cdp.pandoc @@ -0,0 +1,469 @@ +% Intel Cache Allocation Technology and Code and Data Prioritization Features +% Revision 1.9 + +\clearpage + +# Basics + + + Status: **Tech Preview** + +Architecture(s): Intel x86 + + Component(s): Hypervisor, toolstack + + Hardware: L3 CAT: Haswell and beyond CPUs + CDP : Broadwell and beyond CPUs + L2 CAT: Atom codename Goldmont and beyond CPUs + + +# Terminology + +* CAT Cache Allocation Technology +* CBM Capacity BitMasks +* CDP Code and Data Prioritization +* CMT Cache Monitoring Technology +* COS/CLOSClass of Service +* MSRsMachine Specific Registers +* PSR Intel Platform Shared Resource + +# Overview + +Intel provides a set of allocation capabilities including Cache Allocatation +Technology (CAT) and Code and Data Prioritization (CDP). + +CAT allows an OS or hypervisor to control allocation of a CPU's shared cache +based on application/domain priority or Class of Service (COS). Each COS is +configured using capacity bitmasks (CBMs) which represent cache capacity and +indicate the degree of overlap and isolation between classes. Once CAT is co- +nfigured, the processor allows access to portions of cache according to the +established COS. Intel Xeon processor E5 v4 family (and some others) introduce +capabilities to configure and make use of the CAT mechanism on the L3 cache. +Intel Goldmont processor provides support for control over the L2 cache. + +Code and Data Prioritization (CDP) Technology is an extension of CAT. CDP +enables isolation and separate prioritization of code and data fetches to +the L3 cache in a SW configurable manner, which can enable workload priorit- +ization and tuning of cache capacity to the characteristics of the workload. +CDP extends CAT by providing separate code and data masks per Class of Service +(COS). When SW configures to enable CDP, L3 CAT is disabled. + +# User details + +* Feature Enabling: + + Add "psr=cat" to boot line parameter to enable all supported level CAT featu- + res. Add "psr=cdp" to enable L3 CDP but disables L3 CAT by SW. + +* xl interfaces: + + 1. `psr-cat-show [OPTIONS] domain-id`: + + Show
[Xen-devel] [PATCH v10 07/25] x86: refactor psr: L3 CAT: implement get hw info flow.
This patch implements get HW info flow including L3 CAT callback
function.
It also changes sysctl interface to make it more general.
With this patch, 'psr-hwinfo' can work for L3 CAT.
Signed-off-by: Yi Sun
---
v10:
- remove 'PSR_SOCKET_UNKNOWN' and use 'ASSERT_UNREACHABLE()' to handle
this case.
(suggested by Jan Beulich)
- check 'feat_type'.
(suggested by Jan Beulich)
- adjust macros names and values to make them more appropriate.
(suggested by Jan Beulich)
- use 'feat_init_done'.
(suggested by Jan Beulich)
- changes about 'cbm_len'.
(suggested by Jan Beulich)
v9:
- replace feature list handling to feature array handling.
(suggested by Roger Pau)
- define 'PSR_INFO_SIZE'.
(suggested by Roger Pau)
- fix coding style issue.
(suggested by Roger Pau and Jan Beulich)
- use 'ARRAY_SIZE'.
(suggested by Roger Pau)
- rename 'l3_cat_get_feat_info' to 'cat_get_feat_info' to make it a common
function for both L3/L2 CAT.
(suggested by Roger Pau)
- move constant to the right of comparison.
(suggested by Wei Liu)
- remove wrong comment.
(suggested by Jan Beulich)
- rename macros used by psr_get_info to make them meaningful.
(suggested by Jan Beulich)
- remove assignment for 'PSR_SOCKET_UNKNOWN'.
(suggested by Jan Beulich)
- retain blank line after 'case XEN_SYSCTL_PSR_CAT_get_l3_info'.
(suggested by Jan Beulich)
- modify patch title to indicate 'L3 CAT'.
(suggested by Jan Beulich)
- move common data check into common function.
(suggested by Jan Beulich)
v6:
- fix coding style issue.
(suggested by Konrad Rzeszutek Wilk)
- define 'PSR_SOCKET_UNKNOWN' in 'psr_feat_type'.
(suggested by Konrad Rzeszutek Wilk)
- change '-ENOTSOCK' to 'ERANGE'.
(suggested by Konrad Rzeszutek Wilk)
- modify position of macros to remove odd spacing in psr.h.
(suggested by Konrad Rzeszutek Wilk)
v5:
- change 'dat[]' to 'data[]'.
(suggested by Jan Beulich)
- modify parameter type to avoid fixed width type when there is no such
intention.
(suggested by Jan Beulich)
- use 'const' when it is possible.
(suggested by Jan Beulich)
- check feature type outside callback function.
(suggested by Jan Beulich)
- modify macros names to add prefix 'PSR_' and change 'CDP_FLAG' to
'PSR_FLAG'.
(suggested by Jan Beulich)
v4:
- create this patch to make codes easier to understand.
(suggested by Jan Beulich)
---
xen/arch/x86/psr.c| 75 +--
xen/arch/x86/sysctl.c | 19 +---
xen/include/asm-x86/psr.h | 16 ++
3 files changed, 98 insertions(+), 12 deletions(-)
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index 3421219..36ade48 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -93,6 +93,10 @@ struct feat_node {
unsigned int cos_num;
unsigned int cos_max;
unsigned int cbm_len;
+
+/* get_feat_info is used to get feature HW info. */
+bool (*get_feat_info)(const struct feat_node *feat,
+ uint32_t data[], unsigned int array_len);
} *props;
uint32_t cos_reg_val[MAX_COS_REG_CNT];
@@ -183,6 +187,22 @@ static bool feat_init_done(const struct psr_socket_info
*info)
return false;
}
+static enum psr_feat_type psr_cbm_type_to_feat_type(enum cbm_type type)
+{
+enum psr_feat_type feat_type;
+
+switch ( type )
+{
+case PSR_CBM_TYPE_L3:
+feat_type = PSR_SOCKET_L3_CAT;
+break;
+default:
+ASSERT_UNREACHABLE();
+}
+
+return feat_type;
+}
+
/* CAT common functions implementation. */
static void cat_init_feature(const struct cpuid_leaf *regs,
struct feat_node *feat,
@@ -232,9 +252,23 @@ static void cat_init_feature(const struct cpuid_leaf *regs,
socket, feat->props->cos_max, feat->props->cbm_len);
}
+static bool cat_get_feat_info(const struct feat_node *feat,
+ uint32_t data[], unsigned int array_len)
+{
+if ( array_len != PSR_INFO_ARRAY_SIZE )
+return false;
+
+data[PSR_INFO_IDX_COS_MAX] = feat->props->cos_max;
+data[PSR_INFO_IDX_CAT_CBM_LEN] = feat->props->cbm_len;
+data[PSR_INFO_IDX_CAT_FLAG] = 0;
+
+return true;
+}
+
/* L3 CAT ops */
static struct feat_props l3_cat_props = {
.cos_num = 1,
+.get_feat_info = cat_get_feat_info,
};
static void __init parse_psr_bool(char *s, char *value, char *feature,
@@ -446,10 +480,45 @@ void psr_ctxt_switch_to(struct domain *d)
}
}
-int psr_get_cat_l3_info(unsigned int socket, uint32_t *cbm_len,
-uint32_t *cos_max, uint32_t *flags)
+static struct psr_socket_info *get_socket_info(unsigned int socket)
{
-return 0;
+if ( !socket_info )
+return ERR_PTR(-ENODEV);
+
+if
[Xen-devel] [PATCH v10 10/25] x86: refactor psr: L3 CAT: set value: assemble features value array.
Only can one COS ID be used by one domain at one time. That means all enabled
features' COS registers at this COS ID are valid for this domain at that time.
When user updates a feature's value, we need make sure all other features'
values are not affected. So, we firstly need gather an array which contains
all features current values and replace the setting feature's value in array
to new value.
Then, we can try to find if there is a COS ID on which all features' COS
registers values are same as the array. If we can find, we just use this COS
ID. If fail to find, we need pick a new COS ID.
This patch implements value array assembling flow.
Signed-off-by: Yi Sun
---
v10:
- remove 'get_old_val' to directly call 'get_val' to get needed val.
(suggested by Jan Beulich)
- move 'psr_check_cbm' into 'insert_val_to_array'.
(suggested by Jan Beulich)
- change type of 'cbm' in 'psr_check_cbm' to 'unsigned long'.
(suggested by Jan Beulich)
- remove 'set_new_val' as it can be handled in generic process.
- changes related to 'feat_props'.
(suggested by Jan Beulich)
- adjust flow in 'gather_val_array' to avoid array cross.
(suggested by Jan Beulich)
- adjust flow in 'insert_val_to_array' to avoid array cross.
(suggested by Jan Beulich)
v9:
- add comments about boundary checking.
(suggested by Wei Liu)
- rename 'assemble_val_array' to 'combine_val_array' in pervious patch.
(suggested by Wei Liu)
- rename 'l3_cat_get_cos_num' to 'cat_get_cos_num' to cover all L3/L2 CAT
features.
(suggested by Roger Pau)
- rename 'l3_cat_get_old_val' to 'cat_get_old_val' to cover all L3/L2 CAT
features and reuse cat_get_val in it.
(suggested by Roger Pau)
- replace feature list handling to feature array handling.
(suggested by Roger Pau)
- modify patch title to indicate 'L3 CAT'.
(suggested by Jan Beulich)
- replace 'm' to 'new_val'.
(suggested by Jan Beulich)
- move cos check outside callback function.
(suggested by Jan Beulich)
- remove 'get_cos_num' callback function.
(suggested by Jan Beulich)
- changes about 'uint64_t' to 'uint32_t'.
(suggested by Jan Beulich)
v6:
- change 'assemble_val_array' to 'combine_val_array'.
(suggested by Konrad Rzeszutek Wilk)
- check return value of 'get_old_val'.
(suggested by Konrad Rzeszutek Wilk)
- replace some 'EINVAL' to 'ENOSPC'.
(suggested by Konrad Rzeszutek Wilk)
v5:
- modify comments according to changes of codes.
(suggested by Jan Beulich)
- change 'bool_t' to 'bool'.
(suggested by Jan Beulich)
- modify return value of callback functions because we do not need them
to return number of entries the feature uses. In caller, we call
'get_cos_num' to get the number of entries the feature uses.
(suggested by Jan Beulich)
- modify variables names to make them better, e.g. 'feat_tmp' to 'feat'.
(suggested by Jan Beulich)
v4:
- create this patch to make codes easier to understand.
(suggested by Jan Beulich)
---
xen/arch/x86/psr.c | 107 +++--
1 file changed, 104 insertions(+), 3 deletions(-)
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index 9d805d6..c912478 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -224,6 +224,29 @@ static enum psr_feat_type psr_cbm_type_to_feat_type(enum
cbm_type type)
}
/* CAT common functions implementation. */
+static bool psr_check_cbm(unsigned int cbm_len, unsigned long cbm)
+{
+unsigned int first_bit, zero_bit;
+
+/* Set bits should only in the range of [0, cbm_len]. */
+if ( cbm & (~0ul << cbm_len) )
+return false;
+
+/* At least one bit need to be set. */
+if ( cbm == 0 )
+return false;
+
+first_bit = find_first_bit(&cbm, cbm_len);
+zero_bit = find_next_zero_bit(&cbm, cbm_len, first_bit);
+
+/* Set bits should be contiguous. */
+if ( zero_bit < cbm_len &&
+ find_next_bit(&cbm, cbm_len, zero_bit) < cbm_len )
+return false;
+
+return true;
+}
+
static void cat_init_feature(const struct cpuid_leaf *regs,
struct feat_node *feat,
struct psr_socket_info *info,
@@ -593,7 +616,21 @@ int psr_get_val(struct domain *d, unsigned int socket,
/* Set value functions */
static unsigned int get_cos_num(const struct psr_socket_info *info)
{
-return 0;
+unsigned int num = 0, i;
+
+/* Get all features total amount. */
+for ( i = 0; i < PSR_SOCKET_MAX_FEAT; i++ )
+{
+const struct feat_node *feat = info->features[i];
+if ( !feat )
+continue;
+
+feat = info->features[i];
+
+num += feat->props->cos_num;
+}
+
+return num;
}
static int gather_val_array(uint32_t val[],
@@ -601,7 +638,38 @@ static int gather_val_array(uint32_t val[],
[Xen-devel] [PATCH v10 13/25] x86: refactor psr: L3 CAT: set value: implement write msr flow.
Continue from previous patch:
'x86: refactor psr: L3 CAT: set value: implement cos id picking flow.'
We have got the feature value and COS ID to set. Then, we write MSR of the
designated feature.
Till now, set value process is completed.
Signed-off-by: Yi Sun
---
v10:
- remove 'type' from 'write_msr' parameter list. Will add it back when
implementing CDP.
(suggested by Jan Beulich)
- remove unnecessary casts.
(suggested by Jan Beulich)
- changes about 'props'.
(suggested by Jan Beulich)
v9:
- replace feature list handling to feature array handling.
(suggested by Roger Pau)
- add 'array_len' in 'struct cos_write_info' and check if val array
exceeds it.
- modify 'write_psr_msr' flow only to set one value a time. No need to
set whole feature array values.
- modify patch title to indicate 'L3 CAT'.
(suggested by Jan Beulich)
- changes about 'uint64_t' to 'uint32_t'.
(suggested by Jan Beulich)
v8:
- modify 'write_msr' callback function to 'void' because we have to set
all features' cbm. When input cos exceeds some features' cos_max, just
skip them but not break the iteration.
v5:
- modify commit message to provide exact patch name to continue from.
(suggested by Jan Beulich)
- modify return value of callback functions because we do not need them
to return number of entries the feature uses. In caller, we call
'get_cos_num' to get the number of entries the feature uses.
(suggested by Jan Beulich)
- move type check out from callback functions to caller.
(suggested by Jan Beulich)
- modify variables names to make them better, e.g. 'feat_tmp' to 'feat'.
(suggested by Jan Beulich)
- correct code format.
(suggested by Jan Beulich)
v4:
- create this patch to make codes easier understand.
(suggested by Jan Beulich)
---
xen/arch/x86/psr.c | 63 +-
1 file changed, 62 insertions(+), 1 deletion(-)
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index 44c9313..0f57676 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -101,6 +101,10 @@ struct feat_node {
/* get_val is used to get feature COS register value. */
void (*get_val)(const struct feat_node *feat, unsigned int cos,
uint32_t *val);
+
+/* write_msr is used to write out feature MSR register. */
+void (*write_msr)(unsigned int cos, uint32_t val,
+ struct feat_node *feat);
} *props;
uint32_t cos_reg_val[MAX_COS_REG_CNT];
@@ -315,10 +319,21 @@ static void cat_get_val(const struct feat_node *feat,
unsigned int cos,
}
/* L3 CAT ops */
+static void l3_cat_write_msr(unsigned int cos, uint32_t val,
+ struct feat_node *feat)
+{
+if ( feat->cos_reg_val[cos] != val )
+{
+feat->cos_reg_val[cos] = val;
+wrmsrl(MSR_IA32_PSR_L3_MASK(cos), val);
+}
+}
+
static struct feat_props l3_cat_props = {
.cos_num = 1,
.get_feat_info = cat_get_feat_info,
.get_val = cat_get_val,
+.write_msr = l3_cat_write_msr,
};
static void __init parse_psr_bool(char *s, char *value, char *feature,
@@ -878,10 +893,56 @@ static int pick_avail_cos(const struct psr_socket_info
*info,
return -EOVERFLOW;
}
+static unsigned int get_socket_cpu(unsigned int socket)
+{
+if ( likely(socket < nr_sockets) )
+return cpumask_any(socket_cpumask[socket]);
+
+return nr_cpu_ids;
+}
+
+struct cos_write_info
+{
+unsigned int cos;
+struct feat_node *feature;
+uint32_t val;
+};
+
+static void do_write_psr_msr(void *data)
+{
+struct cos_write_info *info = data;
+unsigned int cos= info->cos;
+struct feat_node *feat = info->feature;
+
+if ( cos > feat->props->cos_max )
+return;
+
+feat->props->write_msr(cos, info->val, feat);
+}
+
static int write_psr_msr(unsigned int socket, unsigned int cos,
uint32_t val, enum psr_feat_type feat_type)
{
-return -ENOENT;
+struct psr_socket_info *info = get_socket_info(socket);
+struct cos_write_info data =
+{
+.cos = cos,
+.feature = info->features[feat_type],
+.val = val,
+};
+
+if ( socket == cpu_to_socket(smp_processor_id()) )
+do_write_psr_msr(&data);
+else
+{
+unsigned int cpu = get_socket_cpu(socket);
+
+if ( cpu >= nr_cpu_ids )
+return -ENOTSOCK;
+on_selected_cpus(cpumask_of(cpu), do_write_psr_msr, &data, 1);
+}
+
+return 0;
}
/* The whole set process is protected by domctl_lock. */
--
1.9.1
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[Xen-devel] [PATCH v10 17/25] x86: refactor psr: CDP: implement set value callback functions.
This patch implements L3 CDP set value related callback functions.
With this patch, 'psr-cat-cbm-set' command can work for L3 CDP.
Signed-off-by: Yi Sun
---
v10:
- remove 'l3_cdp_get_old_val' and use 'l3_cdp_get_val' to replace it.
(suggested by Jan Beulich)
- remove 'l3_cdp_set_new_val'.
- modify 'insert_val_to_array' flow to handle multiple COSs case.
(suggested by Jan Beulich)
- remove 'l3_cdp_compare_val' and implement a generic function
'comapre_val'.
(suggested by Jan Beulich)
- remove 'l3_cdp_fits_cos_max'.
(suggested by Jan Beulich)
- introduce macro 'PSR_MAX_COS_NUM'.
- introduce a new member in 'feat_props', 'type[PSR_MAX_COS_NUM]' to record
all 'cbm_type' the feature has.
(suggested by Jan Beulich)
- modify 'gather_val_array' flow to handle multiple COSs case.
(suggested by Jan Beulich)
- modify 'find_cos' flow and implement 'compare_val' to handle multiple
COSs case.
(suggested by Jan Beulich)
- modify 'fits_cos_max' flow to handle multiple COSs case.
(suggested by Jan Beulich)
- changes about 'props'.
(suggested by Jan Beulich)
- remove cast in 'l3_cdp_write_msr'.
(suggested by Jan Beulich)
- implement 'compare_val' function to compare if feature values are what
we expect in finding flow.
- implement 'restore_default_val' function to restore feature's COS values
to default if the feature has multiple COSs. It is called when the COS
ID is reduced to 0.
v9:
- add comment to explain why CDP uses 2 COSs.
(suggested by Wei Liu)
- use 'cat_default_val'.
(suggested by Wei Liu)
- remove 'l3_cdp_get_cos_num' because we can directly get cos_num from
feat_node now.
(suggested by Jan Beulich)
- remove cos checking because it has been moved to common function.
(suggested by Jan Beulich)
- l3_cdp_set_new_val parameter 'm' is changed to 'new_val'.
(suggested by Jan Beulich)
- directly use get_cdp_data(feat, 0) and get_cdp_code(feat, 0) to get
default value.
(suggested by Jan Beulich)
- modify 'l3_cdp_write_msr' flow to write value into register according
to input type.
- changes about 'uint64_t' to 'uint32_t'.
(suggested by Jan Beulich)
v8:
- modify 'l3_cdp_write_msr' type to 'void'.
v5:
- remove type check in callback function.
(suggested by Jan Beulich)
- modify return value of callback functions because we do not need them
to return number of entries the feature uses. In caller, we call
'get_cos_num' to get the number of entries the feature uses.
(suggested by Jan Beulich)
- remove 'l3_cdp_get_cos_max_from_type'.
- rename 'l3_cdp_exceeds_cos_max' to 'l3_cdp_fits_cos_max'.
(suggested by Jan Beulich)
v4:
- create this patch to make codes easier to understand.
(suggested by Jan Beulich)
---
xen/arch/x86/psr.c | 226 +++--
1 file changed, 183 insertions(+), 43 deletions(-)
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index aced012..bfa1777 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -51,6 +51,14 @@
#define PSR_ASSOC_REG_SHIFT 32
+/*
+ * Every PSR feature uses some COS registers for each COS ID, e.g. CDP uses 2
+ * COS registers (DATA and CODE) for one COS ID, but CAT uses 1 COS register.
+ * We use below macro as the max number of COS registers used by all features.
+ * So far, it is 2 which means CDP's COS registers number.
+ */
+#define PSR_MAX_COS_NUM 2
+
enum psr_feat_type {
PSR_SOCKET_L3_CAT,
PSR_SOCKET_L3_CDP,
@@ -94,6 +102,13 @@ struct feat_node {
unsigned int cos_max;
unsigned int cbm_len;
+/*
+ * An array to save all 'enum cbm_type' values of the feature. It is
+ * used with cos_num together to get/write a feature's COS registers
+ * values one by one.
+ */
+enum cbm_type type[PSR_MAX_COS_NUM];
+
/* get_feat_info is used to get feature HW info. */
bool (*get_feat_info)(const struct feat_node *feat,
uint32_t data[], unsigned int array_len);
@@ -104,7 +119,7 @@ struct feat_node {
/* write_msr is used to write out feature MSR register. */
void (*write_msr)(unsigned int cos, uint32_t val,
- struct feat_node *feat);
+ enum cbm_type type, struct feat_node *feat);
} *props;
uint32_t cos_reg_val[MAX_COS_REG_CNT];
@@ -292,6 +307,8 @@ static void cat_init_feature(const struct cpuid_leaf *regs,
/* cos=0 is reserved as default cbm(all bits within cbm_len are 1). */
feat->cos_reg_val[0] = cat_default_val(feat->props->cbm_len);
+feat->props->type[0] = PSR_CBM_TYPE_L3;
+
/*
* To handle cpu offline and then online case, we need restore MSRs to
* default values.
@@ -320,6 +337
[Xen-devel] [PATCH v10 03/25] x86: refactor psr: implement main data structures.
To construct an extendible framework, we need analyze PSR features and abstract the common things and feature specific things. Then, encapsulate them into different data structures. By analyzing PSR features, we can get below map. +--+--+--+ ->| Dom0 | Dom1 | ... | | +--+--+--+ || |Dom ID | cos_id of domain |V | +-+ User ->| PSR | Socket ID | +--+---+---+ | | | Socket0 Info | Socket 1 Info |...| | | +--+---+---+ | || cos_id=0 cos_id=1 ... | || +---+---+---+ | ||->Ref : | ref 0 | ref 1 | ... | | || +---+---+---+ | || +---+---+---+ | ||->L3 CAT: | cos 0 | cos 1 | ... | | || +---+---+---+ | || +---+---+---+ | ||->L2 CAT: | cos 0 | cos 1 | ... | | || +---+---+---+ | || +---+---+---+---+---+ | ||->CDP : | cos0 code | cos0 data | cos1 code | cos1 data | ... | | | +---+---+---+---+---+ | +-+ So, we need define a socket info data structure, 'struct psr_socket_info' to manage information per socket. It contains a reference count array according to COS ID and a feature array to manage all features enabled. Every entry of the reference count array is used to record how many domains are using the COS registers according to the COS ID. For example, L3 CAT and L2 CAT are enabled, Dom1 uses COS_ID=1 registers of both features to save CBM values, like below. +---+---+---+-+ | COS 0 | COS 1 | COS 2 | ... | +---+---+---+-+ L3 CAT | 0x7ff | 0x1ff | ... | ... | +---+---+---+-+ L2 CAT | 0xff | 0xff | ... | ... | +---+---+---+-+ If Dom2 has same CBM values, it can reuse these registers which COS_ID=1. That means, both Dom1 and Dom2 use same COS registers(ID=1) to keep same L3/L2 values. So, the value of ref[1] is 2 which means 2 domains are using COS_ID 1. To manage a feature, we need define a feature node data structure, 'struct feat_node', to manage feature's specific HW info, its common properties (callback functions - all feature's specific behaviors are encapsulated into these callback functions, and generic values - e.g. the cos_max), the feature independent values, and an array of all COS registers values of this feature. CDP is a special feature which uses two entries of the array for one COS ID. So, the number of CDP COS registers is the half of L3 CAT. E.g. L3 CAT has 16 COS registers, then CDP has 8 COS registers if it is enabled. CDP uses the COS registers array as below. +---+---+---+---+---+ CDP cos_reg_val[] index: | 0 | 1 | 2 | 3 | ...| +---+---+---+---+---+ value: | cos0 code | cos0 data | cos1 code | cos1 data | ...| +---+---+---+---+---+ For more details, please refer SDM and patches to implement 'get value' and 'set value'. Signed-off-by: Yi Sun --- v10: - remove initialization for 'PSR_SOCKET_L3_CAT'. (suggested by Jan Beulich) - rename 'feat_ops' to 'feat_props'. (suggested by Jan Beulich) - move 'cbm_len' to 'feat_props' because it is feature independent so far. (suggested by Jan Beulich) - move 'cos_max' to 'feat_props' because it is feature independent. (suggested by Jan Beulich) - move 'cos_num' to 'feat_props' because it is feature independent. (suggested by Jan Beulich) - remove union 'info' and struct 'psr_cat_hw_info'. - remove 'get_cos
[Xen-devel] [PATCH v10 04/25] x86: move cpuid_count_leaf from cpuid.c to processor.h.
This patch moves 'cpuid_count_leaf' from cpuid.c to processor.h to
make it available to external codes.
Signed-off-by: Yi Sun
Acked-by: Jan Beulich
---
v10:
- Acked by Jan.
v9:
- create this patch alone to move 'cpuid_count_leaf'.
(suggested by Wei Liu)
v6:
- use 'struct cpuid_leaf' in psr.c. So we have to access 'cpuid_count_leaf'
which has to be moved to processor.h.
(suggested by Andrew Cooper)
---
xen/arch/x86/cpuid.c| 6 --
xen/include/asm-x86/processor.h | 7 +++
2 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/xen/arch/x86/cpuid.c b/xen/arch/x86/cpuid.c
index d6f6b88..13a28ca 100644
--- a/xen/arch/x86/cpuid.c
+++ b/xen/arch/x86/cpuid.c
@@ -35,12 +35,6 @@ static void cpuid_leaf(uint32_t leaf, struct cpuid_leaf
*data)
cpuid(leaf, &data->a, &data->b, &data->c, &data->d);
}
-static void cpuid_count_leaf(uint32_t leaf, uint32_t subleaf,
- struct cpuid_leaf *data)
-{
-cpuid_count(leaf, subleaf, &data->a, &data->b, &data->c, &data->d);
-}
-
static void sanitise_featureset(uint32_t *fs)
{
/* for_each_set_bit() uses unsigned longs. Extend with zeroes. */
diff --git a/xen/include/asm-x86/processor.h b/xen/include/asm-x86/processor.h
index dda8b83..2588a1b 100644
--- a/xen/include/asm-x86/processor.h
+++ b/xen/include/asm-x86/processor.h
@@ -13,6 +13,7 @@
#include
#include
#include
+#include
#endif
#include
@@ -261,6 +262,12 @@ static always_inline unsigned int cpuid_count_ebx(
return ebx;
}
+static always_inline void cpuid_count_leaf(uint32_t leaf, uint32_t subleaf,
+ struct cpuid_leaf *data)
+{
+cpuid_count(leaf, subleaf, &data->a, &data->b, &data->c, &data->d);
+}
+
static inline unsigned long read_cr0(void)
{
unsigned long cr0;
--
1.9.1
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[Xen-devel] [PATCH v10 06/25] x86: refactor psr: L3 CAT: implement Domain init/free and schedule flows.
This patch implements the Domain init/free and schedule flows.
- When domain init, its psr resource should be allocated.
- When domain free, its psr resource should be freed too.
- When domain is scheduled, its COS ID on the socket should be
set into ASSOC register to make corresponding COS MSR value
work.
Signed-off-by: Yi Sun
---
v10:
- remove 'cat_get_cos_max' as 'cos_max' is a feature property now which
can be directly used.
(suggested by Jan Beulich)
- replace 'info->feat_mask' check to 'feat_init_done'.
(suggested by Jan Beulich)
v9:
- rename 'l3_cat_get_cos_max' to 'cat_get_cos_max' to cover all CAT/CDP
features.
(suggested by Roger Pau)
- replace feature list handling to feature array handling.
(suggested by Roger Pau)
- implement 'psr_alloc_cos' to match 'psr_free_cos'.
(suggested by Wei Liu)
- use 'psr_alloc_feat_enabled'.
(suggested by Wei Liu)
- fix coding style issue.
(suggested by Wei Liu)
- remove 'inline'.
(suggested by Jan Beulich)
- modify patch title to indicate 'L3 CAT'.
(suggested by Jan Beulich)
- remove 'psr_cos_ids' check in 'psr_free_cos'.
(suggested by Jan Beulich)
v6:
- change 'PSR_ASSOC_REG_POS' to 'PSR_ASSOC_REG_SHIFT'.
(suggested by Konrad Rzeszutek Wilk)
v5:
- rename 'feat_tmp' to 'feat'.
(suggested by Jan Beulich)
- define 'PSR_ASSOC_REG_POS'.
(suggested by Jan Beulich)
v4:
- create this patch to make codes easier to understand.
(suggested by Jan Beulich)
---
xen/arch/x86/psr.c | 71 +++---
1 file changed, 68 insertions(+), 3 deletions(-)
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index e422a23..3421219 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -49,6 +49,8 @@
*/
#define MAX_COS_REG_CNT 128
+#define PSR_ASSOC_REG_SHIFT 32
+
enum psr_feat_type {
PSR_SOCKET_L3_CAT,
PSR_SOCKET_L3_CDP,
@@ -376,11 +378,39 @@ void psr_free_rmid(struct domain *d)
d->arch.psr_rmid = 0;
}
-static inline void psr_assoc_init(void)
+static unsigned int get_max_cos_max(const struct psr_socket_info *info)
+{
+const struct feat_node *feat;
+unsigned int cos_max = 0, i;
+
+for ( i = 0; i < PSR_SOCKET_MAX_FEAT; i++ )
+{
+feat = info->features[i];
+if ( !feat )
+continue;
+
+cos_max = max(feat->props->cos_max, cos_max);
+}
+
+return cos_max;
+}
+
+static void psr_assoc_init(void)
{
struct psr_assoc *psra = &this_cpu(psr_assoc);
-if ( psr_cmt_enabled() )
+if ( psr_alloc_feat_enabled() )
+{
+unsigned int socket = cpu_to_socket(smp_processor_id());
+const struct psr_socket_info *info = socket_info + socket;
+unsigned int cos_max = get_max_cos_max(info);
+
+if ( feat_init_done(info) )
+psra->cos_mask = ((1ull << get_count_order(cos_max)) - 1) <<
+ PSR_ASSOC_REG_SHIFT;
+}
+
+if ( psr_cmt_enabled() || psra->cos_mask )
rdmsrl(MSR_IA32_PSR_ASSOC, psra->val);
}
@@ -389,6 +419,13 @@ static inline void psr_assoc_rmid(uint64_t *reg, unsigned
int rmid)
*reg = (*reg & ~rmid_mask) | (rmid & rmid_mask);
}
+static void psr_assoc_cos(uint64_t *reg, unsigned int cos,
+ uint64_t cos_mask)
+{
+*reg = (*reg & ~cos_mask) |
+(((uint64_t)cos << PSR_ASSOC_REG_SHIFT) & cos_mask);
+}
+
void psr_ctxt_switch_to(struct domain *d)
{
struct psr_assoc *psra = &this_cpu(psr_assoc);
@@ -397,6 +434,11 @@ void psr_ctxt_switch_to(struct domain *d)
if ( psr_cmt_enabled() )
psr_assoc_rmid(®, d->arch.psr_rmid);
+if ( psra->cos_mask )
+psr_assoc_cos(®, d->arch.psr_cos_ids ?
+ d->arch.psr_cos_ids[cpu_to_socket(smp_processor_id())] :
+ 0, psra->cos_mask);
+
if ( reg != psra->val )
{
wrmsrl(MSR_IA32_PSR_ASSOC, reg);
@@ -422,14 +464,37 @@ int psr_set_l3_cbm(struct domain *d, unsigned int socket,
return 0;
}
-int psr_domain_init(struct domain *d)
+/* Called with domain lock held, no extra lock needed for 'psr_cos_ids' */
+static void psr_free_cos(struct domain *d)
+{
+xfree(d->arch.psr_cos_ids);
+d->arch.psr_cos_ids = NULL;
+}
+
+static int psr_alloc_cos(struct domain *d)
{
+d->arch.psr_cos_ids = xzalloc_array(unsigned int, nr_sockets);
+if ( !d->arch.psr_cos_ids )
+return -ENOMEM;
+
return 0;
}
+int psr_domain_init(struct domain *d)
+{
+/* Init to success value */
+int ret = 0;
+
+if ( psr_alloc_feat_enabled() )
+ret = psr_alloc_cos(d);
+
+return ret;
+}
+
void psr_domain_free(struct domain *d)
{
psr_free_rmid(d);
+psr_free_cos(d);
}
static void __init init_psr(void)
--
1.9.1
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[Xen-devel] [PATCH v10 00/25] Enable L2 Cache Allocation Technology & Refactor psr.c
Hi all, We plan to bring a new PSR (Platform Shared Resource) feature called Intel L2 Cache Allocation Technology (L2 CAT) to Xen. It has been enabled in Linux Kernel. Besides the L2 CAT implementaion, we refactor the psr.c to make it more flexible and easily to extend to add new features. We abstract the general operations of all features and encapsulate them into a structure. Then, the development of new feature is simple to mainly implement these callback functions. The patch set can be found at: https://github.com/yisun-git/xen.git l2_cat_v10 --- Acked and Reviewed list before V10: a - Acked-by r - Reviewed-by r patch 1 - docs: create Cache Allocation Technology (CAT) and Code and Data Prioritization (CDP) feature document ar patch 2 - x86: refactor psr: remove L3 CAT/CDP codes. a patch 4 - x86: move cpuid_count_leaf from cpuid.c to processor.h. a patch 25 - docs: add L2 CAT description in docs. --- V10 change list: Patch 3: - remove initialization for 'PSR_SOCKET_L3_CAT'. (suggested by Jan Beulich) - rename 'feat_ops' to 'feat_props'. (suggested by Jan Beulich) - move 'cbm_len' to 'feat_props' because it is feature independent so far. (suggested by Jan Beulich) - move 'cos_max' to 'feat_props' because it is feature independent. (suggested by Jan Beulich) - move 'cos_num' to 'feat_props' because it is feature independent. (suggested by Jan Beulich) - remove union 'info' and struct 'psr_cat_hw_info'. - remove 'get_cos_max' from 'feat_props'. (suggested by Jan Beulich) - remove 'feat_mask' from 'psr_socket_info' because we can use 'features[]' to check if any feature is initialized. (suggested by Jan Beulich) - move 'ref_lock' above 'cos_ref'. (suggested by Jan Beulich) - adjust comments and commit message according to above changes. Patch 4: - Acked by Jan. Patch 5: - remove 'asm/x86_emulate.h' inclusion as it has been indirectly included. (suggested by Jan Beulich) - remove 'CAT_COS_NUM' as it is only used once. (suggested by Jan Beulich) - remove 'feat_mask'. (suggested by Jan Beulich) - changes about 'feat_props'. (suggested by Jan Beulich) - remove 'get_cos_max' hook declaration. (suggested by Jan Beulich) - modify 'cat_default_val' implementation. (suggested by Jan Beulich) - modify 'psr_alloc_feat_enabled' implementation to make it simple. (suggested by Jan Beulich) - rename 'free_feature' to 'free_socket_resources' because it is executed when socket is offline. It needs free resources related to the socket. (suggested by Jan Beulich) - define 'feat_init_done' to iterate feature array to check if any feature has been initialized. (suggested by Jan Beulich) - input 'struct cpuid_leaf' pointer into 'cat_init_feature' to avoid memory copy. (suggested by Jan Beulich) - modify 'cat_init_feature' to use switch and things related to above changes. (suggested by Jan Beulich) - add an indentation for label. (suggested by Jan Beulich) Patch 6: - remove 'cat_get_cos_max' as 'cos_max' is a feature property now which can be directly used. (suggested by Jan Beulich) - replace 'info->feat_mask' check to ''feat_init_done'. (suggested by Jan Beulich) Patch 7: - remove 'PSR_SOCKET_UNKNOWN' and use 'ASSERT_UNREACHABLE()' to handle this case. (suggested by Jan Beulich) - check 'feat_type'. (suggested by Jan Beulich) - adjust macros names and values to make them more appropriate. (suggested by Jan Beulich) - use 'feat_init_done'. (suggested by Jan Beulich) - changes about 'cbm_len'. (suggested by Jan Beulich) Patch 8: - use an intermediate variable to get value and avoid cast in domctl. (suggested by Jan Beulich) - remove 'type' in 'get_val' parameters and will add it back when implementing CDP. (suggested by Jan Beulich) - add 'err' in 'psr_get_feat' parameters to get error number back. (suggested by Jan Beulich) - remove unnecessary variable in 'psr_get_feat'. (suggested by Jan Beulich) - use 'ASSET' to check input parameter in 'psr_get_val'. (suggested by Jan Beulich) - changes about 'feat_props'. (suggested by Jan Beulich) Patch 9: - restore domain cos id to 0 when socket is offline. (suggested by Jan Beulich) - check 'psr_cat_op.data' to make sure only lower 32 bits are valid. (suggested by Jan Beulich) - remove unnecessary fixed width type of parameters and variables. (suggested by Jan Beulich) - rename 'insert_new_val_to_array' to 'insert_val_to_array'. (suggested by Jan Beulich) - input 'ref_lock' pointer into functions to check if it has been locked. (suggested by Jan Beulich) - add comment to declare the set process is protected by 'do
[Xen-devel] [PATCH v10 16/25] x86: refactor psr: CDP: implement get value flow.
This patch implements L3 CDP get value callback function.
With this patch, 'psr-cat-show' can work for L3 CDP.
Signed-off-by: Yi Sun
---
v10:
- add 'enum cbm_type type' into 'get_val' parameters to handle CDP case.
(suggested by Jan Beulich)
v9:
- modify the type of 'l3_cdp_get_val' to 'void'.
- cos checking has been done in common function so remove related codes
in CDP callback function.
(suggested by Jan Beulich)
- changes about 'uint64_t' to 'uint32_t'.
(suggested by Jan Beulich)
v5:
- remove type check in callback function.
(suggested by Jan Beulich)
v4:
- create this patch to make codes easier to understand.
(suggested by Jan Beulich)
---
xen/arch/x86/psr.c | 22 --
1 file changed, 16 insertions(+), 6 deletions(-)
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index f0611ad..aced012 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -100,7 +100,7 @@ struct feat_node {
/* get_val is used to get feature COS register value. */
void (*get_val)(const struct feat_node *feat, unsigned int cos,
-uint32_t *val);
+enum cbm_type type, uint32_t *val);
/* write_msr is used to write out feature MSR register. */
void (*write_msr)(unsigned int cos, uint32_t val,
@@ -366,7 +366,7 @@ static bool cat_get_feat_info(const struct feat_node *feat,
}
static void cat_get_val(const struct feat_node *feat, unsigned int cos,
-uint32_t *val)
+enum cbm_type type, uint32_t *val)
{
*val = feat->cos_reg_val[cos];
}
@@ -401,9 +401,19 @@ static bool l3_cdp_get_feat_info(const struct feat_node
*feat,
return true;
}
+static void l3_cdp_get_val(const struct feat_node *feat, unsigned int cos,
+ enum cbm_type type, uint32_t *val)
+{
+if ( type == PSR_CBM_TYPE_L3_DATA )
+*val = get_cdp_data(feat, cos);
+else
+*val = get_cdp_code(feat, cos);
+}
+
static struct feat_props l3_cdp_props = {
.cos_num = 2,
.get_feat_info = l3_cdp_get_feat_info,
+.get_val = l3_cdp_get_val,
};
static void __init parse_psr_bool(char *s, char *value, char *feature,
@@ -701,7 +711,7 @@ int psr_get_val(struct domain *d, unsigned int socket,
if ( cos > feat->props->cos_max )
cos = 0;
-feat->props->get_val(feat, cos, val);
+feat->props->get_val(feat, cos, type, val);
return 0;
}
@@ -755,7 +765,7 @@ static int gather_val_array(uint32_t val[],
cos = 0;
/* Value getting order is same as feature array. */
-feat->props->get_val(feat, cos, &val[0]);
+feat->props->get_val(feat, cos, 0, &val[0]);
array_len -= feat->props->cos_num;
@@ -851,7 +861,7 @@ static int find_cos(const uint32_t val[], unsigned int
array_len,
* COS ID 0 always stores the default value so input 0 to get
* default value.
*/
-feat->props->get_val(feat, 0, &default_val);
+feat->props->get_val(feat, 0, 0, &default_val);
/*
* Compare value according to feature array order.
@@ -912,7 +922,7 @@ static bool fits_cos_max(const uint32_t val[],
if ( cos > feat->props->cos_max )
{
-feat->props->get_val(feat, 0, &default_val);
+feat->props->get_val(feat, 0, 0, &default_val);
if ( val[0] != default_val )
return false;
}
--
1.9.1
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[Xen-devel] [PATCH v10 12/25] x86: refactor psr: L3 CAT: set value: implement cos id picking flow.
Continue from previous patch:
'x86: refactor psr: L3 CAT: set value: implement cos finding flow.'
If fail to find a COS ID, we need pick a new COS ID for domain. Only COS ID
that ref[COS_ID] is 1 or 0 can be picked to input a new set feature values.
Signed-off-by: Yi Sun
---
v10:
- remove 'fits_cos_max' hook and CAT implementation. Move the process into
generic flow.
(suggested by Jan Beulich)
- changes about 'props'.
(suggested by Jan Beulich)
- adjust codes positions.
(suggested by Jan Beulich)
v9:
- modify return value of 'pick_avail_cos' to make it more accurate.
- rename 'l3_cat_fits_cos_max' to 'cat_fits_cos_max' to cover L3/L2 CAT
features.
(suggested by Roger Pau)
- replace feature list handling to feature array handling.
(suggested by Roger Pau)
- fix comment.
(suggested by Wei Liu)
- directly use 'cos_reg_val[0]' as default value.
(suggested by Jan Beulich)
- replace 'get_cos_num' to 'feat->cos_num'.
(suggested by Jan Beulich)
- modify patch title to indicate 'L3 CAT'.
(suggested by Jan Beulich)
- changes about 'uint64_t' to 'uint32_t'.
(suggested by Jan Beulich)
v5:
- modify commit message to provide exact patch name to continue from.
(suggested by Jan Beulich)
- change 'exceeds_cos_max' to 'fits_cos_max' to be accurate.
(suggested by Jan Beulich)
- modify comments according to changes of codes.
(suggested by Jan Beulich)
- modify return value of callback functions because we do not need them
to return number of entries the feature uses. In caller, we call
'get_cos_num' to get the number of entries the feature uses.
(suggested by Jan Beulich)
- move type check out from callback functions to caller.
(suggested by Jan Beulich)
- modify variables names to make them better, e.g. 'feat_tmp' to 'feat'.
(suggested by Jan Beulich)
- modify code format.
(suggested by Jan Beulich)
v4:
- create this patch to make codes easier to understand.
(suggested by Jan Beulich)
---
xen/arch/x86/psr.c | 69 +-
1 file changed, 68 insertions(+), 1 deletion(-)
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index a6c6f18..44c9313 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -800,15 +800,82 @@ static int find_cos(const uint32_t val[], unsigned int
array_len,
return -ENOENT;
}
+static bool fits_cos_max(const uint32_t val[],
+ uint32_t array_len,
+ const struct psr_socket_info *info,
+ unsigned int cos)
+{
+unsigned int i;
+
+for ( i = 0; i < PSR_SOCKET_MAX_FEAT; i++ )
+{
+uint32_t default_val = 0;
+const struct feat_node *feat = info->features[i];
+if ( !feat )
+continue;
+
+if ( array_len < feat->props->cos_num )
+return false;
+
+if ( cos > feat->props->cos_max )
+{
+feat->props->get_val(feat, 0, &default_val);
+if ( val[0] != default_val )
+return false;
+}
+
+array_len -= feat->props->cos_num;
+
+val += feat->props->cos_num;
+}
+
+return true;
+}
+
static int pick_avail_cos(const struct psr_socket_info *info,
spinlock_t *ref_lock,
const uint32_t val[], unsigned int array_len,
unsigned int old_cos,
enum psr_feat_type feat_type)
{
+unsigned int cos;
+unsigned int cos_max = 0;
+const struct feat_node *feat;
+const unsigned int *ref = info->cos_ref;
+
ASSERT(spin_is_locked(ref_lock));
-return -ENOENT;
+/* cos_max is the one of the feature which is being set. */
+feat = info->features[feat_type];
+if ( !feat )
+return -ENOENT;
+
+cos_max = feat->props->cos_max;
+if ( !cos_max )
+return -ENOENT;
+
+/* We cannot use id 0 because it stores the default values. */
+if ( old_cos && ref[old_cos] == 1 &&
+ fits_cos_max(val, array_len, info, old_cos) )
+return old_cos;
+
+/* Find an unused one other than cos0. */
+for ( cos = 1; cos <= cos_max; cos++ )
+{
+/*
+ * ref is 0 means this COS is not used by other domain and
+ * can be used for current setting.
+ */
+if ( !ref[cos] )
+{
+if ( !fits_cos_max(val, array_len, info, cos) )
+break;
+
+return cos;
+}
+}
+
+return -EOVERFLOW;
}
static int write_psr_msr(unsigned int socket, unsigned int cos,
--
1.9.1
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[Xen-devel] [PATCH v10 05/25] x86: refactor psr: L3 CAT: implement CPU init and free flow.
This patch implements the CPU init and free flow including L3 CAT initialization and some resources free. It includes below flows: 1. presmp init: - parse command line parameter. - allocate socket info for every socket. - allocate feature resource. - initialize socket info, get feature info and add feature into feature array per cpuid result. - free resources allocated if error happens. - register cpu notifier to handle cpu events. 2. cpu notifier: - handle cpu online events, if initialization work has been done before, do nothing. - handle cpu offline events, if it is the last cpu offline, free some socket resources. Signed-off-by: Yi Sun --- v10: - remove 'asm/x86_emulate.h' inclusion as it has been indirectly included. (suggested by Jan Beulich) - remove 'CAT_COS_NUM' as it is only used once. (suggested by Jan Beulich) - remove 'feat_mask'. (suggested by Jan Beulich) - changes about 'feat_props'. (suggested by Jan Beulich) - remove 'get_cos_max' hook declaration. (suggested by Jan Beulich) - modify 'cat_default_val' implementation. (suggested by Jan Beulich) - modify 'psr_alloc_feat_enabled' implementation to make it simple. (suggested by Jan Beulich) - rename 'free_feature' to 'free_socket_resources' because it is executed when socket is offline. It needs free resources related to the socket. (suggested by Jan Beulich) - define 'feat_init_done' to iterate feature array to check if any feature has been initialized. (suggested by Jan Beulich) - input 'struct cpuid_leaf' pointer into 'cat_init_feature' to avoid memory copy. (suggested by Jan Beulich) - modify 'cat_init_feature' to use switch and things related to above changes. (suggested by Jan Beulich) - add an indentation for label. (suggested by Jan Beulich) v9: - add commit message to explain the flows. - handle cpu offline and online again case to read MSRs registers values back and save them into cos array to make user can get real data. - create a new patch about moving 'cpuid_count_leaf'. (suggested by Wei Liu) - modify comment to explain why not free some resource in 'free_feature'. (suggested by Wei Liu) - implement 'psr_alloc_feat_enabled' to check if allocation feature is enabled in cmdline and some initialization work done. (suggested by Wei Liu) - implement 'cat_default_val' to set default value for CAT features. (suggested by Wei Liu) - replace feature list handling to feature array handling. (suggested by Roger Pau) - implement a common 'cat_init_feature' to replace L3 CAT/L2 CAT specific init functions. (suggested by Roger Pau) - modify comments for global feature node. (suggested by Jan Beulich) - remove unnecessary comments. (suggested by Jan Beulich) - remove unnecessary 'else'. (suggested by Jan Beulich) - remove 'nr_feat'. (suggested by Jan Beulich) - modify patch title to indicate 'L3 CAT'. (suggested by Jan Beulich) - check global flag with boot cpu operations. (suggested by Jan Beulich) - remove 'cpu_init_work' and move codes into 'psr_cpu_init'. (suggested by Jan Beulich) - remove 'cpu_fini_work' and move codes into 'psr_cpu_fini'. (suggested by Jan Beulich) - assign value for 'cos_num'. (suggested by Jan Beulich) - change about 'uint64_t' to 'uint32_t'. (suggested by Jan Beulich) v8: - fix format issue. (suggested by Konrad Rzeszutek Wilk) - add comments to explain why we care about cpumask_empty when the last cpu on socket is offline. (suggested by Konrad Rzeszutek Wilk) v7: - initialize structure objects for avoiding surprise. (suggested by Konrad Rzeszutek Wilk) - fix typo. (suggested by Konrad Rzeszutek Wilk) - fix a logical mistake when handling the last cpu offline event. (suggested by Konrad Rzeszutek Wilk) v6: - use 'struct cpuid_leaf' introduced in Andrew's patch. (suggested by Konrad Rzeszutek Wilk) - add comments about cpu_add_remove_lock. (suggested by Konrad Rzeszutek Wilk) - change 'clear_bit' to '__clear_bit'. (suggested by Konrad Rzeszutek Wilk) - add 'ASSERT' check when setting 'feat_mask'. (suggested by Konrad Rzeszutek Wilk) - adjust 'printk' position to avoid odd spacing. (suggested by Konrad Rzeszutek Wilk) - add comment to explain usage of 'feat_l3_cat'. (suggested by Konrad Rzeszutek Wilk) - fix wording. (suggested by Konrad Rzeszutek Wilk) - move 'cpuid_count_leaf' helper function to 'asm-x86/processor.h'. It cannot be moved to 'cpuid.h' which causes compilation error because of header file loop reference. (suggested by Andrew Cooper) v5: - add comment to explain the reason to def
[Xen-devel] [PATCH v10 09/25] x86: refactor psr: L3 CAT: set value: implement framework.
As set value flow is the most complicated one in psr, it will be divided to some patches to make things clearer. This patch implements the set value framework to show a whole picture firstly. It also changes domctl interface to make it more general. To make the set value flow be general and can support multiple features at same time, it includes below steps: 1. Get COS ID that current domain is using. 2. Gather a value array to store all features current value into it and replace the current value of the feature which is being set to the new input value. 3. Find if there is already a COS ID on which all features' values are same as the array. Then, we can reuse this COS ID. 4. If fail to find, we need pick an available COS ID. Only COS ID which ref is 0 or 1 can be picked. 5. Write the feature's MSR according to the COS ID and cbm_type. 6. Update ref according to COS ID. 7. Save the COS ID into current domain's psr_cos_ids[socket] so that we can know which COS the domain is using on the socket. So, some functions are abstracted and the callback functions will be implemented in next patches. Here is an example to understand the process. The CPU supports two featuers, e.g. L3 CAT and L2 CAT. User wants to set L3 CAT of Dom1 to 0x1ff. 1. At the initial time, the old_cos of Dom1 is 0. The COS registers values are below at this time. --- | COS 0 | COS 1 | COS 2 | ... | --- L3 CAT | 0x7ff | 0x7ff | 0x7ff | ... | --- L2 CAT | 0xff | 0xff | 0xff | ... | --- 2. Gather the value array and insert new value into it: val[0]: 0x1ff val[1]: 0xff 3. It cannot find a matching COS. 4. Pick COS 1 to store the value set. 5. Write the L3 CAT COS 1 registers. The COS registers values are changed to below now. --- | COS 0 | COS 1 | COS 2 | ... | --- L3 CAT | 0x7ff | 0x1ff | ... | ... | --- L2 CAT | 0xff | 0xff | ... | ... | --- 6. The ref[1] is increased to 1 because Dom1 is using it now. 7. Save 1 to Dom1's psr_cos_ids[socket]. Then, user wants to set L3 CAT of Dom2 to 0x1ff too. The old_cos of Dom2 is 0 too. Repeat above flow. The val array assembled is: val[0]: 0x1ff val[1]: 0xff So, it can find a matching COS, COS 1. Then, it can reuse COS 1 for Dom2. The ref[1] is increased to 2 now because both Dom1 and Dom2 are using this COS ID. Set 1 to Dom2's psr_cos_ids[socket]. Another thing need to emphasize is the context switch. When context switch happens, 'psr_ctxt_switch_to' is called by system to get domain's COS ID from 'psr_cos_ids[socket]'. But 'psr_cos_ids[socket]' is set at step 7 above. So, there are three scenarios, e.g.: 1. User calls domctl interface on Dom0 to set a COS ID 1 for Dom1 into its psr_cos_ids[]. Then, Dom1 is scheduled so that 'psr_ctxt_switch_to()' is called which makes COS ID 1 work. For this case, no action is needed. 2. Dom1 runs on CPU 1 and COS ID 1 is working. At same time, user calls domctl interface on Dom0 to set a new COS ID 2 for Dom1 into psr_cos_ids[]. After time slice ends, the Dom1 is scheduled again, the new COS ID 2 will work. 3. When a new COS ID is being set to psr_cos_ids[], 'psr_ctxt_switch_to()' is called to access the same psr_cos_ids[] member through 'psr_assoc_cos'. The COS ID is constrained by cos_mask so that it cannot exceeds the cos_max. So even the COS ID got here is wrong, it is still a workable ID (within cos_max). The functionality is still workable, the actual valid CBM will be effective for a short time. In next schedule, the correct CBM will take effect. All these cases will not cause race condition and no harm to system. The PSR features are to set cache capacity for a domain. The setting to cache is progressively effective. When the cache setting becomes really effective, the time slice to schedule a domain may have passed. So, even if a wrong COS ID is used to set ASSOC, only another valid CBM be effective for a short time during cache preparation time. The correct COS ID will take effect in a short time. This does not affect cache capacity setting much. Signed-off-by: Yi Sun --- v10: - restore domain cos id to 0 when socket is offline. (suggested by Jan Beulich) - check 'psr_cat_op.data' to make sure only lower 32 bits are valid. (suggested by Jan Beulich) - remove unnecessary fixed width type of parameters and variables. (suggested by Jan Beulich) - rename 'insert_new_val_to_array' to 'insert_val_to_array'. (suggested by Jan Beulich) - input 'ref_lock' pointer into functions to check if it has been locked. (suggested by Jan Beulich) - add comment to declare the set process is protected by 'domctl_lock'. (suggested by Jan Beulic
[Xen-devel] [PATCH v10 02/25] x86: refactor psr: remove L3 CAT/CDP codes.
The current cache allocation codes in psr.c do not consider
future features addition and are not friendly to extend.
To make psr.c be more flexible to add new features and fulfill
the program principle, open for extension but closed for
modification, we have to refactor the psr.c:
1. Analyze cache allocation features and abstract general data
structures.
2. Analyze the init and all other functions flow, abstract all
steps that different features may have different implementations.
Make these steps be callback functions and register feature
specific fuctions. Then, the main processes will not be changed
when introducing a new feature.
Because the quantity of refactor codes is big and the logics are
changed a lot, it will cause reviewers confused if just change
old codes. Reviewers have to understand both old codes and new
implementations. After review iterations from V1 to V3, Jan has
proposed to remove all old cache allocation codes firstly, then
implement new codes step by step. This will help to make codes
be more easily reviewable.
There is no construction without destruction. So, this patch
removes all current L3 CAT/CDP codes in psr.c. The following
patches will introduce the new mechanism.
Signed-off-by: Yi Sun
Acked-by: Jan Beulich
Reviewed-by: Konrad Rzeszutek Wilk
Reviewed-by: Wei Liu
---
v4:
- create this patch to make codes easily understand.
(suggested by Jan Beulich)
---
xen/arch/x86/psr.c | 470 +
1 file changed, 5 insertions(+), 465 deletions(-)
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index 0b5073c..96a8589 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -23,24 +23,6 @@
#define PSR_CAT(1<<1)
#define PSR_CDP(1<<2)
-struct psr_cat_cbm {
-union {
-uint64_t cbm;
-struct {
-uint64_t code;
-uint64_t data;
-};
-};
-unsigned int ref;
-};
-
-struct psr_cat_socket_info {
-unsigned int cbm_len;
-unsigned int cos_max;
-struct psr_cat_cbm *cos_to_cbm;
-spinlock_t cbm_lock;
-};
-
struct psr_assoc {
uint64_t val;
uint64_t cos_mask;
@@ -48,26 +30,11 @@ struct psr_assoc {
struct psr_cmt *__read_mostly psr_cmt;
-static unsigned long *__read_mostly cat_socket_enable;
-static struct psr_cat_socket_info *__read_mostly cat_socket_info;
-static unsigned long *__read_mostly cdp_socket_enable;
-
static unsigned int opt_psr;
static unsigned int __initdata opt_rmid_max = 255;
-static unsigned int __read_mostly opt_cos_max = 255;
static uint64_t rmid_mask;
static DEFINE_PER_CPU(struct psr_assoc, psr_assoc);
-static struct psr_cat_cbm *temp_cos_to_cbm;
-
-static unsigned int get_socket_cpu(unsigned int socket)
-{
-if ( likely(socket < nr_sockets) )
-return cpumask_any(socket_cpumask[socket]);
-
-return nr_cpu_ids;
-}
-
static void __init parse_psr_bool(char *s, char *value, char *feature,
unsigned int mask)
{
@@ -107,9 +74,6 @@ static void __init parse_psr_param(char *s)
if ( val_str && !strcmp(s, "rmid_max") )
opt_rmid_max = simple_strtoul(val_str, NULL, 0);
-if ( val_str && !strcmp(s, "cos_max") )
-opt_cos_max = simple_strtoul(val_str, NULL, 0);
-
s = ss + 1;
} while ( ss );
}
@@ -213,16 +177,7 @@ static inline void psr_assoc_init(void)
{
struct psr_assoc *psra = &this_cpu(psr_assoc);
-if ( cat_socket_info )
-{
-unsigned int socket = cpu_to_socket(smp_processor_id());
-
-if ( test_bit(socket, cat_socket_enable) )
-psra->cos_mask = ((1ull << get_count_order(
- cat_socket_info[socket].cos_max)) - 1) << 32;
-}
-
-if ( psr_cmt_enabled() || psra->cos_mask )
+if ( psr_cmt_enabled() )
rdmsrl(MSR_IA32_PSR_ASSOC, psra->val);
}
@@ -231,12 +186,6 @@ static inline void psr_assoc_rmid(uint64_t *reg, unsigned
int rmid)
*reg = (*reg & ~rmid_mask) | (rmid & rmid_mask);
}
-static inline void psr_assoc_cos(uint64_t *reg, unsigned int cos,
- uint64_t cos_mask)
-{
-*reg = (*reg & ~cos_mask) | (((uint64_t)cos << 32) & cos_mask);
-}
-
void psr_ctxt_switch_to(struct domain *d)
{
struct psr_assoc *psra = &this_cpu(psr_assoc);
@@ -245,459 +194,54 @@ void psr_ctxt_switch_to(struct domain *d)
if ( psr_cmt_enabled() )
psr_assoc_rmid(®, d->arch.psr_rmid);
-if ( psra->cos_mask )
-psr_assoc_cos(®, d->arch.psr_cos_ids ?
- d->arch.psr_cos_ids[cpu_to_socket(smp_processor_id())] :
- 0, psra->cos_mask);
-
if ( reg != psra->val )
{
wrmsrl(MSR_IA32_PSR_ASSOC, reg);
psra->val = reg;
}
}
-static struct psr_cat_socket_info *get_cat_socket_info(unsigned int socket)
-{
-if ( !cat_socket_info )
-return ERR_PTR(-ENODEV);
-
-if ( socket >= nr_sockets )
-ret
[Xen-devel] [PATCH v10 11/25] x86: refactor psr: L3 CAT: set value: implement cos finding flow.
Continue from patch:
'x86: refactor psr: L3 CAT: set value: assemble features value array'
We can try to find if there is a COS ID on which all features' COS registers
values are same as the array assembled before.
Signed-off-by: Yi Sun
---
v10:
- remove 'compare_val' hook and its CAT implementation. Make its
functionality be generic in 'find_cos' flow.
(suggested by Jan Beulich)
- changes related to 'props'.
(suggested by Jan Beulich)
- rename 'val_array' to 'val_ptr'.
(suggested by Jan Beulich)
- rename 'find' to 'found'.
(suggested by Jan Beulich)
- move some variables declaration and initialization into loop.
(suggested by Jan Beulich)
- adjust codes positions.
(suggested by Jan Beulich)
v9:
- modify comments of 'compare_val' to be same as current implementation.
(suggested by Wei Liu)
- fix indentation issue.
(suggested by Wei Liu)
- rename 'l3_cat_compare_val' to 'cat_compare_val' to cover all L3/L2 CAT
features.
(suggested by Roger Pau)
- remove parameter 'found' from 'cat_compare_val' and modify the return
values to let caller know if the id is found or not.
(suggested by Roger Pau)
- replace feature list handling to feature array handling.
(suggested by Roger Pau)
- replace 'get_cos_num' to 'feat->cos_num'.
(suggested by Jan Beulich)
- directly use 'cos_reg_val[0]' as default value.
(suggested by Jan Beulich)
- modify patch title to indicate 'L3 CAT'.
(suggested by Jan Beulich)
- changes about 'uint64_t' to 'uint32_t'.
(suggested by Jan Beulich)
v5:
- modify commit message to provide exact patch name to continue from.
(suggested by Jan Beulich)
- remove 'get_cos_max_from_type' because it can be replaced by
'get_cos_max'.
- move type check out from callback functions to caller.
(suggested by Jan Beulich)
- modify variables names to make them better, e.g. 'feat_tmp' to 'feat'.
(suggested by Jan Beulich)
- modify comments according to changes of codes.
(suggested by Jan Beulich)
v4:
- create this patch to make codes easier to understand.
(suggested by Jan Beulich)
---
xen/arch/x86/psr.c | 75 ++
1 file changed, 75 insertions(+)
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index c912478..a6c6f18 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -720,8 +720,83 @@ static int find_cos(const uint32_t val[], unsigned int
array_len,
const struct psr_socket_info *info,
spinlock_t *ref_lock)
{
+unsigned int cos, i;
+const unsigned int *ref = info->cos_ref;
+const struct feat_node *feat;
+unsigned int cos_max;
+
ASSERT(spin_is_locked(ref_lock));
+/* cos_max is the one of the feature which is being set. */
+feat = info->features[feat_type];
+if ( !feat )
+return -ENOENT;
+
+cos_max = feat->props->cos_max;
+
+for ( cos = 0; cos <= cos_max; cos++ )
+{
+const uint32_t *val_ptr = val;
+bool found = false;
+
+if ( cos && !ref[cos] )
+continue;
+
+/*
+ * If fail to find cos in below loop, need find whole feature array
+ * again from beginning.
+ */
+for ( i = 0; i < PSR_SOCKET_MAX_FEAT; i++ )
+{
+uint32_t default_val = 0;
+
+feat = info->features[i];
+if ( !feat )
+continue;
+
+/*
+ * COS ID 0 always stores the default value so input 0 to get
+ * default value.
+ */
+feat->props->get_val(feat, 0, &default_val);
+
+/*
+ * Compare value according to feature array order.
+ * We must follow this order because value array is assembled
+ * as this order.
+ */
+if ( cos > feat->props->cos_max )
+{
+/*
+ * If cos is bigger than feature's cos_max, the val should be
+ * default value. Otherwise, it fails to find a COS ID. So we
+ * have to exit find flow.
+ */
+if ( val[0] != default_val )
+return -EINVAL;
+
+found = true;
+}
+else
+{
+if ( val[0] == feat->cos_reg_val[cos] )
+found = true;
+}
+
+/* If fail to match, go to next cos to compare. */
+if ( !found )
+break;
+
+val_ptr += feat->props->cos_num;
+if ( val_ptr - val > array_len )
+return -ENOSPC;
+}
+
+/* For this COS ID all entries in the values array do match. Use it. */
+if ( found )
+return cos;
+}
+
return -ENOENT;
}
--
1.9.1
__
[Xen-devel] [PATCH v10 14/25] x86: refactor psr: CDP: implement CPU init and free flow.
This patch implements the CPU init and free flow for CDP including L3 CDP
initialization callback function. The flow is almost same as L3 CAT.
Signed-off-by: Yi Sun
---
v10:
- fix comment.
(suggested by Jan Beulich)
- use swith in 'cat_init_feature' to handle different feature types.
(suggested by Jan Beulich)
- changes about 'props'.
(suggested by Jan Beulich)
- restore MSRs to default value when cpu online.
(suggested by Jan Beulich)
- remove feat_mask.
(suggested by Jan Beulich)
v9:
- modify commit message to describe flow clearer.
- handle cpu offline and online again case to read MSRs registers values
back and save them into cos array to make user can get real data.
- modify error handling process in 'psr_cpu_prepare' to reduce redundant
codes.
- modify 'get_cdp_data' and 'get_cdp_code' to make them standard.
(suggested by Roger Pau and Jan Beulich)
- encapsulate CDP operations into 'cat_init_feature' to reduce redundant
codes.
(suggested by Roger Pau)
- reuse 'cat_get_cos_max' for CDP.
(suggested by Roger Pau)
- handle 'PSR_CDP' in psr_presmp_init to make init work can be done when
there is only 'psr=cdp' in cmdline.
- remove unnecessary comment.
(suggested by Jan Beulich)
- move CDP related codes in 'cpu_init_work' into 'psr_cpu_init'.
(suggested by Jan Beulich)
- add codes to handle CDP's 'cos_num'.
(suggested by Jan Beulich)
- fix coding style issue.
(suggested by Jan Beulich)
- do not free resources when allocation fails in 'psr_cpu_prepare'.
(suggested by Jan Beulich)
- changes about 'uint64_t' to 'uint32_t'.
(suggested by Jan Beulich)
v7:
- initialize 'l3_cdp'.
(suggested by Konrad Rzeszutek Wilk)
v6:
- use 'cpuid_leaf'.
(suggested by Konrad Rzeszutek Wilk and Jan Beulich)
v5:
- remove codes to free 'feat_l3_cdp' in 'free_feature'.
(suggested by Jan Beulich)
- encapsulate cpuid registers into 'struct cpuid_leaf_regs'.
(suggested by Jan Beulich)
- print socket info when 'opt_cpu_info' is true.
(suggested by Jan Beulich)
- rename 'l3_cdp_get_max_cos_max' to 'l3_cdp_get_cos_max'.
(suggested by Jan Beulich)
- rename 'dat[]' to 'data[]'.
(suggested by Jan Beulich)
- move 'cpu_prepare_work' contents into 'psr_cpu_prepare'.
(suggested by Jan Beulich)
v4:
- create this patch to make codes easier to understand.
(suggested by Jan Beulich)
---
xen/arch/x86/psr.c | 84 --
1 file changed, 76 insertions(+), 8 deletions(-)
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index 0f57676..58970fa 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -144,11 +144,28 @@ static DEFINE_PER_CPU(struct psr_assoc, psr_assoc);
* array creation. It is used to transiently store a spare node.
*/
static struct feat_node *feat_l3_cat;
+static struct feat_node *feat_l3_cdp;
/* Common functions */
#define cat_default_val(len) (0x >> (32 - (len)))
/*
+ * get_cdp_data - get DATA COS register value from input COS ID.
+ * @feat:the feature node.
+ * @cos: the COS ID.
+ */
+#define get_cdp_data(feat, cos) \
+( (feat)->cos_reg_val[(cos) * 2] )
+
+/*
+ * get_cdp_code - get CODE COS register value from input COS ID.
+ * @feat:the feature node.
+ * @cos: the COS ID.
+ */
+#define get_cdp_code(feat, cos) \
+( (feat)->cos_reg_val[(cos) * 2 + 1] )
+
+/*
* Use this function to check if any allocation feature has been enabled
* in cmdline.
*/
@@ -283,6 +300,37 @@ static void cat_init_feature(const struct cpuid_leaf *regs,
break;
+case PSR_SOCKET_L3_CDP:
+{
+unsigned long val;
+
+/* Cut half of cos_max when CDP is enabled. */
+feat->props->cos_max >>= 1;
+
+/* We only write mask1 since mask0 is always all ones by default. */
+wrmsrl(MSR_IA32_PSR_L3_MASK(1), cat_default_val(feat->props->cbm_len));
+rdmsrl(MSR_IA32_PSR_L3_QOS_CFG, val);
+wrmsrl(MSR_IA32_PSR_L3_QOS_CFG, val | (1 <<
PSR_L3_QOS_CDP_ENABLE_BIT));
+
+/* cos=0 is reserved as default cbm(all bits within cbm_len are 1). */
+get_cdp_code(feat, 0) = cat_default_val(feat->props->cbm_len);
+get_cdp_data(feat, 0) = cat_default_val(feat->props->cbm_len);
+
+/*
+ * To handle cpu offline and then online case, we need restore MSRs to
+ * default values.
+ */
+for ( i = 1; i <= feat->props->cos_max; i++ )
+{
+wrmsrl(MSR_IA32_PSR_L3_MASK_DATA(i), get_cdp_data(feat, 0));
+wrmsrl(MSR_IA32_PSR_L3_MASK_CODE(i), get_cdp_code(feat, 0));
+get_cdp_code(feat, i) = get_cdp_code(feat, 0);
+get_cdp_data(feat, i) = get_cdp_data(feat, 0);
+}
+
+break;
+}
+
[Xen-devel] [PATCH v10 08/25] x86: refactor psr: L3 CAT: implement get value flow.
There is an interface in user space to show feature value of
domains.
This patch implements get value flow in hypervisor including
L3 CAT callback function.
It also changes domctl interface to make it more general.
With this patch, 'psr-cat-show' can work for L3 CAT but not for
L3 code/data which is implemented in patch "x86: refactor psr:
implement get value flow for CDP.".
Signed-off-by: Yi Sun
---
v10:
- use an intermediate variable to get value and avoid cast in domctl.
(suggested by Jan Beulich)
- remove 'type' in 'get_val' parameters and will add it back when
implementing CDP.
(suggested by Jan Beulich)
- remove unnecessary variable and return error about 'info' in
'psr_get_feat'.
(suggested by Jan Beulich)
- use 'ASSERT' to check input parameter in 'psr_get_val'.
(suggested by Jan Beulich)
- changes about 'feat_props'.
(suggested by Jan Beulich)
v9:
- add commit message to explain there is an user space interface.
- rename 'l3_cat_get_val' to 'cat_get_val' to cover all L3/L2 CAT features.
(suggested by Roger Pau)
- replace feature list handling to feature array handling.
(suggested by Roger Pau)
- change parameter of 'psr_get'. Use 'psr_cos_ids' directly to replace
domain. Also declare it to 'const'.
(suggested by Jan Beulich)
- change code flow to remove 'psr_get' but add 'psr_get_feat' to make codes
more reasonable.
(suggested by Jan Beulich)
- modify patch title to indicate 'L3 CAT'.
(suggested by Jan Beulich)
- move cos check into common function because this check is required by all
features.
(suggested by Jan Beulich)
- fix coding style issue.
(suggested by Jan Beulich)
- changes about 'uint64_t' to 'uint32_t'.
(suggested by Jan Beulich)
v7:
- rename '__psr_get' to 'psr_get'.
(suggested by Wei Liu)
v6:
- modify commit message to make it clearer.
(suggested by Konrad Rzeszutek Wilk)
- remove one extra space in code.
(suggested by Konrad Rzeszutek Wilk)
- remove unnecessary comment.
(suggested by Konrad Rzeszutek Wilk)
- write a helper function to move get info and get val functions into
it. Because most codes of 'get_info' and 'get_val' are same.
(suggested by Konrad Rzeszutek Wilk)
v5:
- rename 'dat[]' to 'data[]'
(suggested by Jan Beulich)
- modify variables names to make them better, e.g. 'feat_tmp' to 'feat'.
(suggested by Jan Beulich)
- check if feature type match in caller of feature callback function.
(suggested by Jan Beulich)
v4:
- create this patch to make codes easier to understand.
(suggested by Jan Beulich)
---
xen/arch/x86/domctl.c | 30 ++---
xen/arch/x86/psr.c| 67 ---
xen/include/asm-x86/psr.h | 4 +--
3 files changed, 80 insertions(+), 21 deletions(-)
diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c
index 02b48e8..dc213a7 100644
--- a/xen/arch/x86/domctl.c
+++ b/xen/arch/x86/domctl.c
@@ -1455,25 +1455,37 @@ long arch_do_domctl(
break;
case XEN_DOMCTL_PSR_CAT_OP_GET_L3_CBM:
-ret = psr_get_l3_cbm(d, domctl->u.psr_cat_op.target,
- &domctl->u.psr_cat_op.data,
- PSR_CBM_TYPE_L3);
+{
+uint32_t val;
+
+ret = psr_get_val(d, domctl->u.psr_cat_op.target,
+ &val, PSR_CBM_TYPE_L3);
+domctl->u.psr_cat_op.data = val;
copyback = 1;
break;
+}
case XEN_DOMCTL_PSR_CAT_OP_GET_L3_CODE:
-ret = psr_get_l3_cbm(d, domctl->u.psr_cat_op.target,
- &domctl->u.psr_cat_op.data,
- PSR_CBM_TYPE_L3_CODE);
+{
+uint32_t val;
+
+ret = psr_get_val(d, domctl->u.psr_cat_op.target,
+ &val, PSR_CBM_TYPE_L3_CODE);
+domctl->u.psr_cat_op.data = val;
copyback = 1;
break;
+}
case XEN_DOMCTL_PSR_CAT_OP_GET_L3_DATA:
-ret = psr_get_l3_cbm(d, domctl->u.psr_cat_op.target,
- &domctl->u.psr_cat_op.data,
- PSR_CBM_TYPE_L3_DATA);
+{
+uint32_t val;
+
+ret = psr_get_val(d, domctl->u.psr_cat_op.target,
+ &val, PSR_CBM_TYPE_L3_DATA);
+domctl->u.psr_cat_op.data = val;
copyback = 1;
break;
+}
default:
ret = -EOPNOTSUPP;
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index 36ade48..25fcd21 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -97,6 +97,10 @@ struct feat_node {
/* get_feat_info is used to get feature HW info. */
bool (*get_feat_info)(const st
[Xen-devel] [PATCH v10 15/25] x86: refactor psr: CDP: implement get hw info flow.
This patch implements get HW info flow for CDP including L3 CDP callback
function. The flow is almost same as L3 CAT.
With this patch, 'psr-hwinfo' can work for L3 CDP.
Signed-off-by: Yi Sun
---
v10:
- update renamed macros used by psr_get_info.
(suggested by Jan Beulich)
- change 'psr_get_info' flow to cover CDP case to make codes in sysctl
more simple.
(suggested by Jan Beulich)
- remove sysctl redundant codes after applying above changes.
(suggested by Jan Beulich)
v9:
- modify commit message to explain flow more clearly.
- reuse 'cat_get_feat_info' for CDP to reduce redundant codes.
(suggested by Roger Pau)
- fix coding style issues.
(suggested by Wei Liu and Roger Pau)
- rename macros used by psr_get_info to make them meaningful.
(suggested by Jan Beulich)
v5:
- rename 'dat[]' to 'data[]'.
(suggested by Jan Beulich)
- remove type check in callback function.
(suggested by Jan Beulich)
v4:
- create this patch to make codes easier to understand.
(suggested by Jan Beulich)
---
xen/arch/x86/psr.c | 24
1 file changed, 24 insertions(+)
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index 58970fa..f0611ad 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -237,6 +237,10 @@ static enum psr_feat_type psr_cbm_type_to_feat_type(enum
cbm_type type)
case PSR_CBM_TYPE_L3:
feat_type = PSR_SOCKET_L3_CAT;
break;
+case PSR_CBM_TYPE_L3_DATA:
+case PSR_CBM_TYPE_L3_CODE:
+feat_type = PSR_SOCKET_L3_CDP;
+break;
default:
ASSERT_UNREACHABLE();
}
@@ -386,8 +390,20 @@ static struct feat_props l3_cat_props = {
};
/* L3 CDP ops */
+static bool l3_cdp_get_feat_info(const struct feat_node *feat,
+ uint32_t data[], uint32_t array_len)
+{
+if ( !cat_get_feat_info(feat, data, array_len) )
+return false;
+
+data[PSR_INFO_IDX_CAT_FLAG] |= XEN_SYSCTL_PSR_CAT_L3_CDP;
+
+return true;
+}
+
static struct feat_props l3_cdp_props = {
.cos_num = 2,
+.get_feat_info = l3_cdp_get_feat_info,
};
static void __init parse_psr_bool(char *s, char *value, char *feature,
@@ -641,6 +657,14 @@ int psr_get_info(unsigned int socket, enum cbm_type type,
if ( IS_ERR(feat) )
return PTR_ERR(feat);
+/* If type is L3 CAT but we cannot find it in feature array, try CDP. */
+if ( !feat && type == PSR_CBM_TYPE_L3 )
+{
+feat = psr_get_feat(socket, PSR_CBM_TYPE_L3_CODE);
+if ( IS_ERR(feat) )
+return PTR_ERR(feat);
+}
+
if ( !feat )
return -ENOENT;
--
1.9.1
___
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[Xen-devel] [xen-4.6-testing test] 107042: regressions - trouble: broken/fail/pass
flight 107042 xen-4.6-testing real [real] http://logs.test-lab.xenproject.org/osstest/logs/107042/ Regressions :-( Tests which did not succeed and are blocking, including tests which could not be run: test-amd64-i386-rumprun-i386 12 guest-destroyfail REGR. vs. 106819 test-xtf-amd64-amd64-3 10 xtf-fep fail REGR. vs. 106819 test-xtf-amd64-amd64-3 11 xtf-run fail REGR. vs. 106819 test-xtf-amd64-amd64-5 11 xtf-run fail REGR. vs. 106819 test-xtf-amd64-amd64-1 10 xtf-fep fail REGR. vs. 106819 test-xtf-amd64-amd64-2 11 xtf-run fail REGR. vs. 106819 test-amd64-amd64-rumprun-amd64 12 guest-destroy fail REGR. vs. 106819 test-xtf-amd64-amd64-1 11 xtf-run fail REGR. vs. 106819 test-xtf-amd64-amd64-4 10 xtf-fep fail REGR. vs. 106819 test-amd64-amd64-xl-xsm 14 guest-saverestorefail REGR. vs. 106819 test-amd64-amd64-libvirt 14 guest-saverestorefail REGR. vs. 106819 test-amd64-i386-libvirt-xsm 14 guest-saverestorefail REGR. vs. 106819 test-amd64-amd64-migrupgrade 24 leak-check/check/dst_host fail REGR. vs. 106819 test-xtf-amd64-amd64-4 11 xtf-run fail REGR. vs. 106819 test-amd64-i386-qemuu-rhel6hvm-intel 9 redhat-install fail REGR. vs. 106819 test-amd64-i386-xl 14 guest-saverestorefail REGR. vs. 106819 test-amd64-i386-xl-xsm 14 guest-saverestorefail REGR. vs. 106819 test-amd64-amd64-xl 14 guest-saverestorefail REGR. vs. 106819 test-amd64-i386-xl-qemuu-ovmf-amd64 9 debian-hvm-install fail REGR. vs. 106819 test-amd64-i386-freebsd10-i386 13 guest-saverestore fail REGR. vs. 106819 test-amd64-i386-qemuu-rhel6hvm-amd 9 redhat-install fail REGR. vs. 106819 test-amd64-amd64-xl-multivcpu 14 guest-saverestore fail REGR. vs. 106819 test-amd64-i386-freebsd10-amd64 13 guest-saverestore fail REGR. vs. 106819 test-amd64-amd64-xl-qemut-debianhvm-amd64 9 debian-hvm-install fail REGR. vs. 106819 test-amd64-amd64-qemuu-nested-intel 9 debian-hvm-install fail REGR. vs. 106819 test-amd64-i386-libvirt 14 guest-saverestorefail REGR. vs. 106819 test-amd64-amd64-libvirt-pair 21 guest-migrate/src_host/dst_host fail REGR. vs. 106819 test-amd64-amd64-libvirt-qemuu-debianhvm-amd64-xsm 9 debian-hvm-install fail REGR. vs. 106819 test-amd64-amd64-xl-qemut-stubdom-debianhvm-amd64-xsm 9 debian-hvm-install fail REGR. vs. 106819 test-amd64-amd64-xl-credit2 14 guest-saverestorefail REGR. vs. 106819 test-amd64-i386-migrupgrade 24 leak-check/check/dst_host fail REGR. vs. 106819 test-amd64-i386-qemut-rhel6hvm-intel 9 redhat-install fail REGR. vs. 106819 test-amd64-amd64-pygrub 9 debian-di-installfail REGR. vs. 106819 test-amd64-amd64-amd64-pvgrub 9 debian-di-install fail REGR. vs. 106819 test-amd64-amd64-pair 21 guest-migrate/src_host/dst_host fail REGR. vs. 106819 test-amd64-i386-qemut-rhel6hvm-amd 9 redhat-install fail REGR. vs. 106819 test-amd64-amd64-xl-qcow2 9 debian-di-installfail REGR. vs. 106819 test-amd64-i386-xl-qemut-debianhvm-amd64-xsm 9 debian-hvm-install fail REGR. vs. 106819 test-amd64-amd64-xl-qemuu-debianhvm-amd64 9 debian-hvm-install fail REGR. vs. 106819 test-amd64-amd64-xl-qemuu-debianhvm-amd64-xsm 9 debian-hvm-install fail REGR. vs. 106819 test-amd64-i386-pair 21 guest-migrate/src_host/dst_host fail REGR. vs. 106819 test-amd64-amd64-libvirt-xsm 14 guest-saverestorefail REGR. vs. 106819 test-amd64-i386-xl-qemut-debianhvm-amd64 9 debian-hvm-install fail REGR. vs. 106819 test-amd64-i386-libvirt-pair 21 guest-migrate/src_host/dst_host fail REGR. vs. 106819 test-amd64-amd64-i386-pvgrub 9 debian-di-installfail REGR. vs. 106819 test-amd64-i386-xl-qemuu-debianhvm-amd64 9 debian-hvm-install fail REGR. vs. 106819 test-amd64-amd64-xl-qemut-debianhvm-amd64-xsm 9 debian-hvm-install fail REGR. vs. 106819 test-amd64-i386-libvirt-qemuu-debianhvm-amd64-xsm 9 debian-hvm-install fail REGR. vs. 106819 test-amd64-i386-xl-qemut-stubdom-debianhvm-amd64-xsm 9 debian-hvm-install fail REGR. vs. 106819 test-amd64-amd64-xl-qemuu-ovmf-amd64 9 debian-hvm-install fail REGR. vs. 106819 test-amd64-i386-xl-qemuu-debianhvm-amd64-xsm 9 debian-hvm-install fail REGR. vs. 106819 test-amd64-amd64-libvirt-vhd 9 debian-di-installfail REGR. vs. 106819 test-armhf-armhf-libvirt-xsm 14 guest-stop fail REGR. vs. 106819 test-amd64-i386-xl-raw9 debian-di-installfail REGR. vs. 106819 test-armhf-armhf-xl-arndale 15 guest-start/debian.repeat fail REGR. vs. 106819 test-armhf-armhf-libvirt 14 guest-stop fail REGR. vs. 106819 test-armhf-armhf-xl-xsm 15 guest-start/debian.repeat fail REGR. vs. 106819 test-armhf-armhf-xl-cubietruck 15 guest-start/debian.repeat fail REGR. vs. 1068
[Xen-devel] [linux-linus test] 107053: regressions - FAIL
flight 107053 linux-linus real [real] http://logs.test-lab.xenproject.org/osstest/logs/107053/ Regressions :-( Tests which did not succeed and are blocking, including tests which could not be run: test-armhf-armhf-xl-arndale 11 guest-start fail REGR. vs. 59254 test-armhf-armhf-xl-credit2 11 guest-start fail REGR. vs. 59254 test-armhf-armhf-libvirt-xsm 11 guest-start fail REGR. vs. 59254 test-armhf-armhf-xl-cubietruck 11 guest-start fail REGR. vs. 59254 test-armhf-armhf-libvirt 11 guest-start fail REGR. vs. 59254 test-armhf-armhf-xl 11 guest-start fail REGR. vs. 59254 test-armhf-armhf-xl-xsm 11 guest-start fail REGR. vs. 59254 test-armhf-armhf-xl-multivcpu 11 guest-start fail REGR. vs. 59254 Regressions which are regarded as allowable (not blocking): test-armhf-armhf-xl-rtds 11 guest-start fail REGR. vs. 59254 test-amd64-amd64-xl-rtds 9 debian-installfail REGR. vs. 59254 test-armhf-armhf-xl-vhd 9 debian-di-install fail baseline untested test-armhf-armhf-libvirt-raw 9 debian-di-install fail baseline untested test-amd64-i386-xl-qemuu-win7-amd64 16 guest-stop fail like 59254 test-amd64-amd64-xl-qemut-win7-amd64 16 guest-stop fail like 59254 test-amd64-amd64-xl-qemuu-win7-amd64 16 guest-stop fail like 59254 test-amd64-i386-xl-qemut-win7-amd64 16 guest-stop fail like 59254 Tests which did not succeed, but are not blocking: test-arm64-arm64-libvirt-xsm 1 build-check(1) blocked n/a test-arm64-arm64-xl 1 build-check(1) blocked n/a build-arm64-libvirt 1 build-check(1) blocked n/a test-arm64-arm64-libvirt-qcow2 1 build-check(1) blocked n/a test-arm64-arm64-libvirt 1 build-check(1) blocked n/a test-arm64-arm64-xl-credit2 1 build-check(1) blocked n/a test-arm64-arm64-xl-rtds 1 build-check(1) blocked n/a test-arm64-arm64-xl-multivcpu 1 build-check(1) blocked n/a test-arm64-arm64-xl-xsm 1 build-check(1) blocked n/a test-amd64-i386-libvirt-xsm 12 migrate-support-checkfail never pass test-amd64-amd64-libvirt-xsm 12 migrate-support-checkfail never pass build-arm64-xsm 5 xen-buildfail never pass test-amd64-amd64-libvirt 12 migrate-support-checkfail never pass test-amd64-amd64-libvirt-qemuu-debianhvm-amd64-xsm 10 migrate-support-check fail never pass test-amd64-i386-libvirt-qemuu-debianhvm-amd64-xsm 10 migrate-support-check fail never pass test-amd64-amd64-libvirt-vhd 11 migrate-support-checkfail never pass test-amd64-amd64-qemuu-nested-amd 16 debian-hvm-install/l1/l2 fail never pass test-amd64-i386-libvirt 12 migrate-support-checkfail never pass build-arm64 5 xen-buildfail never pass version targeted for testing: linuxf9799ad21b5e4a41633f54dfab407ebb37abbd8a baseline version: linux45820c294fe1b1a9df495d57f40585ef2d069a39 Last test of basis59254 2015-07-09 04:20:48 Z 632 days Failing since 59348 2015-07-10 04:24:05 Z 631 days 368 attempts Testing same since 107053 2017-04-01 03:47:46 Z0 days1 attempts 8119 people touched revisions under test, not listing them all jobs: build-amd64-xsm pass build-arm64-xsm fail build-armhf-xsm pass build-i386-xsm pass build-amd64 pass build-arm64 fail build-armhf pass build-i386 pass build-amd64-libvirt pass build-arm64-libvirt blocked build-armhf-libvirt pass build-i386-libvirt pass build-amd64-pvopspass build-arm64-pvopspass build-armhf-pvopspass build-i386-pvops pass build-amd64-rumprun pass build-i386-rumprun pass test-amd64-amd64-xl pass test-arm64-arm64-xl
Re: [Xen-devel] [RFC QEMU PATCH v2 01/10] nvdimm xen: disable label support on Xen
On Mon, Mar 20, 2017 at 08:12:40AM +0800, Haozhong Zhang wrote:
> If xen_enabled(), memory_region_get_ram_ptr() always returns NULL and
> nvdimm_realize() cannot get the correct pointer to the label area. This
> commit disables the label support for Xen accelerator to workaround
> this issue.
>
> Signed-off-by: Haozhong Zhang
> ---
> Cc: "Michael S. Tsirkin"
> Cc: Igor Mammedov
> Cc: Xiao Guangrong
> ---
> hw/mem/nvdimm.c | 6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/hw/mem/nvdimm.c b/hw/mem/nvdimm.c
> index db896b0bb6..0d3e17e94c 100644
> --- a/hw/mem/nvdimm.c
> +++ b/hw/mem/nvdimm.c
> @@ -87,7 +87,11 @@ static void nvdimm_realize(PCDIMMDevice *dimm, Error
> **errp)
> align = memory_region_get_alignment(mr);
>
> pmem_size = size - nvdimm->label_size;
> -nvdimm->label_data = memory_region_get_ram_ptr(mr) + pmem_size;
> +/*
> + * TODO: explain the reason
Ahem?
> + */
> +if (nvdimm->label_size)
> +nvdimm->label_data = memory_region_get_ram_ptr(mr) + pmem_size;
> pmem_size = QEMU_ALIGN_DOWN(pmem_size, align);
>
> if (size <= nvdimm->label_size || !pmem_size) {
> --
> 2.12.0
>
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Re: [Xen-devel] [RFC XEN PATCH v2 00/15] Add vNVDIMM support to HVM domains
On Mon, Mar 20, 2017 at 08:09:34AM +0800, Haozhong Zhang wrote:
> This is v2 RFC patch series to add vNVDIMM support to HVM domains.
> v1 can be found at
> https://lists.xenproject.org/archives/html/xen-devel/2016-10/msg00424.html.
>
> No label and no _DSM except function 0 "query implemented functions"
> is supported by this version, but they will be added by future patches.
>
> The corresponding Qemu patch series is sent in another thread
> "[RFC QEMU PATCH v2 00/10] Implement vNVDIMM for Xen HVM guest".
>
> All patch series can be found at
> Xen: https://github.com/hzzhan9/xen.git nvdimm-rfc-v2
> Qemu: https://github.com/hzzhan9/qemu.git xen-nvdimm-rfc-v2
>
Hey!
Thank you for posting this. A quick question.
> Changes in v2
> ==
>
> - One of the primary changes in v2 is dropping the linux kernel
> patches, which were used to reserve on host pmem for placing its
> frametable and M2P table. In v2, we add a management tool xen-ndctl
> which is used in Dom0 to notify Xen hypervisor of which storage can
> be used to manage the host pmem.
>
> For example,
> 1. xen-ndctl setup 0x24 0x38 0x38 0x3c
> tells Xen hypervisor to use host pmem pages at MFN 0x38 ~
> 0x3c to manage host pmem pages at MFN 0x24 ~ 0x38.
> I.e. the former is used to place the frame table and M2P table of
> both ranges of pmem pages.
>
> 2. xen-ndctl setup 0x24 0x38
> tells Xen hypervisor to use the regular RAM to manage the host
> pmem pages at MFN 0x24 ~ 0x38. I.e the regular RMA is used
> to place the frame table and M2P table.
How were you thinking to 'glue' this to the libvirt (xl) way of setting
up NVDIMM? Could you explain (even in broad ways) how that would be
done? I see the 'vnvdimms' but somehow would have thought the
libxl would parse the /proc/iomem (or perhaps call ndctl to
obtain this ?)
>
> - Another primary change in v2 is dropping the support to map files on
> the host pmem to HVM domains as virtual NVDIMMs, as I cannot find a
> stable to fix the fiemap of host files. Instead, we can rely on the
> ability added in Linux kernel v4.9 that enables creating multiple
> pmem namespaces on a single nvdimm interleave set.
Could you expand on this a bit please? This is a quite important feature
and I thought the mix of mlock + fiemap would have solved this?
>
> - Other changes are logged in each patch separately.
>
> How to Test
Thank you for the detailed way this is explained!
> ==
>
> 0. This patch series can be tested either on the real hardware with
>NVDIMM, or in the nested virtualization environment on KVM. The
Real hardware, eh? Nice!
>latter requires QEMU 2.9 or newer with, for example, following
>commands and options,
> # dd if=/dev/zero of=nvm-8G.img bs=1G count=8
> # rmmod kvm-intel; modprobe kvm-intel nested=1
> # qemu-system-x86_64 -enable-kvm -smp 4 -cpu host,+vmx \
> -hda DISK_IMG_OF_XEN \
> -machine pc,nvdimm \
> -m 8G,slots=4,maxmem=128G \
> -object
> memory-backend-file,id=mem1,mem-path=nvm-8G,size=8G \
> -device nvdimm,id=nv1,memdev=mem1,label-size=2M \
> ...
>Above will create a nested virtualization environment with a 8G
>pmem mode NVDIMM device (whose last 2MB is used as the label
>storage area).
>
> 1. Check out Xen and QEMU from above repositories and branches. Build
>and install Xen with qemu-xen replaced by above QEMU.
>
> 2. Build and install Linux kernel 4.9 or later as Dom0 kernel with the
>following configs selected:
>CONFIG_ACPI_NFIT
>CONFIG_LIBNVDIMM
>CONFIG_BLK_DEV_PMEM
>CONFIG_NVDIMM_PFN
>CONFIG_FS_DAX
>
> 3. Check out ndctl from https://github.com/pmem/ndctl.git. Build and
>install ndctl in Dom0.
>
> 4. Boot to Xen Dom0.
>
> 5. Create pmem namespaces on the host pmem region.
> # ndctl disable-region region0
> # ndctl zero-labels nmem0// clear existing labels
> # ndctl init-labels nmem0// initialize the label
> area
> # ndctl enable-region region0
> # ndctl create-namespace -r region0 -s 4G -m raw // create one 4G pmem
> namespace
> # ndctl create-namespace -r region0 -s 1G -m raw // create one 1G pmem
> namespace
> # ndctl list --namespaces
> [
>{
>"dev":"namespace0.0",
>"mode":"raw",
>"size":4294967296,
>"uuid":"bbfbedbd-3ada-4f55-9484-01f2722c651b",
>"blockdev":"pmem0"
>},
>{
>"dev":"namespace0.1",
>"mode":"raw",
>"size":1073741824,
>"uuid":"dd4d3949-6887-417b-b819-89a7854fcdbd",
>"blockdev":"pmem0.1"
>}
> ]
>
> 6. Ask Xen hypervisor to use namespace0
Re: [Xen-devel] [RFC XEN PATCH v2 15/15] tools/misc: add xen-ndctl
On Thu, Mar 30, 2017 at 03:58:25PM +0800, Haozhong Zhang wrote: > On 03/29/17 21:11 -0700, Dan Williams wrote: > > On Sun, Mar 19, 2017 at 5:09 PM, Haozhong Zhang > > wrote: > > > xen-ndctl is a tool for users in Dom0 to setup the host pmem with Xen > > > hypervisor. It's used to specify the storage, which is either the > > > regular RAM or a pmem range, to manage the specified pmem. > > > > > > Signed-off-by: Haozhong Zhang > > > --- > > > Cc: Ian Jackson > > > Cc: Wei Liu > > > --- > > > > I would be open to moving this tooling into upstream ndctl [1]. > > Especially since you're reusing the same name it would be confusing to > > have 2 ndctl tools. > > > > [1]: https://github.com/pmem/ndctl > > Then it could leverage existing code in ndctl (e.g. getting parameters > from a device name rather than using address in my current implementation). > > I'm not sure about Xen's policy whether a tool should be included in > Xen or can be left in 3rd party program. Let's wait for Xen maintainers' > reply. No problems. For example QEMU has it (it has an configure to detect the headers and then uses xc_XYZ calls). Also kexec-tools does it as well. The big thing that you have to keep in mind is to make the hypercall as future proof as possible - so you don't have #ifdef all over the code. > > Thanks, > Haozhong ___ Xen-devel mailing list Xen-devel@lists.xen.org https://lists.xen.org/xen-devel
Re: [Xen-devel] [RFC XEN PATCH v2 00/15] Add vNVDIMM support to HVM domains
..snip.. > >> Is there a resource I can read more about why the hypervisor needs to > >> have this M2P mapping for nvdimm support? > > > > M2P is basically an array of frame numbers. It's indexed by the host > > page frame number, or the machine frame number (MFN) in Xen's > > definition. The n'th entry records the guest page frame number that is > > mapped to MFN n. M2P is one of the core data structures used in Xen > > memory management, and is used to convert MFN to guest PFN. A > > read-only version of M2P is also exposed as part of ABI to guest. In > > the previous design discussion, we decided to put the management of > > NVDIMM in the existing Xen memory management as much as possible, so > > we need to build M2P for NVDIMM as well. > > > > Thanks, but what I don't understand is why this M2P lookup is needed? Xen uses it to construct the EPT page tables for the guests. > Does Xen establish this metadata for PCI mmio ranges as well? What Xen It doesn't have that (M2P) for PCI MMIO ranges. For those it has an ranges construct (since those are usually contingous and given in ranges to a guest). > memory management operations does this enable? Sorry if these are > basic Xen questions, I'm just looking to see if we can make the > mapping support more dynamic. For example, what if we wanted to change > the MFN to guest PFN relationship after every fault? As in swap it out? (Like a hard drive swaps out faulty sectors?). That is certainly done. We also have tools (xen-hptool) that can mark certain pages as broken/etc and inject the MCEs in the guest to reflect that. But all of that is driven by hypercalls ___ Xen-devel mailing list Xen-devel@lists.xen.org https://lists.xen.org/xen-devel
[Xen-devel] ARM:Booting xen on pine64 board
Hello I am trying to boot xen(debug build) on pine64 ARM64 based board but its hangs at following position, - UART enabled - - CPU booting - - Current EL 0008 - - Xen starting at EL2 - - Zero BSS - - Setting up control registers - - Turning on paging - - Ready - (XEN) Checking for initrd in /chosen (XEN) RAM: 4100 - 7fff (XEN) (XEN) MODULE[0]: 7e20 - 7e202000 Device Tree (XEN) MODULE[1]: 7e40 - 7ef46a00 Kernel console=hvc0 ro root=/dev/mmcblk0p2 clk_ignore_unused rootwait (XEN) RESVD[0]: 7e20 - 7e202000 (XEN) (XEN) Command line: dtuart=serial0 earlyprint loglvl=all conswitch=x dom0_mem=128M (XEN) Placing Xen at 0x7fc0-0x7fe0 (XEN) Update BOOTMOD_XEN from 7fe0-7fefad81 => 7fc0-7fcfad81 (XEN) Booting using Device Tree (XEN) Domain heap initialised (XEN) Platform: Generic System (XEN) Looking for dtuart at "serial0", options "" Xen 4.9-unstable (XEN) Xen version 4.9-unstable (bgohil@) (aarch64-linux-gnu-gcc (Linaro GCC 6.2-2016.11) 6.2.1 20161016) debug=n Tue Mar 28 16:12:32 IST 2017 (XEN) Latest ChangeSet: Fri Mar 24 14:19:47 2017 +0100 git:5b08f85 (XEN) Processor: 410fd034: "ARM Limited", variant: 0x0, part 0xd03, rev 0x4 (XEN) 64-bit Execution: (XEN) Processor Features: (XEN) Exception Levels: EL3:64+32 EL2:64+32 EL1:64+32 EL0:64+32 (XEN) Extensions: FloatingPoint AdvancedSIMD (XEN) Debug Features: 10305106 (XEN) Auxiliary Features: (XEN) Memory Model Features: 1122 (XEN) ISA Features: 00011120 (XEN) 32-bit Execution: (XEN) Processor Features: 0131:00011011 (XEN) Instruction Sets: AArch32 A32 Thumb Thumb-2 Jazelle (XEN) Extensions: GenericTimer Security (XEN) Debug Features: 03010066 (XEN) Auxiliary Features: (XEN) Memory Model Features: 10201105 4000 0126 02102211 (XEN) ISA Features: 02101110 13112111 21232042 01112131 00011142 00011121 (XEN) Using PSCI-0.2 for SMP bringup (XEN) SMP: Allowing 4 CPUs (XEN) Generic Timer IRQ: phys=30 hyp=26 virt=27 Freq: 24000 KHz (XEN) GICv2 initialization: (XEN) gic_dist_addr=01c81000 (XEN) gic_cpu_addr=01c82000 (XEN) gic_hyp_addr=01c84000 (XEN) gic_vcpu_addr=01c86000 (XEN) gic_maintenance_irq=25 (XEN) GICv2: 224 lines, 4 cpus, secure (IID 0200143b). *(XEN) Using scheduler: SMP Credit Scheduler (credit)* but when I boot dtuart= say duart=xyz instead of dtuart=serial0, xen booted successfully but Dom0 crash while probing 'serial0' driver. If I remove 'serial0' node from device tree, Dom0 boot successfully but unable to enter input into 'hvc' console. what could be wrong here or missing something? -- Regards, Bharat Gohil Sr.Software Engineer bharat.go...@harman.com +919427054633 ___ Xen-devel mailing list Xen-devel@lists.xen.org https://lists.xen.org/xen-devel
[Xen-devel] [libvirt test] 107056: regressions - FAIL
flight 107056 libvirt real [real] http://logs.test-lab.xenproject.org/osstest/logs/107056/ Regressions :-( Tests which did not succeed and are blocking, including tests which could not be run: build-armhf-libvirt 5 libvirt-buildfail REGR. vs. 106829 Tests which did not succeed, but are not blocking: test-arm64-arm64-libvirt-xsm 1 build-check(1) blocked n/a test-armhf-armhf-libvirt 1 build-check(1) blocked n/a build-arm64-libvirt 1 build-check(1) blocked n/a test-arm64-arm64-libvirt-qcow2 1 build-check(1) blocked n/a test-armhf-armhf-libvirt-raw 1 build-check(1) blocked n/a test-arm64-arm64-libvirt 1 build-check(1) blocked n/a test-armhf-armhf-libvirt-xsm 1 build-check(1) blocked n/a build-arm64-pvops 5 kernel-build fail never pass test-amd64-amd64-libvirt-xsm 12 migrate-support-checkfail never pass test-amd64-i386-libvirt 12 migrate-support-checkfail never pass test-amd64-i386-libvirt-xsm 12 migrate-support-checkfail never pass test-amd64-amd64-libvirt 12 migrate-support-checkfail never pass build-arm64-xsm 5 xen-buildfail never pass build-arm64 5 xen-buildfail never pass test-amd64-i386-libvirt-qemuu-debianhvm-amd64-xsm 10 migrate-support-check fail never pass test-amd64-amd64-libvirt-qemuu-debianhvm-amd64-xsm 10 migrate-support-check fail never pass test-amd64-amd64-libvirt-vhd 11 migrate-support-checkfail never pass version targeted for testing: libvirt e7e06b7d55d768867692e482588133b9f72a3ae9 baseline version: libvirt 9b14b2bc3ba95457589fe08f139542476314ff19 Last test of basis 106829 2017-03-22 04:22:56 Z 10 days Failing since106855 2017-03-23 04:22:59 Z9 days9 attempts Testing same since 107056 2017-04-01 04:20:16 Z0 days1 attempts People who touched revisions under test: Andrea Bolognani Cédric Bosdonnat Dawid Zamirski Eric Blake Erik Skultety Jiri Denemark John Ferlan Ján Tomko Laine Stump Martin Kletzander Michal Privoznik Peter Krempa Roman Bogorodskiy jobs: build-amd64-xsm pass build-arm64-xsm fail build-armhf-xsm pass build-i386-xsm pass build-amd64 pass build-arm64 fail build-armhf pass build-i386 pass build-amd64-libvirt pass build-arm64-libvirt blocked build-armhf-libvirt fail build-i386-libvirt pass build-amd64-pvopspass build-arm64-pvopsfail build-armhf-pvopspass build-i386-pvops pass test-amd64-amd64-libvirt-qemuu-debianhvm-amd64-xsm pass test-amd64-i386-libvirt-qemuu-debianhvm-amd64-xsmpass test-amd64-amd64-libvirt-xsm pass test-arm64-arm64-libvirt-xsm blocked test-armhf-armhf-libvirt-xsm blocked test-amd64-i386-libvirt-xsm pass test-amd64-amd64-libvirt pass test-arm64-arm64-libvirt blocked test-armhf-armhf-libvirt blocked test-amd64-i386-libvirt pass test-amd64-amd64-libvirt-pairpass test-amd64-i386-libvirt-pair pass test-arm64-arm64-libvirt-qcow2 blocked test-armhf-armhf-libvirt-raw blocked test-amd64-amd64-libvirt-vhd pass sg-report-flight on osstest.test-lab.xenproject.org logs: /home/logs/logs images: /home/logs/images Logs, config files, etc. are available at http://logs.test-lab.xenproject.org/osstest/logs Explanation of these reports, and of osstest in general, is at http://xenbits.xen.org/gitweb/?p=osstest.git;a=blob;f=README.ema
[Xen-devel] [distros-debian-stretch test] 71137: tolerable trouble: blocked/broken/fail/pass
flight 71137 distros-debian-stretch real [real] http://osstest.xs.citrite.net/~osstest/testlogs/logs/71137/ Failures :-/ but no regressions. Regressions which are regarded as allowable (not blocking): test-armhf-armhf-armhf-stretch-netboot-pygrub 9 debian-di-install fail blocked in 68671 test-amd64-amd64-amd64-stretch-netboot-pvgrub 9 debian-di-install fail like 68671 test-amd64-amd64-i386-stretch-netboot-pygrub 9 debian-di-install fail like 68671 test-amd64-i386-amd64-stretch-netboot-pygrub 9 debian-di-install fail like 68671 test-amd64-i386-i386-stretch-netboot-pvgrub 9 debian-di-install fail like 68671 Tests which did not succeed, but are not blocking: test-arm64-arm64-armhf-stretch-netboot-pygrub 1 build-check(1)blocked n/a build-arm64-pvops 2 hosts-allocate broken never pass build-arm64 2 hosts-allocate broken never pass build-arm64-pvops 3 capture-logs broken never pass build-arm64 3 capture-logs broken never pass baseline version: flight 68671 jobs: build-amd64 pass build-arm64 broken build-armhf pass build-i386 pass build-amd64-pvopspass build-arm64-pvopsbroken build-armhf-pvopspass build-i386-pvops pass test-amd64-amd64-amd64-stretch-netboot-pvgrubfail test-amd64-i386-i386-stretch-netboot-pvgrub fail test-amd64-i386-amd64-stretch-netboot-pygrub fail test-arm64-arm64-armhf-stretch-netboot-pygrubblocked test-armhf-armhf-armhf-stretch-netboot-pygrubfail test-amd64-amd64-i386-stretch-netboot-pygrub fail sg-report-flight on osstest.xs.citrite.net logs: /home/osstest/logs images: /home/osstest/images Logs, config files, etc. are available at http://osstest.xs.citrite.net/~osstest/testlogs/logs Test harness code can be found at http://xenbits.xensource.com/gitweb?p=osstest.git;a=summary Push not applicable. ___ Xen-devel mailing list Xen-devel@lists.xen.org https://lists.xen.org/xen-devel
[Xen-devel] [qemu-mainline baseline-only test] 71136: regressions - trouble: blocked/broken/fail/pass
This run is configured for baseline tests only. flight 71136 qemu-mainline real [real] http://osstest.xs.citrite.net/~osstest/testlogs/logs/71136/ Regressions :-( Tests which did not succeed and are blocking, including tests which could not be run: test-amd64-i386-freebsd10-amd64 21 leak-check/check fail REGR. vs. 71132 Regressions which are regarded as allowable (not blocking): test-armhf-armhf-libvirt-xsm 13 saverestore-support-check fail blocked in 71132 test-armhf-armhf-libvirt13 saverestore-support-check fail blocked in 71132 test-armhf-armhf-libvirt-raw 12 saverestore-support-check fail blocked in 71132 test-armhf-armhf-libvirt-xsm 15 guest-start/debian.repeat fail blocked in 71132 test-amd64-amd64-qemuu-nested-intel 16 debian-hvm-install/l1/l2 fail like 71132 test-amd64-i386-xl-qemuu-winxpsp3-vcpus1 9 windows-installfail like 71132 Tests which did not succeed, but are not blocking: test-arm64-arm64-libvirt-xsm 1 build-check(1) blocked n/a test-arm64-arm64-xl 1 build-check(1) blocked n/a build-arm64-libvirt 1 build-check(1) blocked n/a test-arm64-arm64-libvirt-qcow2 1 build-check(1) blocked n/a test-arm64-arm64-libvirt 1 build-check(1) blocked n/a test-arm64-arm64-xl-credit2 1 build-check(1) blocked n/a test-arm64-arm64-xl-rtds 1 build-check(1) blocked n/a test-arm64-arm64-xl-multivcpu 1 build-check(1) blocked n/a test-arm64-arm64-xl-xsm 1 build-check(1) blocked n/a build-arm64 2 hosts-allocate broken never pass build-arm64-pvops 2 hosts-allocate broken never pass build-arm64 3 capture-logs broken never pass build-arm64-pvops 3 capture-logs broken never pass build-arm64-xsm 2 hosts-allocate broken never pass build-arm64-xsm 3 capture-logs broken never pass test-armhf-armhf-xl-xsm 12 migrate-support-checkfail never pass test-armhf-armhf-xl-xsm 13 saverestore-support-checkfail never pass test-armhf-armhf-libvirt-xsm 12 migrate-support-checkfail never pass test-armhf-armhf-xl-midway 12 migrate-support-checkfail never pass test-armhf-armhf-xl-midway 13 saverestore-support-checkfail never pass test-armhf-armhf-xl-multivcpu 12 migrate-support-checkfail never pass test-armhf-armhf-xl-multivcpu 13 saverestore-support-checkfail never pass test-armhf-armhf-xl-credit2 12 migrate-support-checkfail never pass test-armhf-armhf-libvirt 12 migrate-support-checkfail never pass test-armhf-armhf-xl-credit2 13 saverestore-support-checkfail never pass test-armhf-armhf-xl 12 migrate-support-checkfail never pass test-armhf-armhf-xl 13 saverestore-support-checkfail never pass test-armhf-armhf-xl-rtds 12 migrate-support-checkfail never pass test-armhf-armhf-xl-rtds 13 saverestore-support-checkfail never pass test-amd64-amd64-libvirt 12 migrate-support-checkfail never pass test-amd64-i386-libvirt-xsm 12 migrate-support-checkfail never pass test-amd64-i386-libvirt 12 migrate-support-checkfail never pass test-amd64-amd64-libvirt-xsm 12 migrate-support-checkfail never pass test-armhf-armhf-libvirt-raw 11 migrate-support-checkfail never pass test-amd64-amd64-libvirt-qemuu-debianhvm-amd64-xsm 10 migrate-support-check fail never pass test-amd64-i386-libvirt-qemuu-debianhvm-amd64-xsm 10 migrate-support-check fail never pass test-armhf-armhf-xl-vhd 11 migrate-support-checkfail never pass test-armhf-armhf-xl-vhd 12 saverestore-support-checkfail never pass test-amd64-amd64-qemuu-nested-amd 16 debian-hvm-install/l1/l2 fail never pass test-amd64-amd64-libvirt-vhd 11 migrate-support-checkfail never pass test-amd64-amd64-xl-qemuu-win7-amd64 16 guest-stop fail never pass test-amd64-i386-xl-qemuu-win7-amd64 16 guest-stop fail never pass version targeted for testing: qemuua0ee3797bf4917b1b7a4554a4dffbb45f387f087 baseline version: qemuuddc2c3a57e0752c0650fdb735a8b8322542d4248 Last test of basis71132 2017-03-31 10:14:50 Z1 days Testing same since71136 2017-04-01 04:17:56 Z0 days1 attempts People who touched revisions under test: Andrew Baumann Jason Wang Peter Maydell jobs: build-amd64-xsm pass build-arm64-xsm broken build-armhf-xsm pass build-i386-xsm
Re: [Xen-devel] [PATCH v3 19/26] ARM: vITS: handle MAPTI command
On Fri, Mar 31, 2017 at 11:35 PM, Andre Przywara wrote:
> The MAPTI commands associates a DeviceID/EventID pair with a LPI/CPU
> pair and actually instantiates LPI interrupts.
> We connect the already allocated host LPI to this virtual LPI, so that
> any triggering IRQ on the host can be quickly forwarded to a guest.
> Beside entering the VCPU and the virtual LPI number in the respective
> host LPI entry, we also initialize and add the already allocated
> struct pending_irq to our radix tree, so that we can now easily find it
> by its virtual LPI number.
> This exports the vgic_init_pending_irq() function for that purpose.
>
> Signed-off-by: Andre Przywara
> ---
> xen/arch/arm/gic-v3-its.c| 74
>
> xen/arch/arm/gic-v3-lpi.c| 16 +
> xen/arch/arm/vgic-v3-its.c | 36 +--
> xen/arch/arm/vgic.c | 2 +-
> xen/include/asm-arm/gic_v3_its.h | 6
> xen/include/asm-arm/vgic.h | 1 +
> 6 files changed, 132 insertions(+), 3 deletions(-)
>
> diff --git a/xen/arch/arm/gic-v3-its.c b/xen/arch/arm/gic-v3-its.c
> index 8db2a09..39f16b2 100644
> --- a/xen/arch/arm/gic-v3-its.c
> +++ b/xen/arch/arm/gic-v3-its.c
> @@ -747,6 +747,80 @@ restart:
> spin_unlock(&d->arch.vgic.its_devices_lock);
> }
>
> +/* Must be called with the its_device_lock held. */
> +static struct its_devices *get_its_device(struct domain *d, paddr_t doorbell,
> + uint32_t devid)
> +{
> +struct rb_node *node = d->arch.vgic.its_devices.rb_node;
> +struct its_devices *dev;
> +
> +while (node)
> +{
> +int cmp;
> +
> +dev = rb_entry(node, struct its_devices, rbnode);
> +cmp = compare_its_guest_devices(dev, doorbell, devid);
> +
> +if ( !cmp )
> +return dev;
> +
> +if ( cmp > 0 )
> +node = node->rb_left;
> +else
> +node = node->rb_right;
> +}
> +
> +return NULL;
> +}
> +
> +static uint32_t get_host_lpi(struct its_devices *dev, uint32_t eventid)
> +{
> +uint32_t host_lpi = 0;
> +
> +if ( dev && (eventid < dev->eventids) )
> +{
> +host_lpi = dev->host_lpi_blocks[eventid / LPI_BLOCK] +
> + (eventid % LPI_BLOCK);
> +if ( !is_lpi(host_lpi) )
> +host_lpi = 0;
> +}
> +
> +return host_lpi;
> +}
> +
> +/*
> + * Connects the event ID for an already assigned device to the given
> VCPU/vLPI
> + * pair. The corresponding physical LPI is already mapped on the host side
> + * (when assigning the physical device to the guest), so we just connect the
> + * target VCPU/vLPI pair to that interrupt to inject it properly if it fires.
> + */
> +struct pending_irq *gicv3_assign_guest_event(struct domain *d,
> + paddr_t doorbell_address,
> + uint32_t devid, uint32_t
> eventid,
> + struct vcpu *v, uint32_t
> virt_lpi)
> +{
> +struct its_devices *dev;
> +struct pending_irq *pirq = NULL;
> +uint32_t host_lpi = 0;
> +
> +spin_lock(&d->arch.vgic.its_devices_lock);
> +dev = get_its_device(d, doorbell_address, devid);
> +if ( dev )
> +{
> +host_lpi = get_host_lpi(dev, eventid);
> +pirq = &dev->pend_irqs[eventid];
> +}
> +spin_unlock(&d->arch.vgic.its_devices_lock);
> +
> +if ( !host_lpi || !pirq )
> +return NULL;
> +
> +gicv3_lpi_update_host_entry(host_lpi, d->domain_id,
> +v ? v->vcpu_id : -1, virt_lpi);
> +
> +return pirq;
> +}
> +
> /* Scan the DT for any ITS nodes and create a list of host ITSes out of it.
> */
> void gicv3_its_dt_init(const struct dt_device_node *node)
> {
> diff --git a/xen/arch/arm/gic-v3-lpi.c b/xen/arch/arm/gic-v3-lpi.c
> index 2301d53..a6b728e 100644
> --- a/xen/arch/arm/gic-v3-lpi.c
> +++ b/xen/arch/arm/gic-v3-lpi.c
> @@ -178,6 +178,22 @@ void do_LPI(unsigned int lpi)
> rcu_unlock_domain(d);
> }
>
> +void gicv3_lpi_update_host_entry(uint32_t host_lpi, int domain_id,
> + unsigned int vcpu_id, uint32_t virt_lpi)
> +{
> +union host_lpi *hlpip, hlpi;
> +
> +host_lpi -= LPI_OFFSET;
> +
> +hlpip = &lpi_data.host_lpis[host_lpi / HOST_LPIS_PER_PAGE][host_lpi %
> HOST_LPIS_PER_PAGE];
> +
> +hlpi.virt_lpi = virt_lpi;
> +hlpi.dom_id = domain_id;
> +hlpi.vcpu_id = vcpu_id;
> +
> +write_u64_atomic(&hlpip->data, hlpi.data);
> +}
> +
> static int gicv3_lpi_allocate_pendtable(uint64_t *reg)
> {
> uint64_t val;
> diff --git a/xen/arch/arm/vgic-v3-its.c b/xen/arch/arm/vgic-v3-its.c
> index 36b44f2..d9dce3f 100644
> --- a/xen/arch/arm/vgic-v3-its.c
> +++ b/xen/arch/arm/vgic-v3-its.c
> @@ -258,8 +258,8 @@ static bool read_itte(struct virt_its *its, uint32_t
> devid, uint32_t evid,
> }
>
> #define SKIP_LPI_UPDATE 1
> -b
Re: [Xen-devel] [PATCH v3 06/26] ARM: GICv3 ITS: introduce device mapping
Hi Andre,
On Fri, Mar 31, 2017 at 11:35 PM, Andre Przywara wrote:
> The ITS uses device IDs to map LPIs to a device. Dom0 will later use
> those IDs, which we directly pass on to the host.
> For this we have to map each device that Dom0 may request to a host
> ITS device with the same identifier.
> Allocate the respective memory and enter each device into an rbtree to
> later be able to iterate over it or to easily teardown guests.
>
> Signed-off-by: Andre Przywara
> ---
> xen/arch/arm/gic-v3-its.c| 227
> +++
> xen/arch/arm/vgic-v3.c | 4 +
> xen/include/asm-arm/domain.h | 3 +
> xen/include/asm-arm/gic_v3_its.h | 23
> 4 files changed, 257 insertions(+)
>
> diff --git a/xen/arch/arm/gic-v3-its.c b/xen/arch/arm/gic-v3-its.c
> index 1ac598f..295f7dc 100644
> --- a/xen/arch/arm/gic-v3-its.c
> +++ b/xen/arch/arm/gic-v3-its.c
> @@ -21,6 +21,8 @@
> #include
> #include
> #include
> +#include
> +#include
> #include
> #include
> #include
> @@ -32,6 +34,18 @@
>
> LIST_HEAD(host_its_list);
>
> +struct its_devices {
> +struct rb_node rbnode;
> +struct host_its *hw_its;
> +void *itt_addr;
> +paddr_t guest_doorbell; /* Identifies the virtual ITS */
> +uint32_t host_devid;
> +uint32_t guest_devid;
> +uint32_t eventids; /* Number of event IDs (MSIs) */
> +uint32_t *host_lpi_blocks; /* Which LPIs are used on the host */
> +struct pending_irq *pend_irqs; /* One struct per event */
> +};
> +
> bool gicv3_its_host_has_its(void)
> {
> return !list_empty(&host_its_list);
> @@ -151,6 +165,26 @@ static int its_send_cmd_mapc(struct host_its *its,
> uint32_t collection_id,
> return its_send_command(its, cmd);
> }
>
> +static int its_send_cmd_mapd(struct host_its *its, uint32_t deviceid,
> + uint8_t size_bits, paddr_t itt_addr, bool valid)
> +{
> +uint64_t cmd[4];
> +
> +if ( valid )
> +{
> +ASSERT(size_bits < 32);
> +ASSERT(!(itt_addr & ~GENMASK_ULL(51, 8)));
> +}
> +cmd[0] = GITS_CMD_MAPD | ((uint64_t)deviceid << 32);
> +cmd[1] = size_bits;
> +cmd[2] = itt_addr;
> +if ( valid )
> +cmd[2] |= GITS_VALID_BIT;
> +cmd[3] = 0x00;
> +
> +return its_send_command(its, cmd);
> +}
> +
> /* Set up the (1:1) collection mapping for the given host CPU. */
> int gicv3_its_setup_collection(unsigned int cpu)
> {
> @@ -376,6 +410,7 @@ static int gicv3_its_init_single_its(struct host_its
> *hw_its)
> hw_its->devid_bits = min(hw_its->devid_bits, max_its_device_bits);
> if ( reg & GITS_TYPER_PTA )
> hw_its->flags |= HOST_ITS_USES_PTA;
> +hw_its->itte_size = GITS_TYPER_ITT_SIZE(reg);
>
> for ( i = 0; i < GITS_BASER_NR_REGS; i++ )
> {
> @@ -432,6 +467,197 @@ int gicv3_its_init(void)
> return 0;
> }
>
> +static int remove_mapped_guest_device(struct its_devices *dev)
> +{
> +int ret;
> +
> +if ( dev->hw_its )
> +{
> +/* MAPD also discards all events with this device ID. */
> +int ret = its_send_cmd_mapd(dev->hw_its, dev->host_devid, 0, 0,
> false);
> +if ( ret )
> +return ret;
> +}
> +
> +ret = gicv3_its_wait_commands(dev->hw_its);
> +if ( ret )
> +return ret;
> +
> +xfree(dev->itt_addr);
> +xfree(dev->pend_irqs);
> +xfree(dev);
> +
> +return 0;
> +}
> +
> +static struct host_its *gicv3_its_find_by_doorbell(paddr_t doorbell_address)
> +{
> +struct host_its *hw_its;
> +
> +list_for_each_entry(hw_its, &host_its_list, entry)
> +{
> +if ( hw_its->addr + ITS_DOORBELL_OFFSET == doorbell_address )
> +return hw_its;
> +}
> +
> +return NULL;
> +}
> +
> +static int compare_its_guest_devices(struct its_devices *dev,
> + paddr_t doorbell, uint32_t devid)
> +{
> +if ( dev->guest_doorbell < doorbell )
> +return -1;
> +
> +if ( dev->guest_doorbell > doorbell )
> +return 1;
> +
> +if ( dev->guest_devid < devid )
> +return -1;
> +
> +if ( dev->guest_devid > devid )
> +return 1;
> +
> +return 0;
> +}
> +
> +/*
> + * Map a hardware device, identified by a certain host ITS and its device ID
> + * to domain d, a guest ITS (identified by its doorbell address) and device
> ID.
> + * Also provide the number of events (MSIs) needed for that device.
> + * This does not check if this particular hardware device is already mapped
> + * at another domain, it is expected that this would be done by the caller.
> + */
> +int gicv3_its_map_guest_device(struct domain *d,
> + paddr_t host_doorbell, uint32_t host_devid,
> + paddr_t guest_doorbell, uint32_t guest_devid,
> + uint32_t nr_events, bool valid)
> +{
> +void *itt_addr = NULL;
> +struct host_its *hw_its;
> +struc
[Xen-devel] [ovmf test] 107039: all pass - PUSHED
flight 107039 ovmf real [real]
http://logs.test-lab.xenproject.org/osstest/logs/107039/
Perfect :-)
All tests in this flight passed as required
version targeted for testing:
ovmf 4ef6c3850e66617df1ed35a4a390567d2bbf6b76
baseline version:
ovmf de87f23291620d36d69ec55ea53a1c38b8780f0b
Last test of basis 107018 2017-03-31 05:47:36 Z1 days
Failing since107022 2017-03-31 09:16:43 Z0 days3 attempts
Testing same since 107039 2017-03-31 17:15:10 Z0 days1 attempts
People who touched revisions under test:
Ard Biesheuvel
Chen A Chen
Laszlo Ersek
Marc Zyngier
Ruiyu Ni
jobs:
build-amd64-xsm pass
build-i386-xsm pass
build-amd64 pass
build-i386 pass
build-amd64-libvirt pass
build-i386-libvirt pass
build-amd64-pvopspass
build-i386-pvops pass
test-amd64-amd64-xl-qemuu-ovmf-amd64 pass
test-amd64-i386-xl-qemuu-ovmf-amd64 pass
sg-report-flight on osstest.test-lab.xenproject.org
logs: /home/logs/logs
images: /home/logs/images
Logs, config files, etc. are available at
http://logs.test-lab.xenproject.org/osstest/logs
Explanation of these reports, and of osstest in general, is at
http://xenbits.xen.org/gitweb/?p=osstest.git;a=blob;f=README.email;hb=master
http://xenbits.xen.org/gitweb/?p=osstest.git;a=blob;f=README;hb=master
Test harness code can be found at
http://xenbits.xen.org/gitweb?p=osstest.git;a=summary
Pushing revision :
+ branch=ovmf
+ revision=4ef6c3850e66617df1ed35a4a390567d2bbf6b76
+ . ./cri-lock-repos
++ . ./cri-common
+++ . ./cri-getconfig
+++ umask 002
+++ getrepos
getconfig Repos
perl -e '
use Osstest;
readglobalconfig();
print $c{"Repos"} or die $!;
'
+++ local repos=/home/osstest/repos
+++ '[' -z /home/osstest/repos ']'
+++ '[' '!' -d /home/osstest/repos ']'
+++ echo /home/osstest/repos
++ repos=/home/osstest/repos
++ repos_lock=/home/osstest/repos/lock
++ '[' x '!=' x/home/osstest/repos/lock ']'
++ OSSTEST_REPOS_LOCK_LOCKED=/home/osstest/repos/lock
++ exec with-lock-ex -w /home/osstest/repos/lock ./ap-push ovmf
4ef6c3850e66617df1ed35a4a390567d2bbf6b76
+ branch=ovmf
+ revision=4ef6c3850e66617df1ed35a4a390567d2bbf6b76
+ . ./cri-lock-repos
++ . ./cri-common
+++ . ./cri-getconfig
+++ umask 002
+++ getrepos
getconfig Repos
perl -e '
use Osstest;
readglobalconfig();
print $c{"Repos"} or die $!;
'
+++ local repos=/home/osstest/repos
+++ '[' -z /home/osstest/repos ']'
+++ '[' '!' -d /home/osstest/repos ']'
+++ echo /home/osstest/repos
++ repos=/home/osstest/repos
++ repos_lock=/home/osstest/repos/lock
++ '[' x/home/osstest/repos/lock '!=' x/home/osstest/repos/lock ']'
+ . ./cri-common
++ . ./cri-getconfig
++ umask 002
+ select_xenbranch
+ case "$branch" in
+ tree=ovmf
+ xenbranch=xen-unstable
+ '[' xovmf = xlinux ']'
+ linuxbranch=
+ '[' x = x ']'
+ qemuubranch=qemu-upstream-unstable
+ select_prevxenbranch
++ ./cri-getprevxenbranch xen-unstable
+ prevxenbranch=xen-4.8-testing
+ '[' x4ef6c3850e66617df1ed35a4a390567d2bbf6b76 = x ']'
+ : tested/2.6.39.x
+ . ./ap-common
++ : osst...@xenbits.xen.org
+++ getconfig OsstestUpstream
+++ perl -e '
use Osstest;
readglobalconfig();
print $c{"OsstestUpstream"} or die $!;
'
++ :
++ : git://xenbits.xen.org/xen.git
++ : osst...@xenbits.xen.org:/home/xen/git/xen.git
++ : git://xenbits.xen.org/qemu-xen-traditional.git
++ : git://git.kernel.org
++ : git://git.kernel.org/pub/scm/linux/kernel/git
++ : git
++ : git://xenbits.xen.org/xtf.git
++ : osst...@xenbits.xen.org:/home/xen/git/xtf.git
++ : git://xenbits.xen.org/xtf.git
++ : git://xenbits.xen.org/libvirt.git
++ : osst...@xenbits.xen.org:/home/xen/git/libvirt.git
++ : git://xenbits.xen.org/libvirt.git
++ : git://xenbits.xen.org/osstest/rumprun.git
++ : git
++ : git://xenbits.xen.org/osstest/rumprun.git
++ : osst...@xenbits.xen.org:/home/xen/git/osstest/rumprun.git
++ : git://git.seabios.org/seabios.git
++ : osst...@xenbits.xen.org:/home/xen/git/osstest/seabios.git
++ : git://xenbits.xen.org/osstest/seabios.git
++ : https://github.com/tianocore/edk2.git
++ : osst...@xenbits.xen.org:/home/xen/git/osstest/ovmf.git
++ : git://xenbits.xen.org/osstest/ovmf.git
++ : git://xenbits.xen.org/osstest/linux-firmware.git
++ : osst...@xenbits.xen.org:/home/osstest/ext/linux-firmware.g
[Xen-devel] [xen-unstable test] 107034: tolerable FAIL - PUSHED
flight 107034 xen-unstable real [real] http://logs.test-lab.xenproject.org/osstest/logs/107034/ Failures :-/ but no regressions. Regressions which are regarded as allowable (not blocking): test-armhf-armhf-libvirt-xsm 13 saverestore-support-checkfail like 107015 test-armhf-armhf-libvirt 13 saverestore-support-checkfail like 107015 test-amd64-amd64-xl-qemut-win7-amd64 16 guest-stopfail like 107015 test-amd64-i386-xl-qemuu-win7-amd64 16 guest-stop fail like 107015 test-amd64-i386-xl-qemut-win7-amd64 16 guest-stop fail like 107015 test-amd64-amd64-xl-qemuu-win7-amd64 16 guest-stopfail like 107015 test-armhf-armhf-libvirt-raw 12 saverestore-support-checkfail like 107015 test-amd64-amd64-xl-rtds 9 debian-install fail like 107015 Tests which did not succeed, but are not blocking: test-arm64-arm64-libvirt-xsm 1 build-check(1) blocked n/a test-arm64-arm64-xl 1 build-check(1) blocked n/a build-arm64-libvirt 1 build-check(1) blocked n/a test-arm64-arm64-libvirt-qcow2 1 build-check(1) blocked n/a test-arm64-arm64-libvirt 1 build-check(1) blocked n/a test-arm64-arm64-xl-credit2 1 build-check(1) blocked n/a test-arm64-arm64-xl-rtds 1 build-check(1) blocked n/a test-arm64-arm64-xl-multivcpu 1 build-check(1) blocked n/a test-arm64-arm64-xl-xsm 1 build-check(1) blocked n/a test-amd64-i386-libvirt 12 migrate-support-checkfail never pass test-amd64-i386-libvirt-xsm 12 migrate-support-checkfail never pass test-amd64-amd64-libvirt-xsm 12 migrate-support-checkfail never pass test-amd64-amd64-libvirt 12 migrate-support-checkfail never pass build-arm64 5 xen-buildfail never pass build-arm64-xsm 5 xen-buildfail never pass test-amd64-amd64-libvirt-qemuu-debianhvm-amd64-xsm 10 migrate-support-check fail never pass test-amd64-i386-libvirt-qemuu-debianhvm-amd64-xsm 10 migrate-support-check fail never pass build-arm64-pvops 5 kernel-build fail never pass test-armhf-armhf-xl-arndale 12 migrate-support-checkfail never pass test-armhf-armhf-xl-arndale 13 saverestore-support-checkfail never pass test-amd64-amd64-libvirt-vhd 11 migrate-support-checkfail never pass test-armhf-armhf-xl-xsm 12 migrate-support-checkfail never pass test-armhf-armhf-xl-xsm 13 saverestore-support-checkfail never pass test-armhf-armhf-xl-multivcpu 12 migrate-support-checkfail never pass test-armhf-armhf-xl-multivcpu 13 saverestore-support-checkfail never pass test-amd64-amd64-qemuu-nested-amd 16 debian-hvm-install/l1/l2 fail never pass test-armhf-armhf-libvirt-xsm 12 migrate-support-checkfail never pass test-armhf-armhf-libvirt 12 migrate-support-checkfail never pass test-armhf-armhf-xl 12 migrate-support-checkfail never pass test-armhf-armhf-xl 13 saverestore-support-checkfail never pass test-armhf-armhf-xl-credit2 12 migrate-support-checkfail never pass test-armhf-armhf-xl-credit2 13 saverestore-support-checkfail never pass test-armhf-armhf-xl-cubietruck 12 migrate-support-checkfail never pass test-armhf-armhf-xl-cubietruck 13 saverestore-support-checkfail never pass test-armhf-armhf-xl-rtds 12 migrate-support-checkfail never pass test-armhf-armhf-xl-rtds 13 saverestore-support-checkfail never pass test-armhf-armhf-libvirt-raw 11 migrate-support-checkfail never pass test-armhf-armhf-xl-vhd 11 migrate-support-checkfail never pass test-armhf-armhf-xl-vhd 12 saverestore-support-checkfail never pass version targeted for testing: xen 35673d2419af4fde4f235414937bec38864db295 baseline version: xen 3bdb14004b9fe8c35e4961f8a7c73c19f0fb4365 Last test of basis 107015 2017-03-31 02:21:45 Z1 days Testing same since 107034 2017-03-31 14:13:27 Z0 days1 attempts People who touched revisions under test: Al Stone Bob Moore Jan Beulich Lv Zheng Rafael J. Wysocki Sameer Goel jobs: build-amd64-xsm pass build-arm64-xsm fail build-armhf-xsm pass build-i386-xsm pass build-amd64-xtf pass build-amd64 pass build-arm64 fail bui
