This patch adds the detection and initialization code for VMX TSC
scaling.
Signed-off-by: Haozhong Zhang
---
xen/arch/x86/hvm/vmx/vmcs.c| 11 +--
xen/arch/x86/hvm/vmx/vmx.c | 9 +
xen/include/asm-x86/hvm/vmx/vmcs.h | 7 +++
3 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c
index 08f2078..7172b27 100644
--- a/xen/arch/x86/hvm/vmx/vmcs.c
+++ b/xen/arch/x86/hvm/vmx/vmcs.c
@@ -144,6 +144,7 @@ static void __init vmx_display_features(void)
P(cpu_has_vmx_vmfunc, "VM Functions");
P(cpu_has_vmx_virt_exceptions, "Virtualisation Exceptions");
P(cpu_has_vmx_pml, "Page Modification Logging");
+P(cpu_has_vmx_tsc_scaling, "RDTSC(P) Scaling");
#undef P
if ( !printed )
@@ -236,7 +237,8 @@ static int vmx_init_vmcs_config(void)
SECONDARY_EXEC_PAUSE_LOOP_EXITING |
SECONDARY_EXEC_ENABLE_INVPCID |
SECONDARY_EXEC_ENABLE_VM_FUNCTIONS |
- SECONDARY_EXEC_ENABLE_VIRT_EXCEPTIONS);
+ SECONDARY_EXEC_ENABLE_VIRT_EXCEPTIONS |
+ SECONDARY_EXEC_TSC_SCALING);
rdmsrl(MSR_IA32_VMX_MISC, _vmx_misc_cap);
if ( _vmx_misc_cap & VMX_MISC_VMWRITE_ALL )
opt |= SECONDARY_EXEC_ENABLE_VMCS_SHADOWING;
@@ -965,7 +967,7 @@ static int construct_vmcs(struct vcpu *v)
__vmwrite(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_control);
v->arch.hvm_vmx.exec_control = vmx_cpu_based_exec_control;
-if ( d->arch.vtsc )
+if ( d->arch.vtsc && !cpu_has_vmx_tsc_scaling )
v->arch.hvm_vmx.exec_control |= CPU_BASED_RDTSC_EXITING;
v->arch.hvm_vmx.secondary_exec_control = vmx_secondary_exec_control;
@@ -1239,6 +1241,9 @@ static int construct_vmcs(struct vcpu *v)
__vmwrite(GUEST_PAT, guest_pat);
}
+if ( cpu_has_vmx_tsc_scaling )
+__vmwrite(TSC_MULTIPLIER, VMX_TSC_MULTIPLIER_DEFAULT);
+
vmx_vmcs_exit(v);
/* PVH: paging mode is updated by arch_set_info_guest(). */
@@ -1805,6 +1810,8 @@ void vmcs_dump_vcpu(struct vcpu *v)
printk("IDTVectoring: info=%08x errcode=%08x\n",
vmr32(IDT_VECTORING_INFO), vmr32(IDT_VECTORING_ERROR_CODE));
printk("TSC Offset = 0x%016lx\n", vmr(TSC_OFFSET));
+if ( v->arch.hvm_vmx.secondary_exec_control & SECONDARY_EXEC_TSC_SCALING )
+printk("TSC Multiplier = 0x%016lx\n", vmr(TSC_MULTIPLIER));
if ( (v->arch.hvm_vmx.exec_control & CPU_BASED_TPR_SHADOW) ||
(vmx_pin_based_exec_control & PIN_BASED_POSTED_INTERRUPT) )
printk("TPR Threshold = 0x%02x PostedIntrVec = 0x%02x\n",
diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c
index 624db1c..454440e 100644
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -151,6 +151,8 @@ static int vmx_vcpu_initialise(struct vcpu *v)
if ( v->vcpu_id == 0 )
v->arch.user_regs.eax = 1;
+v->arch.tsc_scaling_ratio = VMX_TSC_MULTIPLIER_DEFAULT;
+
return 0;
}
@@ -1965,6 +1967,10 @@ static struct hvm_function_table __initdata
vmx_function_table = {
.altp2m_vcpu_emulate_vmfunc = vmx_vcpu_emulate_vmfunc,
/* support for VMX RDTSC(P) scaling */
.tsc_scaling_supported = 0,
+.default_tsc_scaling_ratio = VMX_TSC_MULTIPLIER_DEFAULT,
+.max_tsc_scaling_ratio = VMX_TSC_MULTIPLIER_MAX,
+.tsc_scaling_ratio_frac_bits = 48,
+.tsc_scaling_ratio_rsvd = 0x0ULL,
};
const struct hvm_function_table * __init start_vmx(void)
@@ -2017,6 +2023,9 @@ const struct hvm_function_table * __init start_vmx(void)
&& cpu_has_vmx_secondary_exec_control )
vmx_function_table.pvh_supported = 1;
+if ( cpu_has_vmx_tsc_scaling )
+vmx_function_table.tsc_scaling_supported = 1;
+
setup_vmcs_dump();
return _function_table;
diff --git a/xen/include/asm-x86/hvm/vmx/vmcs.h
b/xen/include/asm-x86/hvm/vmx/vmcs.h
index f1126d4..d478584 100644
--- a/xen/include/asm-x86/hvm/vmx/vmcs.h
+++ b/xen/include/asm-x86/hvm/vmx/vmcs.h
@@ -225,6 +225,7 @@ extern u32 vmx_vmentry_control;
#define SECONDARY_EXEC_ENABLE_VMCS_SHADOWING0x4000
#define SECONDARY_EXEC_ENABLE_PML 0x0002
#define SECONDARY_EXEC_ENABLE_VIRT_EXCEPTIONS 0x0004
+#define SECONDARY_EXEC_TSC_SCALING 0x0200
extern u32 vmx_secondary_exec_control;
#define VMX_EPT_EXEC_ONLY_SUPPORTED 0x0001
@@ -248,6 +249,9 @@ extern u32 vmx_secondary_exec_control;
#define VMX_MISC_CR3_TARGET 0x1ff
+#define VMX_TSC_MULTIPLIER_DEFAULT 0x0001ULL
+#define VMX_TSC_MULTIPLIER_MAX 0xULL
+
#define cpu_has_wbinvd_exiting \
(vmx_secondary_exec_control & SECONDARY_EXEC_WBINVD_EXITING)
#define cpu_has_vmx_virtualize_apic_accesses \
@@ -291,6 +295,8 @@ extern u32 vmx_secondary_exec_control;
(vmx_secondary_exec_control & SECONDARY_EXEC_ENABLE_VIRT_EXCEPTIONS)