Gather the affected handlers in a single place per trap type.
Add some HSR_SYSREG and AArch32 defines for those registers (because
I'd already typed them in when I realised I didn't need them).
Signed-off-by: Ian Campbell <ian.campb...@citrix.com>
---
xen/arch/arm/traps.c | 37 +++++++++++++++++++++++++++++--------
xen/include/asm-arm/cpregs.h | 2 ++
xen/include/asm-arm/sysregs.h | 2 ++
3 files changed, 33 insertions(+), 8 deletions(-)
diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index 7c37cec..518f047 100644
--- a/xen/arch/arm/traps.c
+++ b/xen/arch/arm/traps.c
@@ -1801,6 +1801,21 @@ static void do_cp14_32(struct cpu_user_regs *regs, const
union hsr hsr)
* DBGDSAR
*/
+ /*
+ * MDCR_EL2.TDOSA
+ *
+ * ARMv7 (DDI 0406C.b): B1.14.15
+ * ARMv8 (DDI 0487A.d): D1-1509 Table D1-58
+ *
+ * Unhandled:
+ * DBGOSLSR
+ * DBGPRCR
+ */
+ case HSR_CPREG32(DBGOSLAR):
+ return handle_wo_wi(regs, r, cp32.read, hsr, 1);
+ case HSR_CPREG32(DBGOSDLR):
+ return handle_raz_wi(regs, r, cp32.read, hsr, 1);
+
case HSR_CPREG32(DBGDIDR):
/*
* Read-only register. Accessible by EL0 if DBGDSCRext.UDCCdis
@@ -1840,12 +1855,8 @@ static void do_cp14_32(struct cpu_user_regs *regs, const
union hsr hsr)
case HSR_CPREG32(DBGWCR0):
case HSR_CPREG32(DBGBVR1):
case HSR_CPREG32(DBGBCR1):
- case HSR_CPREG32(DBGOSDLR):
return handle_raz_wi(regs, r, cp32.read, hsr, 1);
- case HSR_CPREG32(DBGOSLAR):
- return handle_wo_wi(regs, r, cp32.read, hsr, 1);
-
/*
* CPTR_EL2.TTA
*
@@ -1968,6 +1979,20 @@ static void do_sysreg(struct cpu_user_regs *regs,
case HSR_SYSREG_MDRAR_EL1:
return handle_ro_raz(regs, x, hsr.sysreg.read, hsr, 1);
+ /*
+ * MDCR_EL2.TDOSA
+ *
+ * ARMv8 (DDI 0487A.d): D1-1509 Table D1-58
+ *
+ * Unhandled:
+ * OSLSR_EL1
+ * DBGPRCR_EL1
+ */
+ case HSR_SYSREG_OSLAR_EL1:
+ return handle_wo_wi(regs, x, hsr.sysreg.read, hsr, 1);
+ case HSR_SYSREG_OSDLR_EL1:
+ return handle_raz_wi(regs, x, hsr.sysreg.read, hsr, 1);
+
/* RAZ/WI registers: */
/* - Debug */
case HSR_SYSREG_MDSCR_EL1:
@@ -1977,8 +2002,6 @@ static void do_sysreg(struct cpu_user_regs *regs,
/* - Watchpoints */
HSR_SYSREG_DBG_CASES(DBGWVR):
HSR_SYSREG_DBG_CASES(DBGWCR):
- /* - Double Lock Register */
- case HSR_SYSREG_OSDLR_EL1:
/* - Perf monitors */
case HSR_SYSREG_PMINTENSET_EL1:
case HSR_SYSREG_PMINTENCLR_EL1:
@@ -2021,8 +2044,6 @@ static void do_sysreg(struct cpu_user_regs *regs,
return handle_raz_wi(regs, x, hsr.sysreg.read, hsr, 1);
/* Write only, Write ignore registers: */
- case HSR_SYSREG_OSLAR_EL1:
- return handle_wo_wi(regs, x, hsr.sysreg.read, hsr, 1);
case HSR_SYSREG_CNTP_CTL_EL0:
case HSR_SYSREG_CNTP_TVAL_EL0:
diff --git a/xen/include/asm-arm/cpregs.h b/xen/include/asm-arm/cpregs.h
index 9db8cfd..e5cb00c 100644
--- a/xen/include/asm-arm/cpregs.h
+++ b/xen/include/asm-arm/cpregs.h
@@ -83,7 +83,9 @@
#define DBGBVR1 p14,0,c0,c1,4 /* Breakpoint Value 1 */
#define DBGBCR1 p14,0,c0,c1,5 /* Breakpoint Control 1 */
#define DBGOSLAR p14,0,c1,c0,4 /* OS Lock Access */
+#define DBGOSLSR p14,0,c1,c1,4 /* OS Lock Status Register */
#define DBGOSDLR p14,0,c1,c3,4 /* OS Double Lock */
+#define DBGPRCR p14,0,c1,c4,4 /* Debug Power Control Register */
/* CP14 CR0: */
#define TEECR p14,6,c0,c0,0 /* ThumbEE Configuration Register */
diff --git a/xen/include/asm-arm/sysregs.h b/xen/include/asm-arm/sysregs.h
index 55457fd..570f43e 100644
--- a/xen/include/asm-arm/sysregs.h
+++ b/xen/include/asm-arm/sysregs.h
@@ -47,7 +47,9 @@
#define HSR_SYSREG_MDSCR_EL1 HSR_SYSREG(2,0,c0,c2,2)
#define HSR_SYSREG_MDRAR_EL1 HSR_SYSREG(2,0,c1,c0,0)
#define HSR_SYSREG_OSLAR_EL1 HSR_SYSREG(2,0,c1,c0,4)
+#define HSR_SYSREG_OSLSR_EL1 HSR_SYSREG(2,0,c1,c1,4)
#define HSR_SYSREG_OSDLR_EL1 HSR_SYSREG(2,0,c1,c3,4)
+#define HSR_SYSREG_DBGPRCR_EL1 HSR_SYSREG(2,0,c1,c4,4)
#define HSR_SYSREG_MDCCSR_EL0 HSR_SYSREG(2,3,c0,c1,0)
#define HSR_SYSREG_DBGBVRn_EL1(n) HSR_SYSREG(2,0,c0,c##n,4)
--
1.7.10.4
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