Re: [Xen-devel] [PATCH v4 3/3] xen/iommu: arm: Use p2m_ipa_bits as stage2 input size
On Fri, 2015-05-01 at 11:40 +1000, Edgar E. Iglesias wrote:
From: Edgar E. Iglesias edgar.igles...@xilinx.com
The Stage2 input-size must match what the CPU uses because
the SMMU and the CPU share page-tables.
Test that the SMMU supports the P2M IPA bit size, use it if
supported or bail out if not.
Signed-off-by: Edgar E. Iglesias edgar.igles...@xilinx.com
---
xen/drivers/passthrough/arm/smmu.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/xen/drivers/passthrough/arm/smmu.c
b/xen/drivers/passthrough/arm/smmu.c
index 8a9b58b..d9f3931 100644
--- a/xen/drivers/passthrough/arm/smmu.c
+++ b/xen/drivers/passthrough/arm/smmu.c
@@ -2230,8 +2230,14 @@ static int arm_smmu_device_cfg_probe(struct
arm_smmu_device *smmu)
size = arm_smmu_id_size_to_bits((id ID2_IAS_SHIFT) ID2_IAS_MASK);
smmu-s1_output_size = min_t(unsigned long, PHYS_MASK_SHIFT, size);
- /* Xen: Stage-2 input size is not restricted */
- smmu-s2_input_size = size;
+ /* Xen: Stage-2 input size has to match p2m_ipa_bits. */
+ if (size p2m_ipa_bits) {
Referencing my question on 0/3, what if size p2m_ipa_bits?
Do we need to also check that we are configuring the same number of
levels of PT etc, or is that already handled?
+ dev_err(smmu-dev,
+ P2M IPA size not supported (P2M=%u SMMU=%lu)!\n,
+ p2m_ipa_bits, size);
+ return -ENODEV;
+ }
+ smmu-s2_input_size = p2m_ipa_bits;
#if 0
/* Stage-2 input size limited due to pgd allocation (PTRS_PER_PGD) */
#ifdef CONFIG_64BIT
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Re: [Xen-devel] [PATCH v4 3/3] xen/iommu: arm: Use p2m_ipa_bits as stage2 input size
On Tue, May 05, 2015 at 03:30:10PM +0100, Julien Grall wrote: On 05/05/15 14:59, Ian Campbell wrote: On Tue, 2015-05-05 at 14:48 +0100, Julien Grall wrote: Do we need to also check that we are configuring the same number of levels of PT etc, or is that already handled? The SMMU only care about the number of IPA bits. What ensures that the starting level of the SMMU matches the starting level of the MMU-s2? Nothing, it's hardcoded in the SMMU driver for now :/. It's assuming SL0 = 1 which works fine for ARM32 but would be an issue on platform with IPA = 44 bits. S2 output size may need to be restrict too depending of the PA bits. Right, these could cause problems. I've sent out a v5 of the ipa size series. I can have a look at these other MMU settings and send follow-up patches if there is interest? Cheers, Edgar ___ Xen-devel mailing list Xen-devel@lists.xen.org http://lists.xen.org/xen-devel
Re: [Xen-devel] [PATCH v4 3/3] xen/iommu: arm: Use p2m_ipa_bits as stage2 input size
On Tue, 2015-05-05 at 14:48 +0100, Julien Grall wrote: Do we need to also check that we are configuring the same number of levels of PT etc, or is that already handled? The SMMU only care about the number of IPA bits. What ensures that the starting level of the SMMU matches the starting level of the MMU-s2? Feeding a 3-level table to an MMU which is configured to expect 4 won't end well. Ian. ___ Xen-devel mailing list Xen-devel@lists.xen.org http://lists.xen.org/xen-devel
Re: [Xen-devel] [PATCH v4 3/3] xen/iommu: arm: Use p2m_ipa_bits as stage2 input size
On 05/05/15 14:59, Ian Campbell wrote: On Tue, 2015-05-05 at 14:48 +0100, Julien Grall wrote: Do we need to also check that we are configuring the same number of levels of PT etc, or is that already handled? The SMMU only care about the number of IPA bits. What ensures that the starting level of the SMMU matches the starting level of the MMU-s2? Nothing, it's hardcoded in the SMMU driver for now :/. It's assuming SL0 = 1 which works fine for ARM32 but would be an issue on platform with IPA = 44 bits. S2 output size may need to be restrict too depending of the PA bits. Regards, -- Julien Grall ___ Xen-devel mailing list Xen-devel@lists.xen.org http://lists.xen.org/xen-devel
Re: [Xen-devel] [PATCH v4 3/3] xen/iommu: arm: Use p2m_ipa_bits as stage2 input size
Hi Ian,
On 05/05/15 14:24, Ian Campbell wrote:
On Fri, 2015-05-01 at 11:40 +1000, Edgar E. Iglesias wrote:
From: Edgar E. Iglesias edgar.igles...@xilinx.com
The Stage2 input-size must match what the CPU uses because
the SMMU and the CPU share page-tables.
Test that the SMMU supports the P2M IPA bit size, use it if
supported or bail out if not.
Signed-off-by: Edgar E. Iglesias edgar.igles...@xilinx.com
---
xen/drivers/passthrough/arm/smmu.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/xen/drivers/passthrough/arm/smmu.c
b/xen/drivers/passthrough/arm/smmu.c
index 8a9b58b..d9f3931 100644
--- a/xen/drivers/passthrough/arm/smmu.c
+++ b/xen/drivers/passthrough/arm/smmu.c
@@ -2230,8 +2230,14 @@ static int arm_smmu_device_cfg_probe(struct
arm_smmu_device *smmu)
size = arm_smmu_id_size_to_bits((id ID2_IAS_SHIFT) ID2_IAS_MASK);
smmu-s1_output_size = min_t(unsigned long, PHYS_MASK_SHIFT, size);
-/* Xen: Stage-2 input size is not restricted */
-smmu-s2_input_size = size;
+/* Xen: Stage-2 input size has to match p2m_ipa_bits. */
+if (size p2m_ipa_bits) {
Referencing my question on 0/3, what if size p2m_ipa_bits?
The would require more work because we would need to restrict the P2M
which would cause other trouble (see my answer on 0/3) such as the 1:1
mapping in dom0.
Do we need to also check that we are configuring the same number of
levels of PT etc, or is that already handled?
The SMMU only care about the number of IPA bits.
Regards,
--
Julien Grall
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