[Xen-devel] [PATCH v4 1/4] x86emul: Support GFNI insns
Signed-off-by: Yang Zhong
---
xen/arch/x86/x86_emulate/x86_emulate.c | 21 +
xen/include/asm-x86/cpufeature.h | 3 +++
2 files changed, 24 insertions(+)
diff --git a/xen/arch/x86/x86_emulate/x86_emulate.c
b/xen/arch/x86/x86_emulate/x86_emulate.c
index 54a2756..2d331ea 100644
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -385,6 +385,7 @@ static const struct {
[0x40] = { .simd_size = simd_packed_int },
[0x41] = { .simd_size = simd_packed_int, .two_op = 1 },
[0xc8 ... 0xcd] = { .simd_size = simd_other },
+[0xcf] = { .simd_size = simd_packed_int },
[0xdb] = { .simd_size = simd_packed_int, .two_op = 1 },
[0xdc ... 0xdf] = { .simd_size = simd_packed_int },
[0xf0] = { .two_op = 1 },
@@ -421,6 +422,7 @@ static const struct {
[0x4c] = { .simd_size = simd_packed_int, .four_op = 1 },
[0x60 ... 0x63] = { .simd_size = simd_packed_int, .two_op = 1 },
[0xcc] = { .simd_size = simd_other },
+[0xce ... 0xcf] = { .simd_size = simd_packed_int },
[0xdf] = { .simd_size = simd_packed_int, .two_op = 1 },
[0xf0] = {},
};
@@ -1623,6 +1625,7 @@ static bool vcpu_has(
#define vcpu_has_clflushopt() vcpu_has( 7, EBX, 23, ctxt, ops)
#define vcpu_has_clwb()vcpu_has( 7, EBX, 24, ctxt, ops)
#define vcpu_has_sha() vcpu_has( 7, EBX, 29, ctxt, ops)
+#define vcpu_has_gfni()vcpu_has( 7, ECX, 8, ctxt, ops)
#define vcpu_has_rdpid() vcpu_has( 7, ECX, 22, ctxt, ops)
#define vcpu_has_clzero() vcpu_has(0x8008, EBX, 0, ctxt, ops)
@@ -7356,6 +7359,14 @@ x86_emulate(
op_bytes = 16;
goto simd_0f38_common;
+case X86EMUL_OPC_66(0x0f38, 0xcf): /* gf2p8mulb xmm/m128,xmm */
+case X86EMUL_OPC_VEX_66(0x0f38, 0xcf): /* vgf2p8mulb
{x,y}mm/mem,{x,y}mm,{x,y}mm */
+host_and_vcpu_must_have(gfni);
+if ( vex.opcx == vex_none )
+goto simd_0f38_common;
+generate_exception_if(vex.w, EXC_UD);
+goto simd_0f_avx;
+
case X86EMUL_OPC(0x0f38, 0xf0): /* movbe m,r */
case X86EMUL_OPC(0x0f38, 0xf1): /* movbe r,m */
vcpu_must_have(movbe);
@@ -7741,6 +7752,16 @@ x86_emulate(
op_bytes = 16;
goto simd_0f3a_common;
+case X86EMUL_OPC_66(0x0f3a, 0xce): /* gf2p8affineqb
$imm8,xmm/m128,xmm,xmm */
+case X86EMUL_OPC_VEX_66(0x0f3a, 0xce): /* vgf2p8affineqb
$imm8,{x,y}mm/mem,{x,y}mm,{x,y}mm */
+case X86EMUL_OPC_66(0x0f3a, 0xcf): /* gf2p8affineinvqb
$imm8,xmm/m128,xmm,xmm */
+case X86EMUL_OPC_VEX_66(0x0f3a, 0xcf): /* vgf2p8affineinvqb
$imm8,{x,y}mm/mem,{x,y}mm,{x,y}mm */
+host_and_vcpu_must_have(gfni);
+if ( vex.opcx == vex_none )
+goto simd_0f3a_common;
+generate_exception_if(vex.w, EXC_UD);
+goto simd_0f_imm8_avx;
+
case X86EMUL_OPC_66(0x0f3a, 0xdf): /* aeskeygenassist
$imm8,xmm/m128,xmm */
case X86EMUL_OPC_VEX_66(0x0f3a, 0xdf): /* vaeskeygenassist
$imm8,xmm/m128,xmm */
host_and_vcpu_must_have(aesni);
diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeature.h
index 84cc51d..9c43cd8 100644
--- a/xen/include/asm-x86/cpufeature.h
+++ b/xen/include/asm-x86/cpufeature.h
@@ -97,6 +97,9 @@
#define cpu_has_smapboot_cpu_has(X86_FEATURE_SMAP)
#define cpu_has_sha boot_cpu_has(X86_FEATURE_SHA)
+/* CPUID level 0x0007:0.ecx */
+#define cpu_has_gfniboot_cpu_has(X86_FEATURE_GFNI)
+
/* CPUID level 0x8007.edx */
#define cpu_has_itscboot_cpu_has(X86_FEATURE_ITSC)
--
1.9.1
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Re: [Xen-devel] [PATCH v4 1/4] x86emul: Support GFNI insns
>>> On 03.01.18 at 09:26, wrote:
> @@ -7741,6 +7752,16 @@ x86_emulate(
> op_bytes = 16;
> goto simd_0f3a_common;
>
> +case X86EMUL_OPC_66(0x0f3a, 0xce): /* gf2p8affineqb
> $imm8,xmm/m128,xmm,xmm */
> +case X86EMUL_OPC_VEX_66(0x0f3a, 0xce): /* vgf2p8affineqb
> $imm8,{x,y}mm/mem,{x,y}mm,{x,y}mm */
> +case X86EMUL_OPC_66(0x0f3a, 0xcf): /* gf2p8affineinvqb
> $imm8,xmm/m128,xmm,xmm */
> +case X86EMUL_OPC_VEX_66(0x0f3a, 0xcf): /* vgf2p8affineinvqb
> $imm8,{x,y}mm/mem,{x,y}mm,{x,y}mm */
> +host_and_vcpu_must_have(gfni);
> +if ( vex.opcx == vex_none )
> +goto simd_0f3a_common;
> +generate_exception_if(vex.w, EXC_UD);
The documentation says .W1, but I of course don't know whether
you meanwhile tested your code (you still don't add a test case)
and the doc is wrong, or this needs to be !vex.w.
Jan
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Re: [Xen-devel] [PATCH v4 1/4] x86emul: Support GFNI insns
On Wed, Jan 03, 2018 at 10:00:51AM -0700, Jan Beulich wrote:
> >>> On 03.01.18 at 09:26, wrote:
> > @@ -7741,6 +7752,16 @@ x86_emulate(
> > op_bytes = 16;
> > goto simd_0f3a_common;
> >
> > +case X86EMUL_OPC_66(0x0f3a, 0xce): /* gf2p8affineqb
> > $imm8,xmm/m128,xmm,xmm */
> > +case X86EMUL_OPC_VEX_66(0x0f3a, 0xce): /* vgf2p8affineqb
> > $imm8,{x,y}mm/mem,{x,y}mm,{x,y}mm */
> > +case X86EMUL_OPC_66(0x0f3a, 0xcf): /* gf2p8affineinvqb
> > $imm8,xmm/m128,xmm,xmm */
> > +case X86EMUL_OPC_VEX_66(0x0f3a, 0xcf): /* vgf2p8affineinvqb
> > $imm8,{x,y}mm/mem,{x,y}mm,{x,y}mm */
> > +host_and_vcpu_must_have(gfni);
> > +if ( vex.opcx == vex_none )
> > +goto simd_0f3a_common;
> > +generate_exception_if(vex.w, EXC_UD);
>
> The documentation says .W1, but I of course don't know whether
> you meanwhile tested your code (you still don't add a test case)
> and the doc is wrong, or this needs to be !vex.w.
>
Thanks Jan pointed out this issue, you are right!
vgf2p8affineqb and vgf2p8affineinvqb are W1, but vgf2p8mulb is W0.
So, for vgf2p8affineqb and vgf2p8affineinvqb, !vex.w is right.
for vgf2p8mulb vex.w is right.
As for the test case for those insns, i am writing those related test cases
in tools/tests/x86_emulator.
How many test cases will you need ? One test case for one CPU
feature(vaes,gfni and vpclmulqdq)？
Another issue is would you please share your test guide? i will verify those
insns on my simics enviornment.
thanks a lot!
Yang
> Jan
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Re: [Xen-devel] [PATCH v4 1/4] x86emul: Support GFNI insns
>>> On 04.01.18 at 10:20, wrote: > As for the test case for those insns, i am writing those related test > cases in tools/tests/x86_emulator. > > How many test cases will you need ? One test case for one CPU > feature(vaes,gfni and vpclmulqdq)？ My rule of thumb is that I'd like to have tests for everything that isn't fully matching "default" behavior of insn groups. That includes (but is not limited to) unusual encoding or unusual memory operand sizes. Therefore I think VAES and maybe also VPCLMULQDQ don't strictly need individual tests (I still have on my todo list an entry to create a blowfish-like test for AES and SHA, but that's independent of what I'd like you to do), but the unusual .W1 encoding of some of the GFNI insns certainly warrants one (whether that would be an individual insn test or a blowfish-like one I'd leave to you). But please realize that I'm writing this without having looked at the latest version of the other two patches yet, so my opinion regarding the former two may change once I get to that. > Another issue is would you please share your test guide? I'm afraid I don't understand "test guide". Jan ___ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel
