Re: [PATCH] Set RADEON_GEM_NO_CPU_ACCESS flag for BOs which don't need CPU access

[Alex Deucher]

On Thu, Jan 28, 2016 at 4:34 AM, Michel Dänzer  wrote:
> From: Michel Dänzer 
>
> Failing to do this was resulting in the kernel driver unnecessarily
> leaving open the possibility of CPU access to those BOs.
>
> Signed-off-by: Michel Dänzer 

Reviewed-by: Alex Deucher 

> ---
>  src/drmmode_display.c  | 6 --
>  src/radeon.h   | 4 
>  src/radeon_bo_helper.c | 7 +--
>  src/radeon_kms.c   | 3 ++-
>  4 files changed, 15 insertions(+), 5 deletions(-)
>
> diff --git a/src/drmmode_display.c b/src/drmmode_display.c
> index 0424dbd..14f6a55 100644
> --- a/src/drmmode_display.c
> +++ b/src/drmmode_display.c
> @@ -549,7 +549,8 @@ drmmode_crtc_scanout_allocate(xf86CrtcPtr crtc,
> size = RADEON_ALIGN(rotate_pitch * aligned_height, 
> RADEON_GPU_PAGE_SIZE);
>
> scanout->bo = radeon_bo_open(drmmode->bufmgr, 0, size, base_align,
> -RADEON_GEM_DOMAIN_VRAM, 0);
> +RADEON_GEM_DOMAIN_VRAM,
> +RADEON_GEM_NO_CPU_ACCESS);
> if (scanout->bo == NULL)
> return NULL;
>
> @@ -1917,7 +1918,8 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, 
> int height)
> info->front_bo = radeon_bo_open(info->bufmgr, 0, screen_size, 
> base_align,
> info->shadow_primary ?
> RADEON_GEM_DOMAIN_GTT :
> -   RADEON_GEM_DOMAIN_VRAM, 0);
> +   RADEON_GEM_DOMAIN_VRAM,
> +   tiling_flags ? 
> RADEON_GEM_NO_CPU_ACCESS : 0);
> if (!info->front_bo)
> goto fail;
>
> diff --git a/src/radeon.h b/src/radeon.h
> index 0ee6adc..5cec12b 100644
> --- a/src/radeon.h
> +++ b/src/radeon.h
> @@ -66,6 +66,10 @@
>  #include "xf86drm.h"
>  #include "radeon_drm.h"
>
> +#ifndef RADEON_GEM_NO_CPU_ACCESS
> +#define RADEON_GEM_NO_CPU_ACCESS   (1 << 4)
> +#endif
> +
>  #ifdef DAMAGE
>  #include "damage.h"
>  #include "globals.h"
> diff --git a/src/radeon_bo_helper.c b/src/radeon_bo_helper.c
> index ce964e0..531bc45 100644
> --- a/src/radeon_bo_helper.c
> +++ b/src/radeon_bo_helper.c
> @@ -74,7 +74,7 @@ radeon_alloc_pixmap_bo(ScrnInfoPtr pScrn, int width, int 
> height, int depth,
>  int pitch, base_align;
>  uint32_t size, heighta;
>  int cpp = bitsPerPixel / 8;
> -uint32_t tiling = 0;
> +uint32_t tiling = 0, flags = 0;
>  struct radeon_surface surface;
>  struct radeon_bo *bo;
>  int domain = RADEON_GEM_DOMAIN_VRAM;
> @@ -181,8 +181,11 @@ radeon_alloc_pixmap_bo(ScrnInfoPtr pScrn, int width, int 
> height, int depth,
> }
> }
>
> +if (tiling)
> +   flags |= RADEON_GEM_NO_CPU_ACCESS;
> +
>  bo = radeon_bo_open(info->bufmgr, 0, size, base_align,
> -   domain, 0);
> +   domain, flags);
>
>  if (bo && tiling && radeon_bo_set_tiling(bo, tiling, pitch) == 0)
> *new_tiling = tiling;
> diff --git a/src/radeon_kms.c b/src/radeon_kms.c
> index 971f11c..38f5c4e 100644
> --- a/src/radeon_kms.c
> +++ b/src/radeon_kms.c
> @@ -1981,7 +1981,8 @@ static Bool radeon_setup_kernel_mem(ScreenPtr pScreen)
>  base_align,
>  info->shadow_primary ?
>  RADEON_GEM_DOMAIN_GTT :
> -RADEON_GEM_DOMAIN_VRAM, 0);
> +RADEON_GEM_DOMAIN_VRAM,
> +tiling_flags ? 
> RADEON_GEM_NO_CPU_ACCESS : 0);
>  if (info->r600_shadow_fb == TRUE) {
>  if (radeon_bo_map(info->front_bo, 1)) {
>  ErrorF("Failed to map cursor buffer memory\n");
> --
> 2.7.0
>
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[PATCH] Set RADEON_GEM_NO_CPU_ACCESS flag for BOs which don't need CPU access

[Michel Dänzer]

From: Michel Dänzer 

Failing to do this was resulting in the kernel driver unnecessarily
leaving open the possibility of CPU access to those BOs.

Signed-off-by: Michel Dänzer 
---
 src/drmmode_display.c  | 6 --
 src/radeon.h   | 4 
 src/radeon_bo_helper.c | 7 +--
 src/radeon_kms.c   | 3 ++-
 4 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index 0424dbd..14f6a55 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -549,7 +549,8 @@ drmmode_crtc_scanout_allocate(xf86CrtcPtr crtc,
size = RADEON_ALIGN(rotate_pitch * aligned_height, 
RADEON_GPU_PAGE_SIZE);
 
scanout->bo = radeon_bo_open(drmmode->bufmgr, 0, size, base_align,
-RADEON_GEM_DOMAIN_VRAM, 0);
+RADEON_GEM_DOMAIN_VRAM,
+RADEON_GEM_NO_CPU_ACCESS);
if (scanout->bo == NULL)
return NULL;
 
@@ -1917,7 +1918,8 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int 
height)
info->front_bo = radeon_bo_open(info->bufmgr, 0, screen_size, 
base_align,
info->shadow_primary ?
RADEON_GEM_DOMAIN_GTT :
-   RADEON_GEM_DOMAIN_VRAM, 0);
+   RADEON_GEM_DOMAIN_VRAM,
+   tiling_flags ? RADEON_GEM_NO_CPU_ACCESS 
: 0);
if (!info->front_bo)
goto fail;
 
diff --git a/src/radeon.h b/src/radeon.h
index 0ee6adc..5cec12b 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -66,6 +66,10 @@
 #include "xf86drm.h"
 #include "radeon_drm.h"
 
+#ifndef RADEON_GEM_NO_CPU_ACCESS
+#define RADEON_GEM_NO_CPU_ACCESS   (1 << 4)
+#endif
+
 #ifdef DAMAGE
 #include "damage.h"
 #include "globals.h"
diff --git a/src/radeon_bo_helper.c b/src/radeon_bo_helper.c
index ce964e0..531bc45 100644
--- a/src/radeon_bo_helper.c
+++ b/src/radeon_bo_helper.c
@@ -74,7 +74,7 @@ radeon_alloc_pixmap_bo(ScrnInfoPtr pScrn, int width, int 
height, int depth,
 int pitch, base_align;
 uint32_t size, heighta;
 int cpp = bitsPerPixel / 8;
-uint32_t tiling = 0;
+uint32_t tiling = 0, flags = 0;
 struct radeon_surface surface;
 struct radeon_bo *bo;
 int domain = RADEON_GEM_DOMAIN_VRAM;
@@ -181,8 +181,11 @@ radeon_alloc_pixmap_bo(ScrnInfoPtr pScrn, int width, int 
height, int depth,
}
}
 
+if (tiling)
+   flags |= RADEON_GEM_NO_CPU_ACCESS;
+
 bo = radeon_bo_open(info->bufmgr, 0, size, base_align,
-   domain, 0);
+   domain, flags);
 
 if (bo && tiling && radeon_bo_set_tiling(bo, tiling, pitch) == 0)
*new_tiling = tiling;
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index 971f11c..38f5c4e 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -1981,7 +1981,8 @@ static Bool radeon_setup_kernel_mem(ScreenPtr pScreen)
 base_align,
 info->shadow_primary ?
 RADEON_GEM_DOMAIN_GTT :
-RADEON_GEM_DOMAIN_VRAM, 0);
+RADEON_GEM_DOMAIN_VRAM,
+tiling_flags ? 
RADEON_GEM_NO_CPU_ACCESS : 0);
 if (info->r600_shadow_fb == TRUE) {
 if (radeon_bo_map(info->front_bo, 1)) {
 ErrorF("Failed to map cursor buffer memory\n");
-- 
2.7.0

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