Re: [Xpert]Flushing CPU write cache
On Mon, 12 Nov 2001, Eugene M. Kim wrote: > > > > Any load or store on uncached memory (like the graphics accelerator's > > registers) will flush it. > > > > Any locked atomic RMW instruction (xchgl). > > > > Any port IO (write 0x3D0 or other unused port address. Expensive). > > Thank you for the information. I also read about these in the IA-32 > documentation, and supposed there would be no problem because in order > to initiate the blit we have to tell the GC through the memory-mapped > I/O range (uncached). However it didn't work out as expected, and the > same Intel documentation also said serializing instructions would not > push data out of the write cache to the external memory, so I was > wondering if there were some other ways. > Perhaps the problem isn't what you think it is. The i810 driver doesn't seem to have any problems with this and I believe its DMA buffer is write combined. Mark. ___ Xpert mailing list [EMAIL PROTECTED] http://XFree86.Org/mailman/listinfo/xpert
Re: [Xpert]Flushing CPU write cache
On Mon, Nov 12, 2001 at 06:14:48PM -0800, Mark Vojkovich wrote: > > > On Mon, 12 Nov 2001, Eugene M. Kim wrote: > > > Greetings, > > > > Question: What would be the way for a driver to flush some data in the > > CPU write cache, preferably all the way down to physical memory through > > the memory controller, but at least to the memory controller? > > > > Background: I'm trying to add XAA color-expansion blit support to the > > i8xx driver. The hardware limitation dictates that the indirect (one- > > line-at-once) mode should be used. In order to do this, the driver > > lets the XAA common layer know the address of interim buffers, let them > > be filled, then issues the actual blit command to the i8xx hardware > > which reads and uses the buffer filled by the XAA common layer. > >I thought the i810 driver already supported this? I see > the code there to do it. Oh, this is a pet project of mine (I'm trying to write a driver on my own, partly as an exercise =p). > > > > > The interim buffer is allocated in the video memory mapped into the AGP > > aperture. The problem is that the aperture has write-combining turned > > on so that not all writes go directly back to memory, and this makes it > > possible that some data written by the XAA common layer is not flushed > > out of CPU-internal write cache and seen by the memory/graphics > > controller. Result: incomplete blit. > >All you need to do is flush the write combine cache. > > > > > So far, it seems that I have to use some x86 assembler instruction like > > CLCACHE (we can always assume a Pentium II or better processor, because > > the driver is for i8xx chipset =p), but I'd like to know if there are > > more elegant solutions. WBINVD seems impractical because 1) it flushes > > the entire cache so the performance penalty will be obvious and 2) > > WBINVD is a privileged instruction so we must to switch to kernel mode > > before we can use it (means even more performance penalty). > > > > Any load or store on uncached memory (like the graphics accelerator's > registers) will flush it. > > Any locked atomic RMW instruction (xchgl). > > Any port IO (write 0x3D0 or other unused port address. Expensive). Thank you for the information. I also read about these in the IA-32 documentation, and supposed there would be no problem because in order to initiate the blit we have to tell the GC through the memory-mapped I/O range (uncached). However it didn't work out as expected, and the same Intel documentation also said serializing instructions would not push data out of the write cache to the external memory, so I was wondering if there were some other ways. I'll give the problem some more thoughts... Regards, Eugene ___ Xpert mailing list [EMAIL PROTECTED] http://XFree86.Org/mailman/listinfo/xpert
Re: [Xpert]Flushing CPU write cache
On Mon, 12 Nov 2001, Eugene M. Kim wrote: > Greetings, > > Question: What would be the way for a driver to flush some data in the > CPU write cache, preferably all the way down to physical memory through > the memory controller, but at least to the memory controller? > > Background: I'm trying to add XAA color-expansion blit support to the > i8xx driver. The hardware limitation dictates that the indirect (one- > line-at-once) mode should be used. In order to do this, the driver > lets the XAA common layer know the address of interim buffers, let them > be filled, then issues the actual blit command to the i8xx hardware > which reads and uses the buffer filled by the XAA common layer. I thought the i810 driver already supported this? I see the code there to do it. > > The interim buffer is allocated in the video memory mapped into the AGP > aperture. The problem is that the aperture has write-combining turned > on so that not all writes go directly back to memory, and this makes it > possible that some data written by the XAA common layer is not flushed > out of CPU-internal write cache and seen by the memory/graphics > controller. Result: incomplete blit. All you need to do is flush the write combine cache. > > So far, it seems that I have to use some x86 assembler instruction like > CLCACHE (we can always assume a Pentium II or better processor, because > the driver is for i8xx chipset =p), but I'd like to know if there are > more elegant solutions. WBINVD seems impractical because 1) it flushes > the entire cache so the performance penalty will be obvious and 2) > WBINVD is a privileged instruction so we must to switch to kernel mode > before we can use it (means even more performance penalty). > Any load or store on uncached memory (like the graphics accelerator's registers) will flush it. Any locked atomic RMW instruction (xchgl). Any port IO (write 0x3D0 or other unused port address. Expensive). Mark. ___ Xpert mailing list [EMAIL PROTECTED] http://XFree86.Org/mailman/listinfo/xpert
