[clang] [llvm] [AArch64] Add -mlr-for-calls-only to replace the now removed -ffixed-x30 flag. (PR #98073)

@@ -3267,10 +3267,13 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters( InsertSEH(MIB, TII, MachineInstr::FrameSetup); } else { // The code when the pair of ZReg is not present MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc)); - if

[clang] [llvm] [AArch64] Add -mlr-for-calls-only to replace the now removed -ffixed-x30 flag. (PR #98073)

https://github.com/aemerson updated https://github.com/llvm/llvm-project/pull/98073 >From d7a8f55b0790b15060f73f188ce97c83fe75f62d Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Mon, 8 Jul 2024 10:09:06 -0700 Subject: [PATCH 1/3] [AArch64] Add -mlr-for-calls-only to replace the now

[clang] [llvm] [AArch64] Add -mlr-for-calls-only to replace the now removed -ffixed-x30 flag. (PR #98073)

@@ -3267,10 +3267,13 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters( InsertSEH(MIB, TII, MachineInstr::FrameSetup); } else { // The code when the pair of ZReg is not present MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc)); - if

[clang] [llvm] [AArch64] Add -mlr-for-calls-only to replace the now removed -ffixed-x30 flag. (PR #98073)

https://github.com/aemerson updated https://github.com/llvm/llvm-project/pull/98073 >From d7a8f55b0790b15060f73f188ce97c83fe75f62d Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Mon, 8 Jul 2024 10:09:06 -0700 Subject: [PATCH 1/2] [AArch64] Add -mlr-for-calls-only to replace the now

[clang] [llvm] Revert "[AArch64] Add support for -ffixed-x30" (PR #88019)

aemerson wrote: Candidate PR: https://github.com/llvm/llvm-project/pull/98073 https://github.com/llvm/llvm-project/pull/88019 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [AArch64] Add -mlr-for-calls-only to replace the now removed -ffixed-x30 flag. (PR #98073)

https://github.com/aemerson created https://github.com/llvm/llvm-project/pull/98073 This re-introduces the effective behaviour that was reverted in 7ad481e76c9bee5b9895ebfa0fdb52f31cb7de77. This time we're not using the same mechanism, exposing another reservation feature that prevents only

[clang] [llvm] Revert "[AArch64] Add support for -ffixed-x30" (PR #88019)

aemerson wrote: Ah, perfect. https://github.com/llvm/llvm-project/pull/88019 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Revert "[AArch64] Add support for -ffixed-x30" (PR #88019)

aemerson wrote: Ok, given that our only way to implement something like this is with the reserving mechanism, I'll just rename the `-ffixed-x30` to something like `-mno-allocate-lr` and keep the underlying cc1/target features the same? https://github.com/llvm/llvm-project/pull/88019

[clang] [llvm] Revert "[AArch64] Add support for -ffixed-x30" (PR #88019)

aemerson wrote: @efriedma-quic @francisvm Can we restore this change? We need this for security hardening purposes to prevent LR allocated for general uses. (There is also an issue with reserving LR in that AArch64's PEI doesn't add live-in flags for reserved regs, but I think we should fix

[clang] [Clang][AArch64] Expose compatible SVE intrinsics with only +sme (PR #95787)

@@ -17,7 +25,7 @@ // CPP-CHECK-NEXT:[[TMP1:%.*]] = shl nuw nsw i64 [[TMP0]], 4 // CPP-CHECK-NEXT:ret i64 [[TMP1]] // -uint64_t test_svcntb() +uint64_t test_svcntb(void) MODE_ATTR aemerson wrote: Why is that restriction there? We often run into

[clang] [llvm] [CLANG][LLVM][AArch64]Add SME2.1 intrinsics for MOVAZ tile to vector,… (PR #88499)

aemerson wrote: Reverse ping https://github.com/llvm/llvm-project/pull/88499 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [CLANG][LLVM][AArch64]Add SME2.1 intrinsics for MOVAZ array to vector (PR #88901)

aemerson wrote: Reverse ping https://github.com/llvm/llvm-project/pull/88901 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [CLANG][LLVM][AArch64]SME2.1 intrinsics for MOVAZ tile to 2/4 vectors (PR #88710)

aemerson wrote: Reverse ping https://github.com/llvm/llvm-project/pull/88710 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [CLANG][LLVM][AArch64]Add SME2.1 intrinsics for MOVAZ tile to vector,… (PR #88499)

aemerson wrote: Can #88901 #88710 and this be merged? https://github.com/llvm/llvm-project/pull/88499 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [CLANG][LLVM][AArch64]Add SME2.1 intrinsics for MOVAZ array to vector (PR #88901)

https://github.com/aemerson approved this pull request. https://github.com/llvm/llvm-project/pull/88901 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [CLANG][LLVM][AArch64]Add SME2.1 intrinsics for MOVAZ tile to vector,… (PR #88499)

https://github.com/aemerson approved this pull request. https://github.com/llvm/llvm-project/pull/88499 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [CLANG][LLVM][AArch64]SME2.1 intrinsics for MOVAZ tile to 2/4 vectors (PR #88710)

https://github.com/aemerson approved this pull request. LGTM unless others have comments. https://github.com/llvm/llvm-project/pull/88710 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[clang] [llvm] [CLANG][LLVM][AArch64]SME2.1 intrinsics for MOVAZ tile to 2/4 vectors (PR #88710)

@@ -674,3 +674,26 @@ let TargetGuard = "sme2" in { def SVLUTI2_LANE_ZT_X2 : Inst<"svluti2_lane_zt_{d}_x2", "2.di[i", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt_x2", [IsStreaming, IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_7>]>; def

[clang] [llvm] [CLANG][LLVM][AArch64]Add SME2.1 intrinsics for MOVAZ array to vector (PR #88901)

aemerson wrote: Same comment as https://github.com/llvm/llvm-project/pull/88710#discussion_r1624880487 https://github.com/llvm/llvm-project/pull/88901 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[clang] [llvm] [CLANG][LLVM][AArch64]Add SME2.1 intrinsics for MOVAZ tile to vector,… (PR #88499)

aemerson wrote: Same comment as https://github.com/llvm/llvm-project/pull/88710#discussion_r1624880487 https://github.com/llvm/llvm-project/pull/88499 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[clang] [llvm] [CLANG][LLVM][AArch64]SME2.1 intrinsics for MOVAZ tile to 2/4 vectors (PR #88710)

@@ -674,3 +674,26 @@ let TargetGuard = "sme2" in { def SVLUTI2_LANE_ZT_X2 : Inst<"svluti2_lane_zt_{d}_x2", "2.di[i", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt_x2", [IsStreaming, IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_7>]>; def

[clang] [Clang][AArch64] Generalise streaming mode checks for builtins. (PR #93802)

https://github.com/aemerson approved this pull request. LGTM with suggestion https://github.com/llvm/llvm-project/pull/93802 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang][AArch64] Generalise streaming mode checks for builtins. (PR #93802)

@@ -0,0 +1,51 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fsyntax-only -verify %s + +// REQUIRES: aarch64-registered-target + +#include +

[clang] [Clang][AArch64] Generalise streaming mode checks for builtins. (PR #93802)

https://github.com/aemerson edited https://github.com/llvm/llvm-project/pull/93802 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [AArch64][SME] Add intrinsics for multi-vector BFCLAMP (PR #93532)

aemerson wrote: You should just re-open the old PR instead of making a new one, or if the fix is trivial then just re-commit the change without a PR unless you need someone to review it. https://github.com/llvm/llvm-project/pull/93532 ___

[clang] [Clang][AArch64] Require SVE or SSVE for scalable types. (PR #91356)

https://github.com/aemerson approved this pull request. https://github.com/llvm/llvm-project/pull/91356 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] AArch64: add __builtin_arm_trap (PR #85054)

https://github.com/aemerson approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/85054 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[libc] [compiler-rt] [clang-tools-extra] [flang] [lldb] [llvm] [clang] [GlobalIsel] Combine select of binops (PR #76763)

Thorsten =?utf-8?q?Sch=C3=BCtt?= , Thorsten =?utf-8?q?Sch=C3=BCtt?= , Thorsten =?utf-8?q?Sch=C3=BCtt?= Message-ID: In-Reply-To: https://github.com/aemerson approved this pull request. https://github.com/llvm/llvm-project/pull/76763 ___ cfe-commits

[llvm] [clang-tools-extra] [clang] Add out-of-line-atomics support to GlobalISel (PR #74588)

https://github.com/aemerson commented: Not an expert on atomics, but why would we have a libcall for -O0 but not for O1 in the tests? https://github.com/llvm/llvm-project/pull/74588 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[clang] [clang-tools-extra] [llvm] Add out-of-line-atomics support to GlobalISel (PR #74588)

https://github.com/aemerson edited https://github.com/llvm/llvm-project/pull/74588 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang-tools-extra] [llvm] [clang] Add out-of-line-atomics support to GlobalISel (PR #74588)

@@ -765,6 +766,138 @@ llvm::createMemLibcall(MachineIRBuilder , MachineRegisterInfo , return LegalizerHelper::Legalized; } +static RTLIB::Libcall getOutlineAtomicLibcall(MachineInstr ) { + unsigned Opc = MI.getOpcode(); + auto = cast(MI); + auto = AtomicMI.getMMO(); +

[clang] d7ce580 - Add -fclang-abi-compat=latest to aarch64-sve-vector-init.cpp

Author: Amara Emerson Date: 2023-11-15T15:22:12-08:00 New Revision: d7ce58048a586157e709e2dca5f33dd4f41b087d URL: https://github.com/llvm/llvm-project/commit/d7ce58048a586157e709e2dca5f33dd4f41b087d DIFF: https://github.com/llvm/llvm-project/commit/d7ce58048a586157e709e2dca5f33dd4f41b087d.diff

[clang] 250d9c8 - [clang][SME][NFC] Add -fclang-abi-compat=latest to tests.

Author: Amara Emerson Date: 2023-11-15T14:12:52-08:00 New Revision: 250d9c86c201799755611c425ce6e02fb5867716 URL: https://github.com/llvm/llvm-project/commit/250d9c86c201799755611c425ce6e02fb5867716 DIFF: https://github.com/llvm/llvm-project/commit/250d9c86c201799755611c425ce6e02fb5867716.diff

[clang] f64802e - [Clang][AArch64][Darwin] Enable GlobalISel by default for Darwin ARM64 platforms.

Author: Amara Emerson Date: 2022-11-07T15:04:09-08:00 New Revision: f64802e8d3e9db299cad913ffcb734c8d35dc5f0 URL: https://github.com/llvm/llvm-project/commit/f64802e8d3e9db299cad913ffcb734c8d35dc5f0 DIFF: https://github.com/llvm/llvm-project/commit/f64802e8d3e9db299cad913ffcb734c8d35dc5f0.diff

[clang] 66af90b - [darwin][driver] Pass through -global-isel LLVM flags to ld.

Author: Amara Emerson Date: 2021-03-22T17:23:06-07:00 New Revision: 66af90b46e1fe395806474dde2d49b8dc78bae1a URL: https://github.com/llvm/llvm-project/commit/66af90b46e1fe395806474dde2d49b8dc78bae1a DIFF: https://github.com/llvm/llvm-project/commit/66af90b46e1fe395806474dde2d49b8dc78bae1a.diff

[clang] 3c7e8d6 - Fix sdk version test to use 99.99.99 as a max dummy version instead of 10.99.99.

Author: Amara Emerson Date: 2020-07-06T16:53:12-07:00 New Revision: 3c7e8d6d0eb0660fb8fbae98c3e49ca059943416 URL: https://github.com/llvm/llvm-project/commit/3c7e8d6d0eb0660fb8fbae98c3e49ca059943416 DIFF: https://github.com/llvm/llvm-project/commit/3c7e8d6d0eb0660fb8fbae98c3e49ca059943416.diff

[clang] 7f1ea92 - Add a new -fglobal-isel option and make -fexperimental-isel an alias for it.

Author: Amara Emerson Date: 2020-03-31T12:06:11-07:00 New Revision: 7f1ea924c695f3293ff48f662cd1ec5f44bc1ab6 URL: https://github.com/llvm/llvm-project/commit/7f1ea924c695f3293ff48f662cd1ec5f44bc1ab6 DIFF: https://github.com/llvm/llvm-project/commit/7f1ea924c695f3293ff48f662cd1ec5f44bc1ab6.diff

Re: r366123 - ARM MTE stack sanitizer.

Hi Evgeniy, This commit looks like it broke the lldb bot: http://green.lab.llvm.org/green/job/lldb-cmake/31011/ Can you take a look? Amara > On Jul 15, 2019, at 1:02 PM, Evgeniy Stepanov via cfe-commits > wrote: > > Author: eugenis >

r360483 - [Darwin] Introduce a new flag, -fapple-link-rtlib that forces linking of the builtins library.

Author: aemerson Date: Fri May 10 16:24:20 2019 New Revision: 360483 URL: http://llvm.org/viewvc/llvm-project?rev=360483=rev Log: [Darwin] Introduce a new flag, -fapple-link-rtlib that forces linking of the builtins library. This driver flag is useful when users want to link against the

r356722 - [AArch64] Split the neon.addp intrinsic into integer and fp variants.

Author: aemerson Date: Thu Mar 21 15:31:37 2019 New Revision: 356722 URL: http://llvm.org/viewvc/llvm-project?rev=356722=rev Log: [AArch64] Split the neon.addp intrinsic into integer and fp variants. This is the result of discussions on the list about how to deal with intrinsics which require

[clang-tools-extra] r351100 - Revert r351051 "[clangd] Unlink VFS working dir from OS working dir."

Author: aemerson Date: Mon Jan 14 10:59:17 2019 New Revision: 351100 URL: http://llvm.org/viewvc/llvm-project?rev=351100=rev Log: Revert r351051 "[clangd] Unlink VFS working dir from OS working dir." The llvm commit r351050 broke some bots and was reverted. Modified:

Re: [clang-tools-extra] r350847 - [clangd] Introduce loading of shards within auto-index

Hi Kadir, It seems this commit started causing failures on builds in green dragon, starting from: http://green.lab.llvm.org/green/job/clang-stage1-configure-RA/52811/ Can you please take a look, and revert if the fix

Re: r332885 - CodeGen, Driver: Start using direct split dwarf emission in clang.

> On 21 May 2018, at 21:31, Peter Collingbourne via cfe-commits > wrote: > > Author: pcc > Date: Mon May 21 13:31:59 2018 > New Revision: 332885 > > URL: http://llvm.org/viewvc/llvm-project?rev=332885=rev > Log: > CodeGen, Driver: Start using direct split dwarf

r332971 - Revert "Add missing x86-registered-target."

Author: aemerson Date: Tue May 22 04:18:43 2018 New Revision: 332971 URL: http://llvm.org/viewvc/llvm-project?rev=332971=rev Log: Revert "Add missing x86-registered-target." This reverts commit r332911, as a dependency to revert r332885. Modified: cfe/trunk/test/Misc/cc1as-split-dwarf.s

r332973 - Revert "CodeGen, Driver: Start using direct split dwarf emission in clang."

Author: aemerson Date: Tue May 22 04:18:58 2018 New Revision: 332973 URL: http://llvm.org/viewvc/llvm-project?rev=332973=rev Log: Revert "CodeGen, Driver: Start using direct split dwarf emission in clang." This reverts commit r332885 as it broke several greendragon buildbots. Removed:

r332972 - Revert "Fix another make_unique ambiguity."

Author: aemerson Date: Tue May 22 04:18:49 2018 New Revision: 332972 URL: http://llvm.org/viewvc/llvm-project?rev=332972=rev Log: Revert "Fix another make_unique ambiguity." This reverts commit r332906 as a dependency to revert r332885. Modified: cfe/trunk/lib/CodeGen/BackendUtil.cpp

Re: r332720 - Move #include manipulation code to new lib/Tooling/Inclusions.

Hi Eric, Green dragon buildbots have started failing too, e.g.: http://green.lab.llvm.org/green/job/clang-stage2-Rthinlto/10222/ If you don’t have a quick fix can you please revert it. Thanks, Amara > On May 18, 2018, at 7:46 PM, Eric Liu wrote: > > Hi Vedant, > > It

r323485 - [Driver] Add an -fexperimental-isel driver option to enable/disable GlobalISel.

Author: aemerson Date: Thu Jan 25 16:27:22 2018 New Revision: 323485 URL: http://llvm.org/viewvc/llvm-project?rev=323485=rev Log: [Driver] Add an -fexperimental-isel driver option to enable/disable GlobalISel. Differential Revision: https://reviews.llvm.org/D42276 Added:

r307919 - [AArch64] Add support for handling the +sve target feature.

Author: aemerson Date: Thu Jul 13 08:36:01 2017 New Revision: 307919 URL: http://llvm.org/viewvc/llvm-project?rev=307919=rev Log: [AArch64] Add support for handling the +sve target feature. This also adds the appropriate predefine for SVE if enabled. Differential Revision:

r286456 - Add the loop end location to the loop metadata. This additional information

Author: aemerson Date: Thu Nov 10 08:44:30 2016 New Revision: 286456 URL: http://llvm.org/viewvc/llvm-project?rev=286456=rev Log: Add the loop end location to the loop metadata. This additional information can be used to improve the locations when generating remarks for loops. Depends on the