4vtomat wrote:
moved to the new [one](https://github.com/llvm/llvm-project/pull/74213)
https://github.com/llvm/llvm-project/pull/69000
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4vtomat wrote:
> Do we need to add the "experimental" feature to RISCVFeatures.td? If the
> feature string shows up in the function attributes, won't the backend print
> that it doesn't recognize the feature name when it parses the string?
Yes, we do, I forgot it lol~
https://github.com/llvm/
4vtomat wrote:
This update add "experimental" to `RISCVFeatures.td`, also add a member
variable `HasExperimental` to record whether the target has this feature.
https://github.com/llvm/llvm-project/pull/69000
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https://github.com/llvm/llvm-project/pull/69559
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https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/66860
>From a43d20450eef2d41e88ab867de2656e2fd9631b7 Mon Sep 17 00:00:00 2001
From: 4vtomat
Date: Tue, 19 Sep 2023 23:06:01 -0700
Subject: [PATCH 1/3] [RISCV] Fix wrong implication for zvknhb.
---
clang/include/clang
https://github.com/4vtomat closed
https://github.com/llvm/llvm-project/pull/66860
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https://github.com/llvm/llvm-project/pull/68296
>From 625c45da9928c3da295bba28708c992a42f3cd52 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Wed, 4 Oct 2023 10:23:52 -0700
Subject: [PATCH] [RISCV][SiFive] Support Xsfvfwmaccqqq extensions
Bfloat16 Matrix Mul
https://github.com/4vtomat closed
https://github.com/llvm/llvm-project/pull/68296
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4vtomat wrote:
Good catch！
LGTM, leave final decision to others~
https://github.com/llvm/llvm-project/pull/71140
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4vtomat wrote:
> > Since it's possible that **ISA spec** and **intrinsics spec** are not
> > synchronized, so the updates add an dummy extension called
> > **zexperimental**, once `-menable-experimental-extensions` is specified,
> > the feature `zexperimental` is automatically added.
> > If `l
@@ -106,6 +106,8 @@ static const RISCVSupportedExtension SupportedExtensions[]
= {
{"zdinx", RISCVExtensionVersion{1, 0}},
+{"zexperimental", RISCVExtensionVersion{1, 0}},
+
4vtomat wrote:
No, we don't~
https://github.com/llvm/llvm-project/pull/690
4vtomat wrote:
ping
https://github.com/llvm/llvm-project/pull/69559
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4vtomat wrote:
ping
https://github.com/llvm/llvm-project/pull/66860
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4vtomat wrote:
ping
https://github.com/llvm/llvm-project/pull/68296
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4vtomat wrote:
ping
https://github.com/llvm/llvm-project/pull/68297
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4vtomat wrote:
Since it's possible that **ISA spec** and **intrinsics spec** are not
synchronized, so the updates add an dummy extension called **zexperimental**,
once `-menable-experimental-extensions` is specified, the feature
`zexperimental` is automatically added.
If specifying `let Requir
https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/77487
This patch optimize:
1. Reduce string size of RVVIntrinsicDef.
2. Reduce the type size of the index of intrinsics.
I use valgrind --tool=massif to analyze a simple program:
```
#include
vint32m1_t test(vint3
4vtomat wrote:
> Thanks for the patch, some very quick feedback and I'd highlight the first
> bullet as the most important, as this is potentially a blocker for graduating
> these extensions from experimental.
>
> * My big concern with this would be the intrinsics - could you please comment
>
@@ -558,6 +558,12 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI,
uint64_t &Size,
"XTHeadVdot custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfvcp, DecoderTableXSfvcp32,
"SiFive VCIX custo
@@ -476,6 +524,31 @@ class GetFTypeInfo {
!eq(Scalar, f64) : "FPR64");
}
+multiclass VPatVMACC info_pairs, ValueType vec_m1> {
+ foreach pair = info_pairs in {
+defvar VdInfo = pair.Wti;
+defvar Vs2Info = pair.Vti;
+let Predicates = [
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@@ -450,6 +474,18 @@ multiclass VPatVC_XVV;
+ // Add another patterns for float type return value.
+ if !ne(wti.SEW, 8) then {
+defvar wfti = !cast("VF"#wti.SEW#wti.LMul.MX);
4vtomat wrote:
Yes, I'll add some tests for it~
https://github.com/llvm/llvm-proj
@@ -450,6 +474,18 @@ multiclass VPatVC_XVV;
+ // Add another patterns for float type return value.
+ if !ne(wti.SEW, 8) then {
+defvar wfti = !cast("VF"#wti.SEW#wti.LMul.MX);
4vtomat wrote:
Do you think test cases all of combination of vector type arguments
https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/73765
Extend the multi-lib re-use selection mechanism for RISC-V.
This funciton will try to re-use multi-lib if they are compatible.
Definition of compatible:
- ABI must be the same.
- multi-lib is a subset of curre
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/73765
>From c406872192d75c92dedd13d1afc36e7b5d71ccca Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Wed, 29 Nov 2023 00:27:25 -0800
Subject: [PATCH] [RISCV] Implement multi-lib reuse rule for RISC-V bare-metal
toolch
@@ -1715,6 +1716,129 @@ static void findCSKYMultilibs(const Driver &D, const
llvm::Triple &TargetTriple,
Result.Multilibs = CSKYMultilibs;
}
+/// Extend the multi-lib re-use selection mechanism for RISC-V.
+/// This funciton will try to re-use multi-lib if they are compat
@@ -1715,6 +1716,129 @@ static void findCSKYMultilibs(const Driver &D, const
llvm::Triple &TargetTriple,
Result.Multilibs = CSKYMultilibs;
}
+/// Extend the multi-lib re-use selection mechanism for RISC-V.
+/// This funciton will try to re-use multi-lib if they are compat
@@ -1715,6 +1716,129 @@ static void findCSKYMultilibs(const Driver &D, const
llvm::Triple &TargetTriple,
Result.Multilibs = CSKYMultilibs;
}
+/// Extend the multi-lib re-use selection mechanism for RISC-V.
+/// This funciton will try to re-use multi-lib if they are compat
@@ -1715,6 +1716,129 @@ static void findCSKYMultilibs(const Driver &D, const
llvm::Triple &TargetTriple,
Result.Multilibs = CSKYMultilibs;
}
+/// Extend the multi-lib re-use selection mechanism for RISC-V.
+/// This funciton will try to re-use multi-lib if they are compat
@@ -0,0 +1,86 @@
+// Test case for scanning input of GCC output as multilib config
4vtomat wrote:
No we don't use gcc, it's a copy mistake from downstream lol~
https://github.com/llvm/llvm-project/pull/73765
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https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/73765
>From 0c5f7497a8ce41695cba8f16a9402d74e4f798ea Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Wed, 29 Nov 2023 00:27:25 -0800
Subject: [PATCH 1/2] [RISCV] Implement multi-lib reuse rule for RISC-V
bare-metal to
4vtomat wrote:
Resolved the comments and also modified the commit messages.
https://github.com/llvm/llvm-project/pull/73765
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>From 320061a69ed129947eab1097d6308af434134a35 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Wed, 29 Nov 2023 00:27:25 -0800
Subject: [PATCH 1/3] [RISCV] Implement multi-lib reuse rule for RISC-V
bare-metal to
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/73765
>From 320061a69ed129947eab1097d6308af434134a35 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Wed, 29 Nov 2023 00:27:25 -0800
Subject: [PATCH 1/3] [RISCV] Implement multi-lib reuse rule for RISC-V
bare-metal to
https://github.com/4vtomat closed
https://github.com/llvm/llvm-project/pull/73765
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https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/75890
Extend the multi-lib re-use selection mechanism for RISC-V.
This funciton will try to re-use multi-lib if they are compatible.
Definition of compatible:
- ABI must be the same.
- multi-lib is a subset of curre
@@ -121,38 +121,36 @@ entry:
declare
@llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv64i8(
,
,
- ,
+ ,
iXLen, iXLen);
-define @intrinsic_vqmaccus_4x8x4_tu_i32m8( %0, %1, %2, iXLen %3) nounwind {
+define @intrinsic_vqmaccus_4x8x4_tu_i32m8( %0, %1, %2, iXLen %
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/75890
>From 3f4a4f10ed75cb0b0f937129b2372184ac34849d Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Mon, 18 Dec 2023 15:52:14 +0800
Subject: [PATCH 1/2] Recommit [RISCV] Implement multi-lib reuse rule for
RISC-V bare
https://github.com/4vtomat closed
https://github.com/llvm/llvm-project/pull/75890
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@@ -349,16 +349,24 @@ multiclass VPseudoSiFiveVMACC;
}
-multiclass VPseudoSiFiveVQMACC {
+multiclass VPseudoSiFiveVQMACCDOD {
foreach m = MxListVF8 in
let VLMul = m.value in
defm NAME : VPseudoSiFiveVMACC;
}
+multiclass VPseudoSiFiveVQMACCQOQ {
+ foreach i = [0
@@ -349,16 +349,24 @@ multiclass VPseudoSiFiveVMACC;
}
-multiclass VPseudoSiFiveVQMACC {
+multiclass VPseudoSiFiveVQMACCDOD {
foreach m = MxListVF8 in
let VLMul = m.value in
defm NAME : VPseudoSiFiveVMACC;
}
+multiclass VPseudoSiFiveVQMACCQOQ {
+ foreach i = [0
@@ -553,29 +560,40 @@ class GetFTypeInfo {
}
multiclass VPatVMACC info_pairs, ValueType vec_m1> {
+ list info_pairs, ValueType vec_m1,
+ bit lmul_follows_vd = 0> {
4vtomat wrote:
Oh, that's right.
https://github.com/ll
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@@ -8927,8 +8927,13 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) {
}
}
- if (T->isRVVSizelessBuiltinType())
-checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext));
+ if (T->isRVVSizelessBuiltinType() && isa(CurContext)) {
+const FunctionD
https://github.com/4vtomat edited
https://github.com/llvm/llvm-project/pull/83674
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@@ -8927,8 +8927,13 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) {
}
}
- if (T->isRVVSizelessBuiltinType())
-checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext));
+ if (T->isRVVSizelessBuiltinType() && isa(CurContext)) {
+const FunctionD
@@ -36,6 +36,11 @@ struct RISCVSupportedExtension {
}
};
+struct RISCVProfile {
4vtomat wrote:
Very minor too, if you use std::pair, could you add the comments describing
what the fields represent?
https://github.com/llvm/llvm-project/pull/76357
_
@@ -854,6 +895,30 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+ Arch.starts_with("r
@@ -854,6 +895,30 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+ Arch.starts_with("r
@@ -8927,8 +8927,13 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) {
}
}
- if (T->isRVVSizelessBuiltinType())
-checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext));
+ if (T->isRVVSizelessBuiltinType() && isa(CurContext)) {
+const FunctionD
@@ -8927,8 +8927,13 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) {
}
}
- if (T->isRVVSizelessBuiltinType())
-checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext));
+ if (T->isRVVSizelessBuiltinType() && isa(CurContext)) {
+const FunctionD
@@ -8927,8 +8927,13 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) {
}
}
- if (T->isRVVSizelessBuiltinType())
-checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext));
+ if (T->isRVVSizelessBuiltinType() && isa(CurContext)) {
+const FunctionD
@@ -8927,8 +8927,13 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) {
}
}
- if (T->isRVVSizelessBuiltinType())
-checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext));
+ if (T->isRVVSizelessBuiltinType() && isa(CurContext)) {
+const FunctionD
4vtomat wrote:
Rebase
https://github.com/llvm/llvm-project/pull/77560
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4vtomat wrote:
ping
https://github.com/llvm/llvm-project/pull/77560
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https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/83553
Currently using the command `clang -cc1 -triple riscv64` to compile the
code below:
```
#include
void foo() {
vfloat64m1_t f64m1;
}
```
would get the error message "RISC-V type 'vfloat64m1_t' ... requires the
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/83553
>From 8ad3a883d29155dc26c79abdd57ea0f72d046dfc Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Fri, 1 Mar 2024 00:40:21 -0800
Subject: [PATCH 1/2] [clang][RISCV] Reorder sema check for RVV type
Currently using t
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/83553
>From 8ad3a883d29155dc26c79abdd57ea0f72d046dfc Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Fri, 1 Mar 2024 00:40:21 -0800
Subject: [PATCH 1/3] [clang][RISCV] Reorder sema check for RVV type
Currently using t
4vtomat wrote:
Maybe we can modify the current test case, it would get the error message
"RISC-V type 'vfloat64m1_t' ... requires the 'zve64x' extension", but should be
'zve64d' instead.
https://github.com/llvm/llvm-project/pull/83553
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https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/83674
It is currently not possible to use "RVV type" and "RVV intrinsics" if
the "zve32x" is not enabled globally. However in some cases we may want
to use them only in some functions, for instance:
```
#include
__att
4vtomat wrote:
Related request: https://github.com/riscv-non-isa/riscv-c-api-doc/issues/69
https://github.com/llvm/llvm-project/pull/83674
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4vtomat wrote:
> I tried compiling it and then got two warnings.
>
> ```
> llvm-project/clang/lib/CodeGen/CGDebugInfo.cpp:1408:11: warning: enumeration
> value 'CC_RISCVVectorCall' not handled in switch [-Wswitch]
> 1408 | switch (CC) {
> | ^~
> 1 warning generated.
> [3629/3
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/83674
>From f14c54cb7c3c31e84a78ddf33b932c4c74e20365 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Fri, 1 Mar 2024 09:52:35 -0800
Subject: [PATCH 1/2] [clang][RISCV] Enable RVV with function attribute
__attribute__(
https://github.com/4vtomat edited
https://github.com/llvm/llvm-project/pull/83674
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@@ -0,0 +1,41 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -S -verify %s
+
+// REQUIRES: riscv-registered-target
+#include
+
+void test_builtin() {
+ __riscv_vsetvl_e8m8(1); // expected-error {{'__builtin_r
@@ -463,7 +463,8 @@ ParsedTargetAttr RISCVTargetInfo::parseTargetAttr(StringRef
Features) const {
Ret.Duplicate = "tune=";
Ret.Tune = AttrString;
-}
+} else if (Feature.starts_with("+"))
4vtomat wrote:
Updated!
https://github.com/llvm/
@@ -8927,8 +8927,13 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) {
}
}
- if (T->isRVVSizelessBuiltinType())
-checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext));
+ if (T->isRVVSizelessBuiltinType() && isa(CurContext)) {
+const FunctionD
4vtomat wrote:
Rebase and squash
https://github.com/llvm/llvm-project/pull/77560
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https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/77560
>From 08371002a08d8958cd23eecb5ff3c5f2f2661c0e Mon Sep 17 00:00:00 2001
From: 4vtomat
Date: Wed, 22 Mar 2023 22:58:35 -0700
Subject: [PATCH] [RISCV] RISCV vector calling convention (1/2)
This is the vector calli
https://github.com/4vtomat closed
https://github.com/llvm/llvm-project/pull/77560
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https://github.com/4vtomat edited
https://github.com/llvm/llvm-project/pull/77560
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https://github.com/llvm/llvm-project/pull/83674
>From 10ab0fa16e62e44b8d04b372f20b95018f065048 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Fri, 1 Mar 2024 09:52:35 -0800
Subject: [PATCH 1/3] [clang][RISCV] Enable RVV with function attribute
__attribute__(
4vtomat wrote:
Rebase
https://github.com/llvm/llvm-project/pull/83674
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https://github.com/llvm/llvm-project/pull/83674
>From f14c54cb7c3c31e84a78ddf33b932c4c74e20365 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Fri, 1 Mar 2024 09:52:35 -0800
Subject: [PATCH 1/3] [clang][RISCV] Enable RVV with function attribute
__attribute__(
4vtomat wrote:
Move the test cases to existing files.
https://github.com/llvm/llvm-project/pull/83674
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https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/83989
If the "march" has some extension with version that is not supported, it
returns the error message like: "error: invalid arch name 'some_arch',
unsupported version number 2.0 for extension 'some_arch'", which is n
https://github.com/4vtomat closed
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>From 764c861931fd8013df5b144c2d789614bc952126 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Tue, 5 Mar 2024 02:28:10 -0800
Subject: [PATCH 1/2] [RISCV] Improve error message when the extension is not
supporte
4vtomat wrote:
> perhaps the llvm libSupport prats of this change should be unit tested in
> LLVM, rather than only tested indirectly in clang?
Good point, thanks!
I've added for unites.
https://github.com/llvm/llvm-project/pull/83989
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https://github.com/llvm/llvm-project/pull/83989
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https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/83674
>From faab3d0d9163e99185fb6a2d3efd21549ed33e00 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Fri, 1 Mar 2024 09:52:35 -0800
Subject: [PATCH 1/3] [clang][RISCV] Enable RVV with function attribute
__attribute__(
4vtomat wrote:
Rebase.
https://github.com/llvm/llvm-project/pull/83674
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@@ -3439,6 +3439,8 @@ StringRef FunctionType::getNameForCallConv(CallingConv
CC) {
case CC_PreserveAll: return "preserve_all";
case CC_M68kRTD: return "m68k_rtd";
case CC_PreserveNone: return "preserve_none";
+ case CC_RISCVVectorCall:
4vtomat wrote:
S
@@ -1883,6 +1883,12 @@ let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
def vfncvt_rtz_x_f_w : RVVConvToNarrowingSignedBuiltin<"vfncvt_rtz_x">;
def vfncvt_rod_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_rod_f">;
}
+
+// Zvfbfmin - Vector convert BF16 to FP32
+let Log2LMUL = [-
@@ -0,0 +1,479 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 4
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
+// RUN: -target-feature +zvfh -target-feat
@@ -1730,12 +1730,26 @@ let ManualCodegen = [{
defm vfwnmacc : RVVFloatingWidenTerBuiltinSetRoundingMode;
defm vfwmsac : RVVFloatingWidenTerBuiltinSetRoundingMode;
defm vfwnmsac : RVVFloatingWidenTerBuiltinSetRoundingMode;
+
+// Vector BF16 widening multiply-ac
https://github.com/4vtomat deleted
https://github.com/llvm/llvm-project/pull/79618
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@@ -1883,6 +1883,12 @@ let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
def vfncvt_rtz_x_f_w : RVVConvToNarrowingSignedBuiltin<"vfncvt_rtz_x">;
def vfncvt_rod_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_rod_f">;
}
+
+// Zvfbfmin - Vector convert BF16 to FP32
+let Log2LMUL = [-
https://github.com/4vtomat closed
https://github.com/llvm/llvm-project/pull/79618
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https://github.com/4vtomat closed
https://github.com/llvm/llvm-project/pull/79615
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4vtomat wrote:
The latest fixup commit add [[riscv::riscv_vector]] supports for C23 and C++11.
https://github.com/llvm/llvm-project/pull/77560
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4vtomat wrote:
Since it only reduces about 160 of 54100 intrinsics generated, I have no
opinion on this, just left the final decision to others~
But if this PR is finally decided to be merged, please add some comments around
the code you added to explain, thanks!
https://github.com/llvm/llvm-p
@@ -10,7 +10,8 @@
// CHECK-RV64-LABEL: @test_sf_vc_x_se_u64m1(
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT:call void @llvm.riscv.sf.vc.x.se.e64m1.i64.i64.i64(i64
3, i64 31, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[CONV:%.*]] = trunc i64 [[RS1
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/77487
>From 84ea759c43d8e9cb450d95d00fd802be622153a2 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Sun, 7 Jan 2024 18:10:59 -0800
Subject: [PATCH 1/2] [RISCV][clang] Optimize memory usage of intrinsic lookup
table
@@ -380,14 +380,14 @@ void RISCVIntrinsicManagerImpl::InitRVVIntrinsic(
OverloadedName += "_" + OverloadedSuffixStr.str();
// clang built-in function name, e.g. __builtin_rvv_vadd.
- std::string BuiltinName = "__builtin_rvv_" + std::string(Record.Name);
+ std::string B
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