https://github.com/androm3da closed
https://github.com/llvm/llvm-project/pull/98712
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https://github.com/llvm/llvm-project/pull/98712
>From 62c2ffac958ee5a235db254ad001875bb2980c1b Mon Sep 17 00:00:00 2001
From: Brian Cain
Date: Fri, 12 Jul 2024 21:34:56 -0700
Subject: [PATCH] [cmake] Add hexagon-linux cmake cache files
These can be used
https://github.com/androm3da updated
https://github.com/llvm/llvm-project/pull/98712
>From 8fab99299900ef7312dc0503d829bae99d67cd60 Mon Sep 17 00:00:00 2001
From: Brian Cain
Date: Fri, 12 Jul 2024 21:34:56 -0700
Subject: [PATCH] [cmake] Add hexagon-linux cmake cache files
These can be used
@@ -0,0 +1,25 @@
+
androm3da wrote:
Absolutely. That's been the status quo and this PR on its own can't change
that.
The intent of this pull req is to allow anyone to build a toolchain for
targeting hexagon (of which libc++, libc++abi, libunwind are a part).
androm3da wrote:
@ldionne please take a look when you get a chance. Thanks!
https://github.com/llvm/llvm-project/pull/98712
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On 9/16/2024 11:31 AM, Brian Cain wrote:
On 9/16/2024 11:05 AM, Brian Cain wrote:
On 9/16/2024 10:47 AM, Alex Bennée wrote:
Brian Cain writes:
On 9/16/2024 8:12 AM, Alex Bennée wrote:
Brian Cain writes:
On 9/6/2024 9:39 PM, Brian Cain wrote:
With newer clang builds (19.x), there
>free, so that that the memory is
properly cleaned when the object is finalized, but the former doesn't.
Fixes: e72a7f65c1 (hw: Move declaration of IRQState to header and add init
function)
Signed-off-by: Matheus Tavares Bernardino
Reviewed-by: BALATON Zoltan
---
Reviewed-by: Brian
TARGET_NR_listmount 458
+#define TARGET_NR_lsm_get_self_attr 459
+#define TARGET_NR_lsm_set_self_attr 460
+#define TARGET_NR_lsm_list_modules 461
+#define TARGET_NR_mseal 462
+#define TARGET_NR_syscalls 463
For hexagon system calls:
Reviewed-by: Brian Cain
Note for future updates that as of v6.11
On 9/17/2024 1:47 PM, Matheus Tavares Bernardino wrote:
At e72a7f65c1 (hw: Move declaration of IRQState to header and add init
function, 2024-06-29), we've changed qemu_allocate_irq() to use a
combination of g_new() + object_initialize() instead of
IRQ(object_new()). The latter sets obj->free,
https://github.com/androm3da updated
https://github.com/llvm/llvm-project/pull/98712
>From 3d8388d723b3c5dc3d51a6d3e80051dfe7da8a4c Mon Sep 17 00:00:00 2001
From: Brian Cain
Date: Fri, 12 Jul 2024 21:34:56 -0700
Subject: [PATCH] [cmake] Add hexagon-linux cmake cache files
These can be used
On 9/16/2024 11:05 AM, Brian Cain wrote:
On 9/16/2024 10:47 AM, Alex Bennée wrote:
Brian Cain writes:
On 9/16/2024 8:12 AM, Alex Bennée wrote:
Brian Cain writes:
On 9/6/2024 9:39 PM, Brian Cain wrote:
With newer clang builds (19.x), there's a warning for implicit
fun
On 9/16/2024 10:47 AM, Alex Bennée wrote:
Brian Cain writes:
On 9/16/2024 8:12 AM, Alex Bennée wrote:
Brian Cain writes:
On 9/6/2024 9:39 PM, Brian Cain wrote:
With newer clang builds (19.x), there's a warning for implicit function
declarations and it rejects linux-test.c.
On 9/16/2024 8:12 AM, Alex Bennée wrote:
Brian Cain writes:
On 9/6/2024 9:39 PM, Brian Cain wrote:
With newer clang builds (19.x), there's a warning for implicit function
declarations and it rejects linux-test.c.
glibc/musl's readdir64() declaration in dirent is
On 9/6/2024 9:39 PM, Brian Cain wrote:
With newer clang builds (19.x), there's a warning for implicit function
declarations and it rejects linux-test.c.
glibc/musl's readdir64() declaration in dirent is guarded by
_LARGEFILE64_SOURCE, so we'll define it to fix the warning
On 9/13/2024 9:30 PM, Brad Smith wrote:
On 2024-09-10 10:06 p.m., Brian Cain wrote:
On 9/10/2024 5:26 PM, Brad Smith wrote:
On 2024-09-10 4:17 p.m., Thomas Huth wrote:
Some systems (like OpenBSD) do not have the sha256sum or sha512sum
programs
installed by default. Use the Python hashlib
fixed grammar typo and s/use-after-frees/uses-after-free/
v1:
https://lore.kernel.org/qemu-devel/a788215960b94d863baeffb736f06e3fb94275e7.1726145226.git.quic_mathb...@quicinc.com/
Reviewed-by: Brian Cain
docs/devel/testing/fuzzing.rst | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
On 9/12/2024 7:47 AM, Matheus Tavares Bernardino wrote:
This options has been removed at cb771ac1f5 (meson: Split
--enable-sanitizers to --enable-{asan, ubsan}, 2024-08-13), so let's
update its last standing mention in the docs.
Signed-off-by: Matheus Tavares Bernardino
---
docs/devel/testi
androm3da wrote:
@ldionne I think you'll be satisfied with the changes I've made. Previously I
didn't think your feedback made sense, but I've come around 😉
https://github.com/llvm/llvm-project/pull/98712
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7;re named sha256 and sha512.
Rather than port the test to each OS's particular program names, we
should use the portable solution that's included w/Python.
Reported-by: Peter Maydell
Signed-off-by: Thomas Huth
---
Reviewed-by: Brian Cain
tests/functional/qem
"macros.inc" as "macros.h.inc".
Signed-off-by: Philippe Mathieu-Daudé
---
Reviewed-by: Brian Cain
target/hexagon/idef-parser/README.rst | 4 ++--
target/hexagon/idef-parser/{macros.inc => macros.h.inc} | 0
target/hexagon/gen_idef_parser_funcs.p
https://github.com/androm3da updated
https://github.com/llvm/llvm-project/pull/98712
>From 29554e6a090075993a67126880cfb9e5f93f28f4 Mon Sep 17 00:00:00 2001
From: Brian Cain
Date: Fri, 12 Jul 2024 21:34:56 -0700
Subject: [PATCH] [cmake] Add hexagon-linux cmake cache files
These can be used
https://github.com/androm3da closed
https://github.com/llvm/llvm-project/pull/107161
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de = readdir64(dir);
| ^
Signed-off-by: Brian Cain
---
tests/tcg/multiarch/linux/linux-test.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/tcg/multiarch/linux/linux-test.c
b/tests/tcg/multiarch/linux/linux-test.c
index 64f57cb287..4e0e862ad9 100644
--- a/tests/tcg/multiarch
).
Signed-off-by: Matheus Tavares Bernardino
---
Reviewed-by: Brian Cain
target/hexagon/cpu_bits.h| 15 ++-
target/hexagon/helper.h | 15 ++-
target/hexagon/mmvec/mmvec.h | 15 ++-
tests/tcg/hexagon
@@ -0,0 +1,25 @@
+
+set(LLVM_DEFAULT_TARGET_TRIPLE hexagon-unknown-linux-musl CACHE STRING "")
+set(LLVM_ENABLE_PER_TARGET_RUNTIME_DIR OFF CACHE BOOL "")
+set(LLVM_ENABLE_RUNTIMES libcxx;libcxxabi;libunwind;compiler-rt CACHE STRING
"")
+set(LIBCXX_INCLUDE_BENCHMARKS OFF CACHE BOO
https://github.com/androm3da updated
https://github.com/llvm/llvm-project/pull/98712
>From 29554e6a090075993a67126880cfb9e5f93f28f4 Mon Sep 17 00:00:00 2001
From: Brian Cain
Date: Fri, 12 Jul 2024 21:34:56 -0700
Subject: [PATCH] [cmake] Add hexagon-linux cmake cache files
These can be used
@@ -0,0 +1,25 @@
+
+set(LLVM_DEFAULT_TARGET_TRIPLE hexagon-unknown-linux-musl CACHE STRING "")
+set(LLVM_ENABLE_PER_TARGET_RUNTIME_DIR OFF CACHE BOOL "")
+set(LLVM_ENABLE_RUNTIMES libcxx;libcxxabi;libunwind;compiler-rt CACHE STRING
"")
+set(LIBCXX_INCLUDE_BENCHMARKS OFF CACHE BOO
androm3da wrote:
@SundeepKushwaha or @ronlieb could you review this PR? Should be
non-controversial I hope.
https://github.com/llvm/llvm-project/pull/107161
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@@ -0,0 +1,25 @@
+
+set(LLVM_DEFAULT_TARGET_TRIPLE hexagon-unknown-linux-musl CACHE STRING "")
+set(LLVM_ENABLE_PER_TARGET_RUNTIME_DIR OFF CACHE BOOL "")
+set(LLVM_ENABLE_RUNTIMES libcxx;libcxxabi;libunwind;compiler-rt CACHE STRING
"")
+set(LIBCXX_INCLUDE_BENCHMARKS OFF CACHE BOO
@@ -0,0 +1,25 @@
+
+set(LLVM_DEFAULT_TARGET_TRIPLE hexagon-unknown-linux-musl CACHE STRING "")
+set(LLVM_ENABLE_PER_TARGET_RUNTIME_DIR OFF CACHE BOOL "")
+set(LLVM_ENABLE_RUNTIMES libcxx;libcxxabi;libunwind;compiler-rt CACHE STRING
"")
+set(LIBCXX_INCLUDE_BENCHMARKS OFF CACHE BOO
https://github.com/androm3da updated
https://github.com/llvm/llvm-project/pull/98712
>From bca45b046e8b6092bfa44c01172ecfcad84758d7 Mon Sep 17 00:00:00 2001
From: Brian Cain
Date: Fri, 12 Jul 2024 21:34:56 -0700
Subject: [PATCH] [cmake] Add hexagon-linux cmake cache files
These can be used
@@ -0,0 +1,25 @@
+
+set(LLVM_DEFAULT_TARGET_TRIPLE hexagon-unknown-linux-musl CACHE STRING "")
androm3da wrote:
Hmm, so I already have `CMAKE_CXX_COMPILER_TARGET` set this way in
`hexagon-linux-cross.cmake` (I left this cache out of this PR but I could
include
@@ -0,0 +1,25 @@
+
+set(LLVM_DEFAULT_TARGET_TRIPLE hexagon-unknown-linux-musl CACHE STRING "")
+set(LLVM_ENABLE_PER_TARGET_RUNTIME_DIR OFF CACHE BOOL "")
+set(LLVM_ENABLE_RUNTIMES libcxx;libcxxabi;libunwind;compiler-rt CACHE STRING
"")
+set(LIBCXX_INCLUDE_BENCHMARKS OFF CACHE BOO
@@ -0,0 +1,25 @@
+
+set(LLVM_DEFAULT_TARGET_TRIPLE hexagon-unknown-linux-musl CACHE STRING "")
+set(LLVM_ENABLE_PER_TARGET_RUNTIME_DIR OFF CACHE BOOL "")
+set(LLVM_ENABLE_RUNTIMES libcxx;libcxxabi;libunwind;compiler-rt CACHE STRING
"")
+set(LIBCXX_INCLUDE_BENCHMARKS OFF CACHE BOO
@@ -0,0 +1,25 @@
+
+set(LLVM_DEFAULT_TARGET_TRIPLE hexagon-unknown-linux-musl CACHE STRING "")
androm3da wrote:
I'm willing to try that, it makes sense.
https://github.com/llvm/llvm-project/pull/98712
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androm3da wrote:
Note that this was the only source file from the original commit without the
correct header.
https://github.com/llvm/llvm-project/pull/107161
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I should have contributed
this file with the `Apache+LLVM exception` license.
>From b4705aa71a261e58930f08056d1fd79c6537a50d Mon Sep 17 00:00:00 2001
From: Brian Cain
Date: Tue, 3 Sep 2024 15:37:08 -0700
Subject: [PATCH] [clang, hexagon] Update copyright, license text
When this f
The values previously used for "HEX_EXCP_*" were the cause code
definitions and not the event numbers. So in this commit, we update
the names to reflect the cause codes. In HEX_EVENT_TRAP0's case, we add
a new "HEX_EVENT_*" with the correct event number.
Signed-off-b
Signed-off-by: Brian Cain
---
target/hexagon/cpu_bits.h | 22 ++
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h
index 2e60c0fafe..ff596e2a94 100644
--- a/target/hexagon/cpu_bits.h
+++ b/target/hexagon
Changes in v2:
* Fixed the HEX_EVENT_{INVALID*,PRIV*,etc} - several of these were actually
cause codes, just like TRAP0.
* I combined "Rename HEX_EXCP_ => HEX_EVENT_" and "rename
HEX_EVENT_TRAP0=>HEX_CAUSE_TRAP0"
into a single commit.
Brian Cain (2):
target
> -Original Message-
> From: Alex Bennée
> Sent: Tuesday, August 20, 2024 5:59 AM
> To: QEMU Developers
> Cc: Alessandro Di Federico ; Alistair Francis
> ; Anton Johansson ; Markus
> Armbruster ; Brian Cain ; Daniel P.
> Berrange ; Chao Peng ;
> c...@nvidi
.org; David S. Miller
> ; Andreas Larsson ;
> sparcli...@vger.kernel.org; Michael Ellerman ; Nicholas
> Piggin ; Christophe Leroy
> ; Naveen N . Rao
> ; linuxppc-dev@lists.ozlabs.org; Brian Cain
> ; linux-hexa...@vger.kernel.org; Guo Ren
> ; linux-c...@vger.kernel.org; Heiko Car
.org; David S. Miller
> ; Andreas Larsson ;
> sparcli...@vger.kernel.org; Michael Ellerman ; Nicholas
> Piggin ; Christophe Leroy
> ; Naveen N . Rao
> ; linuxppc-...@lists.ozlabs.org; Brian Cain
> ; linux-hexa...@vger.kernel.org; Guo Ren
> ; linux-csky@vger.kernel.org; Heiko Car
The value previously used for "HEX_EVENT_TRAP0" was the cause code
definition and not the event number. So in this commit, we update
the name to reflect the cause code and add a new "HEX_EVENT_TRAP0"
with the correct event number.
Signed-off-by: Brian Cain
---
target/he
Change the name of these definitions to reflect that they correspond
to the event code for the exception.
Signed-off-by: Brian Cain
---
linux-user/hexagon/cpu_loop.c | 4 ++--
target/hexagon/cpu.h | 2 +-
target/hexagon/cpu_bits.h | 14 +++---
target/hexagon/gen_tcg.h
Signed-off-by: Brian Cain
---
target/hexagon/cpu_bits.h | 22 ++
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h
index eec456d8f9..2454ef72bf 100644
--- a/target/hexagon/cpu_bits.h
+++ b/target/hexagon
androm3da wrote:
> @ldionne ping
@ldionne let me know if it would be helpful for me to decompose this change
into a smaller one that would be easier to review.
https://github.com/llvm/llvm-project/pull/98712
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https://github.com/androm3da updated
https://github.com/llvm/llvm-project/pull/103003
>From 2188e4b6b6dc257436f6d9086fe0b7205f8d512a Mon Sep 17 00:00:00 2001
From: Brian Cain
Date: Mon, 12 Aug 2024 20:07:08 -0500
Subject: [PATCH] [libc++] Use a different smart ptr type alias (#102089)
On 8/8/2024 5:39 PM, Richard Henderson wrote:
On 8/8/24 13:42, Brian Cain wrote:
The following changes since commit
4c395ac42e55ff8e9fd4c992e351a04b10785503:
Merge tag 'pull-tcg-20240808' of https://gitlab.com/rth7680/qemu
into staging (2024-08-08 09:07:00 +1000)
are availa
From: Anton Johansson
The self assignment is clearly useless, and @1.last_column does not have
to be set for an expression with only a single token, so remove it.
Reported-by: Peter Maydell
Signed-off-by: Anton Johansson
Reviewed-by: Brian Cain
Reviewed-by: Philippe Mathieu-Daudé
Message-Id
Predicate Registers:
p0 = 0x00
p1 = 0xff
p2 = 0x00
p3 = 0xff
Signed-off-by: Taylor Simpson
Reviewed-by: Brian Cain
Reviewed-by: Matheus Tavares Bernardino
Message-Id: <20240613182209.140082-1-ltaylorsimp...@gmail.com>
Signed-off-by: Brian Cain
---
gdb
_conv* fix
Anton Johansson (1):
target/hexagon/idef-parser: Remove self-assignment
Brian Cain (3):
MAINTAINERS: Add my hexagon git tree
target/hexagon: define a v66 CPU
target/hexagon: switch to dc set_props() list
Matheus Tavares Bernardino (1):
He
For now, v66 behavior is the same as other CPUs.
Signed-off-by: Brian Cain
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Taylor Simpson
---
target/hexagon/cpu-qom.h | 1 +
target/hexagon/cpu.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/target/hexagon/cpu-qom.h b/target
ed-by: Brian Cain
Reviewed-by: Taylor Simpson
Signed-off-by: Brian Cain
---
target/hexagon/op_helper.c | 18 +-
tests/tcg/hexagon/usr.c| 12 +++-
2 files changed, 20 insertions(+), 10 deletions(-)
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
Add my git tree for hexagon. Note that the branch is "hex-next" and not
"hex.next" as had been used previously. But I'll keep the "hex.next" branch
in sync with "hex-next" until this commit lands to avoid confusion.
Signed-off-by: Brian Cain
R
Define a hexagon_cpu_properties list to match the idiom used
by other targets.
Signed-off-by: Brian Cain
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Taylor Simpson
---
target/hexagon/cpu.c | 18 --
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/target
binaries to be static.
Signed-off-by: Alyssa Ross
---
Reviewed-by: Brian Cain
target/hexagon/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/hexagon/meson.build b/target/hexagon/meson.build
index b0b253aa6b..9ea1f4fc59 100644
--- a/target/hexagon/meson.build
androm3da wrote:
@ldionne ping
https://github.com/llvm/llvm-project/pull/98712
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On 8/5/2024 8:57 AM, Brian Cain wrote:
On 8/5/2024 5:49 AM, Alyssa Ross wrote:
When cross compiling QEMU configured with --static, I've been getting
configure errors like the following:
Build-time dependency glib-2.0 found: NO
../target/hexagon/meson.build:303:15:
On 8/5/2024 5:49 AM, Alyssa Ross wrote:
When cross compiling QEMU configured with --static, I've been getting
configure errors like the following:
Build-time dependency glib-2.0 found: NO
../target/hexagon/meson.build:303:15: ERROR: Dependency lookup for
glib-2.0 with method 'pkgco
Add my git tree for hexagon. Note that the branch is "hex-next" and not
"hex.next" as had been used previously. But I'll keep the "hex.next" branch
in sync with "hex-next" until this commit lands to avoid confusion.
Signed-off-by: Brian Cain
---
M
On 7/31/2024 12:07 PM, Peter Maydell wrote:
On Thu, 13 Jul 2023 at 17:21, Brian Cain wrote:
-Original Message-
From: Anton Johansson
Sent: Thursday, July 13, 2023 7:09 AM
To: qemu-devel@nongnu.org
Cc: Brian Cain ; peter.mayd...@linaro.org
Subject: [PATCH] target/hexagon/idef
Define a hexagon_cpu_properties list to match the idiom used
by other targets.
Signed-off-by: Brian Cain
---
target/hexagon/cpu.c | 18 --
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 64cc05cca7..93579fbb15
For now, v66 behavior is the same as other CPUs.
Signed-off-by: Brian Cain
---
target/hexagon/cpu-qom.h | 1 +
target/hexagon/cpu.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/target/hexagon/cpu-qom.h b/target/hexagon/cpu-qom.h
index da92fe7468..0b149bd5fe 100644
--- a/target
On 6/12/2024 11:42 AM, Taylor Simpson wrote:
hexagon-core.xml only exposes register p3_0 which is an alias that
aggregates the predicate registers. It is more convenient for users
to interact directly with the predicate registers.
Tested with lldb downloaded from this location
https://github.
vares Bernardino
Reviewed-by: Brian Cain
Reviewed-by: Taylor Simpson
---
v2: updated the copyright year
Queued. thanks!
target/hexagon/op_helper.c | 18 +-
tests/tcg/hexagon/usr.c| 12 +++-
2 files changed, 20 insertions(+), 10 deletions(-)
diff --git a/t
vares Bernardino
---
Reviewed-by: Brian Cain
target/hexagon/op_helper.c | 16
tests/tcg/hexagon/usr.c| 10 ++
2 files changed, 18 insertions(+), 8 deletions(-)
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
index ae5a605513..e1fc88aa0d 1
@@ -0,0 +1,25 @@
+
+set(CMAKE_EXE_LINKER_FLAGS "-lclang_rt.builtins-hexagon -nostdlib" CACHE
STRING "")
+set(CMAKE_SHARED_LINKER_FLAGS "-lclang_rt.builtins-hexagon -nostdlib" CACHE
STRING "")
+set(CMAKE_CXX_COMPILER_TARGET hexagon-unknown-linux-musl CACHE STRING "")
+
+set(LLVM_
https://github.com/androm3da closed
https://github.com/llvm/llvm-project/pull/99552
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https://github.com/androm3da updated
https://github.com/llvm/llvm-project/pull/99552
>From c7fae87eadc5931902d8b0adb555f7ce4b0b99c1 Mon Sep 17 00:00:00 2001
From: Brian Cain
Date: Wed, 17 Jul 2024 08:08:30 -0500
Subject: [PATCH] [clang] [hexagon] handle --unwindlib arg
Signed-off-by: Br
@@ -156,6 +156,8 @@ def err_drv_unsupported_rtlib_for_platform : Error<
"unsupported runtime library '%0' for platform '%1'">;
def err_drv_invalid_unwindlib_name : Error<
"invalid unwind library name in argument '%0'">;
+def err_drv_unsupported_unwind_for_platform : Error<
https://github.com/androm3da updated
https://github.com/llvm/llvm-project/pull/99552
>From 4729e43f3904774dbe5a06ed18a12cbddae8db03 Mon Sep 17 00:00:00 2001
From: Brian Cain
Date: Wed, 17 Jul 2024 08:08:30 -0500
Subject: [PATCH] [clang] [hexagon] handle --unwindlib arg
Signed-off-by: Br
https://github.com/androm3da created
https://github.com/llvm/llvm-project/pull/99552
None
>From 304b87ca8eab37f499dc202bc184c66f45b574e5 Mon Sep 17 00:00:00 2001
From: Brian Cain
Date: Wed, 17 Jul 2024 08:08:30 -0500
Subject: [PATCH] [clang] [hexagon] handle --unwindlib arg
Signed-off
https://github.com/androm3da updated
https://github.com/llvm/llvm-project/pull/98712
>From bfe841f7b917940716b0662cdbaa9fd0597a255f Mon Sep 17 00:00:00 2001
From: Brian Cain
Date: Fri, 12 Jul 2024 21:34:56 -0700
Subject: [PATCH] [cmake] Add hexagon-linux cmake cache files
These can be used
https://github.com/androm3da edited
https://github.com/llvm/llvm-project/pull/98712
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@@ -0,0 +1,25 @@
+
+set(CMAKE_EXE_LINKER_FLAGS "-lclang_rt.builtins-hexagon -nostdlib" CACHE
STRING "")
+set(CMAKE_SHARED_LINKER_FLAGS "-lclang_rt.builtins-hexagon -nostdlib" CACHE
STRING "")
androm3da wrote:
Ok, I think the driver bug (`--unwindlib=none` was i
https://github.com/androm3da updated
https://github.com/llvm/llvm-project/pull/98712
>From c01c1ee772c86ac637578fca866588b8191b15c4 Mon Sep 17 00:00:00 2001
From: Brian Cain
Date: Fri, 12 Jul 2024 21:34:56 -0700
Subject: [PATCH] [cmake] Add hexagon-linux cmake cache files
These can be used
@@ -0,0 +1,25 @@
+
+set(CMAKE_EXE_LINKER_FLAGS "-lclang_rt.builtins-hexagon -nostdlib" CACHE
STRING "")
+set(CMAKE_SHARED_LINKER_FLAGS "-lclang_rt.builtins-hexagon -nostdlib" CACHE
STRING "")
androm3da wrote:
Thanks for the suggestion, it looks like this uncove
@@ -0,0 +1,25 @@
+
+set(CMAKE_EXE_LINKER_FLAGS "-lclang_rt.builtins-hexagon -nostdlib" CACHE
STRING "")
+set(CMAKE_SHARED_LINKER_FLAGS "-lclang_rt.builtins-hexagon -nostdlib" CACHE
STRING "")
androm3da wrote:
The first failure encountered when I remove these is
@@ -0,0 +1,25 @@
+
+set(CMAKE_EXE_LINKER_FLAGS "-lclang_rt.builtins-hexagon -nostdlib" CACHE
STRING "")
+set(CMAKE_SHARED_LINKER_FLAGS "-lclang_rt.builtins-hexagon -nostdlib" CACHE
STRING "")
androm3da wrote:
I'll double check these too - I recall they were nec
@@ -0,0 +1,25 @@
+
androm3da wrote:
IMO landing these cache files are baby steps towards having such a CI job.
I'll look into what it would take, yes.
https://github.com/llvm/llvm-project/pull/98712
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@@ -0,0 +1,25 @@
+
+set(CMAKE_EXE_LINKER_FLAGS "-lclang_rt.builtins-hexagon -nostdlib" CACHE
STRING "")
+set(CMAKE_SHARED_LINKER_FLAGS "-lclang_rt.builtins-hexagon -nostdlib" CACHE
STRING "")
+set(CMAKE_CXX_COMPILER_TARGET hexagon-unknown-linux-musl CACHE STRING "")
+
+set(LLVM_
On 7/15/2024 4:59 AM, Michael Tokarev wrote:
06.07.2024 00:50, Brian Cain wrote:
On 7/4/2024 3:47 AM, Zhao Liu wrote:
Fix the superfluous trailing semicolon in
target/hexagon/imported/mmvec/
ext.idef.
Cc: Brian Cain
Signed-off-by: Zhao Liu
Reviewed-by: Brian Cain
Brian, is it okay
https://github.com/androm3da approved this pull request.
You might want to get approval from someone else - I'm not even remotely close
to a maintainer here.
https://github.com/llvm/llvm-project/pull/90959
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@@ -0,0 +1,62 @@
+//===-- xray_init.cpp ---*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
@@ -0,0 +1,62 @@
+//===-- xray_init.cpp ---*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
rom 3cb0ce53c66815496ac0b5296ee36aaa2f255935 Mon Sep 17 00:00:00 2001
From: Brian Cain
Date: Fri, 12 Jul 2024 21:34:56 -0700
Subject: [PATCH] [cmake] Add hexagon-linux cmake cache files
These can be used to create a fully-bootstrapped toolchain to target
hexagon {baremetal,linux} with scripts like the ones in
https://github.
https://github.com/androm3da closed
https://github.com/llvm/llvm-project/pull/94877
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@@ -471,42 +518,123 @@ uint16_t __xray_register_event_type(
}
XRayPatchingStatus __xray_patch() XRAY_NEVER_INSTRUMENT {
- return controlPatching(true);
+ XRayPatchingStatus CombinedStatus{SUCCESS};
androm3da wrote:
> We could add an assertion to make this a
@@ -346,8 +392,8 @@ else() # not Apple
DEFS ${XRAY_COMMON_DEFINITIONS}
OBJECT_LIBS RTXrayBASIC
PARENT_TARGET xray)
- # Profiler Mode runtime
- add_compiler_rt_runtime(clang_rt.xray-profiling
+# Profiler Mode runtime
+add_compiler_rt_runtime(clang_r
https://github.com/androm3da ready_for_review
https://github.com/llvm/llvm-project/pull/94877
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https://github.com/androm3da updated
https://github.com/llvm/llvm-project/pull/94877
>From ffccfde9f5892520f499b6cfc12ba824aafe5fbd Mon Sep 17 00:00:00 2001
From: Brian Cain
Date: Sat, 8 Jun 2024 16:25:11 -0700
Subject: [PATCH] [hexagon] Add {con,de}structive interference size defn
T
On 7/4/2024 3:47 AM, Zhao Liu wrote:
Fix the superfluous trailing semicolon in target/hexagon/imported/mmvec/
ext.idef.
Cc: Brian Cain
Signed-off-by: Zhao Liu
Reviewed-by: Brian Cain
---
target/hexagon/imported/mmvec/ext.idef | 2 +-
1 file changed, 1 insertion(+), 1 deletion
@@ -0,0 +1,62 @@
+//===-- xray_init.cpp ---*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
@@ -111,6 +156,71 @@ void __xray_init() XRAY_NEVER_INSTRUMENT {
#endif
}
+// Default visibility is hidden, so we have to explicitly make it visible to
+// DSO.
+SANITIZER_INTERFACE_ATTRIBUTE int32_t __xray_register_dso(
+const XRaySledEntry *SledsBegin, const XRaySledEntry
@@ -0,0 +1,62 @@
+//===-- xray_init.cpp ---*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
@@ -471,42 +518,123 @@ uint16_t __xray_register_event_type(
}
XRayPatchingStatus __xray_patch() XRAY_NEVER_INSTRUMENT {
- return controlPatching(true);
+ XRayPatchingStatus CombinedStatus{SUCCESS};
androm3da wrote:
If none of the objects are loaded, `__xray
@@ -471,42 +518,123 @@ uint16_t __xray_register_event_type(
}
XRayPatchingStatus __xray_patch() XRAY_NEVER_INSTRUMENT {
- return controlPatching(true);
+ XRayPatchingStatus CombinedStatus{SUCCESS};
+ for (size_t I = 0; I < __xray_num_objects(); ++I) {
+if (!isObjectLoad
@@ -63,6 +63,10 @@ XRayArgs::XRayArgs(const ToolChain &TC, const ArgList &Args)
{
<< XRayInstrument->getSpelling() << Triple.str();
}
+ if (Args.hasFlag(options::OPT_fxray_enable_shared,
+ options::OPT_fno_xray_enable_shared, false))
+XRayEnab
@@ -50,14 +52,72 @@ atomic_uint8_t XRayInitialized{0};
// This should always be updated before XRayInitialized is updated.
SpinMutex XRayInstrMapMutex;
-XRaySledMap XRayInstrMap;
+// XRaySledMap XRayInstrMap;
+// Contains maps for the main executable as well as DSOs.
+// std:
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