Re: No command line?

2021-03-02 Thread Chris Wilson
is now a batch analyse function in the graphical version of gnubg > (actually also in the text) that you mind find useful. > > C > On 3/2/21 11:03 AM, Chris Wilson wrote: > > Thanks Ian. I run these batches overnight, but it won't hurt to add 'set > priority to idle'. I am running an

Re: [Intel-gfx] [PATCH] drm/i915: Verify dma_addr in gen8_ggtt_pte_encode

2021-03-02 Thread Chris Wilson
Quoting Piorkowski, Piotr (2021-02-24 15:29:25) > From: Piotr Piórkowski > > Until now, the gen8_ggtt_pte_encode function, responsible for the preparation > of GGTT PTE, has not verified in any way whether the address given as the > parameter is correct. > By adding a GGTT address mask, we can

Re: [Intel-gfx] [PATCH] drm/i915: Wedge the GPU if command parser setup fails

2021-03-02 Thread Chris Wilson
ikely but for > correctness should still be handled. > > Signed-off-by: Tvrtko Ursulin > Fixes: 311a50e76a33 ("drm/i915: Add support for mandatory cmdparsing") > Cc: Jon Bloomfield > Cc: Joonas Lahtinen > Cc: Chris Wilson > --- > To catchup with referenced

Re: No command line?

2021-03-02 Thread Chris Wilson
uld let gnubg use all the power when nothing else is > happening, but back off on hogging resources when you’re doing other stuff. > I have set priority idle as a permanent setting. > > Cheers, > Ian > > From: Bug-gnubg [mailto:bug-gnubg-bounces+ian.shaw=riverauto.co...@gnu.

Re: No command line?

2021-03-01 Thread Chris Wilson
0 > set analysis movefilter 3 2 0 4 0.08 > set analysis movefilter 4 0 4 12 0.32 > set analysis movefilter 4 1 -1 0 0 > set analysis movefilter 4 2 0 4 0.08 > set analysis movefilter 4 3 -1 0 0 > > set analysis cubedecision eval plies 4 > set analysis chequerplay eva

No command line?

2021-03-01 Thread Chris Wilson
Years ago I would batch analyze my matches. I wrote a program that created entries in the following format (minus the dashes): --- set cache 65536 set Priority Idle set analysis luckanalysis plies 2 set analysis luckanalysis reduced 2 set analysis luckanalysis cubeful on import mat

[Intel-gfx] [PATCH] drm/i915: Refine VT-d scanout workaround

2021-02-20 Thread Chris Wilson
the vma is included with the guard. Signed-off-by: Chris Wilson Cc: Ville Syrjälä Cc: Matthew Auld Cc: Imre Deak Reviewed-by: Matthew Auld --- drivers/gpu/drm/i915/gem/i915_gem_domain.c | 13 +++ drivers/gpu/drm/i915/gt/intel_ggtt.c | 25 +- drivers/gpu/drm

[Intel-gfx] [PATCH] drm/i915: Refine VT-d scanout workaround

2021-02-20 Thread Chris Wilson
the vma is included with the guard. Signed-off-by: Chris Wilson Cc: Ville Syrjälä Cc: Matthew Auld Cc: Imre Deak Reviewed-by: Matthew Auld --- drivers/gpu/drm/i915/gem/i915_gem_domain.c | 13 +++ drivers/gpu/drm/i915/gt/intel_ggtt.c | 25 +- drivers/gpu/drm

Re: [Intel-gfx] [PATCH] drm/i915: Wait for scanout to stop when sanitizing planes

2021-02-17 Thread Chris Wilson
d intel_plane_disable_noatomic(struct > intel_crtc *crtc, > intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, > false); > > intel_disable_plane(plane, crtc_state); > + intel_wait_for_vblank(dev_priv, crtc->pipe); I could only find paths here from sanitize, so it looks safe from the p

Re: [PATCH] drm/i915: Enable -Wuninitialized

2021-02-17 Thread Chris Wilson
always > initialized in icl_combo_phy_verify_state") > Reported-by: Arnd Bergmann > Signed-off-by: Nathan Chancellor make CC=clang-11 now compiles cleanly for me as well, Reviewed-by: Chris Wilson -Chris

Re: [Intel-gfx] [PATCH i-g-t] tests/i915/perf_pmu: Subtest to measure sampling error for 100% busy

2021-02-16 Thread Chris Wilson
Quoting Tvrtko Ursulin (2021-02-16 15:59:33) > > On 16/02/2021 12:49, Chris Wilson wrote: > > Quoting Tvrtko Ursulin (2021-02-16 10:50:50) > >> From: Tvrtko Ursulin > >> > >> Test that periodic reads of engine busyness against a constant 100% load >

Re: [Intel-gfx] [PATCH] drm/i915: Readout conn_state->max_bpc

2021-02-16 Thread Chris Wilson
not be populated on pre-g4x machines, > in which case we just fall back to max_bpc==8 and let .compute_config() > limit the resulting pipe_bpp further if necessary. > > Cc: Daniel Vetter > Reported-by: Chris Wilson > Signed-off-by: Ville Syrjälä Tested-by: Chris Wilso

[Intel-gfx] [PATCH i-g-t] i915/gem_exec_reloc: Verify relocations with pinned scanout framebuffers

2021-02-16 Thread Chris Wilson
In light of the VT-d workarounds, we may introduce padding around the scanout vma. This should not affect relocations referencing the scanout on !full-ppgtt where we leak the GGTT address of scanout to users. Signed-off-by: Chris Wilson Cc: Matthew Auld Reviewed-by: Matthew Auld --- tests

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] i915/gem_exec_reloc: Verify relocations with pinned scanout framebuffers

2021-02-16 Thread Chris Wilson
Quoting Matthew Auld (2021-02-16 16:49:28) > On Tue, 16 Feb 2021 at 14:32, Chris Wilson wrote: > > > > In light of the VT-d workarounds, we may introduce padding around the > > scanout vma. This should not affect relocations referencing the scanout > > on !full-p

[Intel-gfx] [PATCH i-g-t] i915/gem_exec_reloc: Verify relocations with pinned scanout framebuffers

2021-02-16 Thread Chris Wilson
In light of the VT-d workarounds, we may introduce padding around the scanout vma. This should not affect relocations referencing the scanout on !full-ppgtt where we leak the GGTT address of scanout to users. Signed-off-by: Chris Wilson Cc: Matthew Auld --- tests/i915/gem_exec_reloc.c | 102

Re: [Intel-gfx] [PATCH i-g-t] tests/i915/perf_pmu: Subtest to measure sampling error for 100% busy

2021-02-16 Thread Chris Wilson
Quoting Tvrtko Ursulin (2021-02-16 10:50:50) > From: Tvrtko Ursulin > > Test that periodic reads of engine busyness against a constant 100% load > are within the 5000ppm tolerance when comparing perf timestamp versus > counter values. > > Signed-off-by: Tvrtko Ursulin > --- >

Re: [Intel-gfx] [PATCH i-g-t] tests/i915/perf_pmu: Subtest to measure sampling error for 100% busy

2021-02-16 Thread Chris Wilson
Quoting Tvrtko Ursulin (2021-02-16 10:50:50) > From: Tvrtko Ursulin > > Test that periodic reads of engine busyness against a constant 100% load > are within the 5000ppm tolerance when comparing perf timestamp versus > counter values. > > Signed-off-by: Tvrtko Ursulin > --- >

Re: [Intel-gfx] [PATCH] drm/i915/gem: Add a check for object size for corner cases

2021-02-16 Thread Chris Wilson
Quoting Ram Moon, AnandX (2021-02-16 12:05:23) > Hi Chris, > > -Original Message- > From: dri-devel On Behalf Of Chris > Wilson > Sent: Monday, February 15, 2021 6:10 PM > To: Auld, Matthew ; Ram Moon, AnandX > ; Surendrakumar Upadhyay, TejaskumarX > ; Ursul

Re: [Intel-gfx] [PATCH] drm/i915/gem: Add a check for object size for corner cases

2021-02-16 Thread Chris Wilson
Quoting Ram Moon, AnandX (2021-02-16 12:05:23) > Hi Chris, > > -Original Message- > From: dri-devel On Behalf Of Chris > Wilson > Sent: Monday, February 15, 2021 6:10 PM > To: Auld, Matthew ; Ram Moon, AnandX > ; Surendrakumar Upadhyay, TejaskumarX > ; Ursul

Re: [Intel-gfx] [PATCH i-g-t] tests/i915/perf_pmu: Subtest to measure sampling error for 100% busy

2021-02-16 Thread Chris Wilson
Quoting Tvrtko Ursulin (2021-02-16 10:50:50) > From: Tvrtko Ursulin > > Test that periodic reads of engine busyness against a constant 100% load > are within the 5000ppm tolerance when comparing perf timestamp versus > counter values. We've previously only included the accuracy tests on

[Intel-gfx] [PATCH] drm/i915: Introduce guard pages to i915_vma

2021-02-15 Thread Chris Wilson
checks and placement restrictions. v3: Fix the check on the placement upper bound. The request user offset is relative to the guard offset (not the node.start) and so we should not include the initial guard offset again when computing the upper bound of the node. Signed-off-by: Chris Wilson Cc

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Introduce guard pages to i915_vma

2021-02-15 Thread Chris Wilson
Quoting Matthew Auld (2021-02-15 19:31:39) > On Mon, 15 Feb 2021 at 18:15, Chris Wilson wrote: > > > > Quoting Matthew Auld (2021-02-15 18:04:08) > > > On Mon, 15 Feb 2021 at 15:56, Chris Wilson > > > wrote: > > > > > > > > Introduce th

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Introduce guard pages to i915_vma

2021-02-15 Thread Chris Wilson
Quoting Matthew Auld (2021-02-15 18:04:08) > On Mon, 15 Feb 2021 at 15:56, Chris Wilson wrote: > > > > Introduce the concept of padding the i915_vma with guard pages before > > and aft. The major consequence is that all ordinary uses of i915_vma > > must use i9

Re: [Intel-gfx] [PATCH] drm/i915/selftest: Fix an error code in mock_context_barrier()

2021-02-15 Thread Chris Wilson
Quoting Dan Carpenter (2021-02-15 15:58:27) > If the igt_request_alloc() call fails then this should return a > negative error code, but currently it returns success. > > Fixes: 85fddf0b0027 ("drm/i915: Introduce a context barrier callback") > Signed-off-by: Dan Carpe

[Intel-gfx] [PATCH 3/3] drm/i915: Refine VT-d scanout workaround

2021-02-15 Thread Chris Wilson
which is still used by the drm_mm itself, into an adjustment of node.start at the point of use. v3: Pass the requested guard padding from the caller, so we can drop the VT-d w/a knowledge from the i915_vma allocator. Signed-off-by: Chris Wilson Cc: Ville Syrjälä Cc: Matthew Auld Reviewed

[Intel-gfx] [PATCH 1/3] drm/i915: Wrap all access to i915_vma.node.start|size

2021-02-15 Thread Chris Wilson
otable exceptions are the selftests that are testing exact behaviour of i915_vma_pin/i915_vma_insert. Signed-off-by: Chris Wilson Reviewed-by: Matthew Auld --- drivers/gpu/drm/i915/display/intel_fbdev.c| 6 +-- .../gpu/drm/i915/gem/i915_gem_client_blt.c| 3 +- .../gpu/drm/i9

[Intel-gfx] [PATCH 2/3] drm/i915: Introduce guard pages to i915_vma

2021-02-15 Thread Chris Wilson
checks and placement restrictions. Signed-off-by: Chris Wilson Cc: Matthew Auld --- drivers/gpu/drm/i915/gt/intel_ggtt.c | 12 ++-- drivers/gpu/drm/i915/i915_vma.c | 28 ++- drivers/gpu/drm/i915/i915_vma.h | 5 +++-- drivers/gpu/drm/i915/i915_vma_types.h

Re: [Intel-gfx] [PATCH] drm/i915/gem: Add a check for object size for corner cases

2021-02-15 Thread Chris Wilson
Quoting Ram Moon, AnandX (2021-02-15 12:29:17) > Hi Chris, > > -Original Message- > From: dri-devel On Behalf Of Chris > Wilson > Sent: Wednesday, February 10, 2021 4:15 PM > To: Ram Moon, AnandX ; Jani Nikula > ; Auld, Matthew ; > Surendrakumar Upadhya

Re: [Intel-gfx] [PATCH] drm/i915/gem: Add a check for object size for corner cases

2021-02-15 Thread Chris Wilson
Quoting Ram Moon, AnandX (2021-02-15 12:29:17) > Hi Chris, > > -Original Message- > From: dri-devel On Behalf Of Chris > Wilson > Sent: Wednesday, February 10, 2021 4:15 PM > To: Ram Moon, AnandX ; Jani Nikula > ; Auld, Matthew ; > Surendrakumar Upadhya

Re: [Intel-gfx] [CI 4/4] drm/i915: move intel_init_audio_hooks inside display

2021-02-13 Thread Chris Wilson
rchi And patch 2 answered the question of what about intel_audio_init(). Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [RFC 3/3] drm/i915/gt: Export device and per-process runtimes via procfs

2021-02-12 Thread Chris Wilson
Quoting Emil Velikov (2021-02-12 15:45:04) > On Fri, 12 Feb 2021 at 15:16, Chris Wilson wrote: > > > > Quoting Emil Velikov (2021-02-12 14:57:56) > > > Hi Chris, > > > > > > On Thu, 4 Feb 2021 at 12:11, Chris Wilson > > > wrote: > >

Re: [RFC 3/3] drm/i915/gt: Export device and per-process runtimes via procfs

2021-02-12 Thread Chris Wilson
Quoting Emil Velikov (2021-02-12 15:45:04) > On Fri, 12 Feb 2021 at 15:16, Chris Wilson wrote: > > > > Quoting Emil Velikov (2021-02-12 14:57:56) > > > Hi Chris, > > > > > > On Thu, 4 Feb 2021 at 12:11, Chris Wilson > > > wrote: > >

Re: [Intel-gfx] [PATCH] Revert "HAX sound: Disable probing snd_hda with DG1"

2021-02-12 Thread Chris Wilson
Quoting Chris Wilson (2021-02-12 15:22:13) > Quoting Kai Vehmanen (2021-02-12 14:53:02) > > This reverts commit 3632610d38316bca9b0cd9d649ce3cefab58520a. > > > > DG1 has been supported in upstream since v5.10 with commit > > 69b08bdfa818 ("ALSA: hda

Re: [Intel-gfx] [PATCH] Revert "HAX sound: Disable probing snd_hda with DG1"

2021-02-12 Thread Chris Wilson
Quoting Kai Vehmanen (2021-02-12 14:53:02) > This reverts commit 3632610d38316bca9b0cd9d649ce3cefab58520a. > > DG1 has been supported in upstream since v5.10 with commit > 69b08bdfa818 ("ALSA: hda - add Intel DG1 PCI and HDMI ids"). Exactly, otherwise this patch wouldn't have been required to

Re: [RFC 3/3] drm/i915/gt: Export device and per-process runtimes via procfs

2021-02-12 Thread Chris Wilson
Quoting Emil Velikov (2021-02-12 14:57:56) > Hi Chris, > > On Thu, 4 Feb 2021 at 12:11, Chris Wilson wrote: > > > > Register with /proc/gpu to provide the client runtimes for generic > > top-like overview, e.g. gnome-system-monitor can use this information to > &g

Re: [Intel-gfx] [RFC 3/3] drm/i915/gt: Export device and per-process runtimes via procfs

2021-02-12 Thread Chris Wilson
Quoting Emil Velikov (2021-02-12 14:57:56) > Hi Chris, > > On Thu, 4 Feb 2021 at 12:11, Chris Wilson wrote: > > > > Register with /proc/gpu to provide the client runtimes for generic > > top-like overview, e.g. gnome-system-monitor can use this information to > &g

[Intel-gfx] [PATCH i-g-t] i915/gem_userptr_blts: Move readonly test into common block

2021-02-12 Thread Chris Wilson
Since we only run test_readonly for a single sync-flag, place it in the common block. Signed-off-by: Chris Wilson --- tests/i915/gem_userptr_blits.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tests/i915/gem_userptr_blits.c b/tests/i915/gem_userptr_blits.c index

[Intel-gfx] [PATCH i-g-t] i915/gem_userptr_blts: Move readonly test into common block

2021-02-12 Thread Chris Wilson
Since we only run test_readonly for a single sync-flag, place it in the common block. Signed-off-by: Chris Wilson --- tests/i915/gem_userptr_blits.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tests/i915/gem_userptr_blits.c b/tests/i915/gem_userptr_blits.c index

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Introduce guard pages to i915_vma

2021-02-12 Thread Chris Wilson
Quoting Matthew Auld (2021-02-12 13:43:46) > On Fri, 12 Feb 2021 at 10:22, Chris Wilson wrote: > > > > Introduce the concept of padding the i915_vma with guard pages before > > and aft. The major consequence is that all ordinary uses of i915_vma > > must use i9

[Intel-gfx] [PATCH v6] drm/i915/gt: Ratelimit heartbeat completion probing

2021-02-12 Thread Chris Wilson
of a successful heartbeat. Remove it, but then put it back to handle large mismatches between the sysfs properties and reality. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2853 Suggested-by: CQ Tang Signed-off-by: Chris Wilson --- .../gpu/drm/i915/gt/intel_engine_heartbeat.c | 107

[Intel-gfx] [PATCH 3/3] drm/i915: Refine VT-d scanout workaround

2021-02-12 Thread Chris Wilson
which is still used by the drm_mm itself, into an adjustment of node.start at the point of use. Signed-off-by: Chris Wilson Cc: Ville Syrjälä Cc: Matthew Auld --- drivers/gpu/drm/i915/gem/i915_gem_domain.c | 3 +++ drivers/gpu/drm/i915/gt/intel_ggtt.c | 25 +- drivers/gpu

[Intel-gfx] [PATCH 2/3] drm/i915: Introduce guard pages to i915_vma

2021-02-12 Thread Chris Wilson
ure that the execobj.offset is transparent and excludes the guards. (On such platforms, without full-ppgtt, userspace has to use relocations so the presence of more untouchable regions within its GTT such be of no further issue.) Signed-off-by: Chris Wilson Cc: Matthew Auld --- drivers/gpu/drm/i915/gt/intel_ggt

[Intel-gfx] [PATCH 1/3] drm/i915: Wrap all access to i915_vma.node.start|size

2021-02-12 Thread Chris Wilson
otable exceptions are the selftests that are testing exact behaviour of i915_vma_pin/i915_vma_insert. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/display/intel_fbdev.c| 6 ++-- .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 29 ++- drivers/gpu/drm/i915/gem/i915_gem_

[Intel-gfx] [PATCH v5] drm/i915/gt: Ratelimit heartbeat completion probing

2021-02-11 Thread Chris Wilson
-by: CQ Tang Signed-off-by: Chris Wilson --- .../gpu/drm/i915/gt/intel_engine_heartbeat.c | 92 +++--- drivers/gpu/drm/i915/gt/intel_engine_types.h | 7 ++ .../drm/i915/gt/selftest_engine_heartbeat.c | 93 --- drivers/gpu/drm/i915/gt/selftest_execlists.c | 5 +- 4

[Intel-gfx] [PATCH v4] drm/i915/gt: Ratelimit heartbeat completion probing

2021-02-11 Thread Chris Wilson
and detection of false/unexpected hang reports. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2853 Suggested-by: CQ Tang Signed-off-by: Chris Wilson --- .../gpu/drm/i915/gt/intel_engine_heartbeat.c | 107 +++--- drivers/gpu/drm/i915/gt/intel_engine_types.h | 8 ++ .../drm

Re: [Intel-gfx] [PATCH] drm/i915: Refine VT-d scanout workaround

2021-02-11 Thread Chris Wilson
Quoting Matthew Auld (2021-02-11 17:00:20) > Throwing some color_adjust at it might be another option to consider. > Maybe something like: > > +static void i915_ggtt_color_adjust_vdt(const struct drm_mm_node *node, > + unsigned long color, > +

Re: [Intel-gfx] [PATCH] drm/i915: Refine VT-d scanout workaround

2021-02-11 Thread Chris Wilson
Quoting Ville Syrjälä (2021-02-11 16:05:59) > On Wed, Feb 10, 2021 at 11:39:46PM +0000, Chris Wilson wrote: > > @@ -637,6 +642,13 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 > > alignment, u64 flags) > > alignment,

Re: [Intel-gfx] [PATCH] drm/i915: Refine VT-d scanout workaround

2021-02-11 Thread Chris Wilson
Quoting Matthew Auld (2021-02-11 14:25:41) > On 10/02/2021 23:39, Chris Wilson wrote: > > VT-d may cause overfetch of the scanout PTE, both before and after the > > vma (depending on the scanout orientation). bspec recommends that we > > provide a tile-row in either direction

Re: [Intel-gfx] [PATCH] drm/i915: Probe system memory regions before enabling HW

2021-02-11 Thread Chris Wilson
Quoting Matthew Auld (2021-02-11 12:27:56) > On 11/02/2021 11:20, Chris Wilson wrote: > > If we want to track system/stolen as memory regions, we need to setup > > our bookkeeping *before* we want to start allocating and reserving > > objects in those regions. In particular,

[Intel-gfx] [PATCH v3] drm/i915/gt: Ratelimit heartbeat completion probing

2021-02-11 Thread Chris Wilson
and detection of false/unexpected hang reports. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2853 Suggested-by: CQ Tang Signed-off-by: Chris Wilson --- .../gpu/drm/i915/gt/intel_engine_heartbeat.c | 104 +++--- drivers/gpu/drm/i915/gt/intel_engine_types.h | 8 ++ .../drm

[Intel-gfx] [PATCH] lib: Add a YAML emitter

2021-02-11 Thread Chris Wilson
/libyaml/blob/master/src/emitter.c under a permissive MIT licence. Signed-off-by: Chris Wilson Cc: Jani Nikula Cc: Joonas Lahtinen --- Converting to kerneldoc is about the last major task. It uses an opencoded stack struct which might be nice to convert to a library, maybe just use XArray? It has

[Intel-gfx] [PATCH] drm/i915: Defer object allocation from GGTT probe to GGTT init

2021-02-11 Thread Chris Wilson
Rather than try and allocate objects as we perform our early HW probes, defer the allocation for GGTT objects (such as the scratch page) to later in the initialisation. Signed-off-by: Chris Wilson Cc: Matthew Auld --- drivers/gpu/drm/i915/gt/intel_ggtt.c | 38 +++- 1

[Intel-gfx] [PATCH] drm/i915: Probe system memory regions before enabling HW

2021-02-11 Thread Chris Wilson
-stolen memory region beforehand. Signed-off-by: Chris Wilson Cc: Matthew Auld --- drivers/gpu/drm/i915/i915_drv.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index b708517d3972..139cea4443fd 100644

Re: [Intel-gfx] [5.10.y regression] i915 clear-residuals mitigation is causing gfx issues

2021-02-11 Thread Chris Wilson
Quoting Hans de Goede (2021-02-11 10:36:13) > Hi, > > On 2/10/21 1:48 PM, Chris Wilson wrote: > > Quoting Hans de Goede (2021-02-10 10:37:19) > >> Hi, > >> > >> On 2/10/21 12:07 AM, Chris Wilson wrote: > >>> Quoting Hans de Goede (2021-02-09

Re: [Intel-gfx] [PATCH 1/6] drm/i915/gt: Sanitize GPU during prepare-to-suspend

2021-02-11 Thread Chris Wilson
Quoting Rodrigo Vivi (2021-02-11 04:25:17) > On Wed, Feb 10, 2021 at 10:19:50PM +0000, Chris Wilson wrote: > > After calling intel_gt_suspend_prepare(), the driver starts to turn off > > various subsystems, such as clearing the GGTT, before calling > > intel_gt_suspend_late()

Re: [Intel-gfx] [PATCH 2/6] drm/i915: Clear internal GT state on hibernate

2021-02-11 Thread Chris Wilson
Quoting Rodrigo Vivi (2021-02-11 04:28:41) > On Wed, Feb 10, 2021 at 10:19:51PM +0000, Chris Wilson wrote: > > Call intel_gt_suspend_late() to disable the GT before hibernation. > > > > Signed-off-by: Chris Wilson > > --- > > drivers/gpu/drm/i915/gem/i915_gem_p

Re: [Intel-gfx] [5.10.y regression] i915 clear-residuals mitigation is causing gfx issues

2021-02-10 Thread Chris Wilson
Quoting Hans de Goede (2021-02-10 10:37:19) > Hi, > > On 2/10/21 12:07 AM, Chris Wilson wrote: > > Quoting Hans de Goede (2021-02-09 11:46:46) > >> Hi, > >> > >> On 2/9/21 12:27 AM, Chris Wilson wrote: > >>> Quoting Hans de Goede (2021-02-08 2

[Intel-gfx] [PATCH] drm/i915: Refine VT-d scanout workaround

2021-02-10 Thread Chris Wilson
pages around scanout, we can avoid touching the whole GGTT. To avoid having to introduce extra nodes around each scanout vma, we adjust the scanout drm_mm_node to be smaller than the allocated space, and fixup the extra PTE during dma binding. Signed-off-by: Chris Wilson Cc: Ville Syrjälä Cc

[Intel-gfx] [PATCH 4/6] drm/i915/selftests: Restrict partial-tiling to write into the object

2021-02-10 Thread Chris Wilson
Check that the address we are about to write into maps into the object to avoid stray writes into the scratch page. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c | 11 +-- 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm

[Intel-gfx] [PATCH 3/6] drm/i915/selftests: Declare suspend_state before testing suspend

2021-02-10 Thread Chris Wilson
As we mock the suspend routines to exercise suspending driver and manipulating backing storage across the suspend, declare the suspend target as we do. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/selftests/i915_gem.c | 40 +-- 1 file changed, 30 insertions(+), 10

[Intel-gfx] [PATCH 5/6] drm/i915: Check for scratch page scribbling

2021-02-10 Thread Chris Wilson
Periodically check, for example when idling and upon closing user contexts, whether or not some client has written into unallocated PTE in their ppGTT. Signed-off-by: Chris Wilson Reviewed-by: Mika Kuoppala --- .../drm/i915/gem/selftests/i915_gem_context.c | 24 +++--- .../drm/i915/gem

[Intel-gfx] [PATCH 6/6] drm/i915: Remove unused debug functions

2021-02-10 Thread Chris Wilson
Remove or hide unused debug functions from clang, or else it moans. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_sw_fence.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_sw_fence.c b/drivers/gpu/drm/i915/i915_sw_fence.c index

[Intel-gfx] [PATCH 2/6] drm/i915: Clear internal GT state on hibernate

2021-02-10 Thread Chris Wilson
Call intel_gt_suspend_late() to disable the GT before hibernation. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gem/i915_gem_pm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_pm.c index 000e1cd8e920

[Intel-gfx] [PATCH 1/6] drm/i915/gt: Sanitize GPU during prepare-to-suspend

2021-02-10 Thread Chris Wilson
internal state to the residual GGTT addresses that are now pointing into scratch. Let's reset the GPU to clear that internal state as soon we have idled the GPU in prepare-to-suspend. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gt/intel_gt_pm.c | 5 - 1 file changed, 4 insertions(+), 1

Re: [Intel-gfx] [5.10.y regression] i915 clear-residuals mitigation is causing gfx issues

2021-02-10 Thread Chris Wilson
Quoting Hans de Goede (2021-02-10 10:37:19) > Hi, > > On 2/10/21 12:07 AM, Chris Wilson wrote: > > Quoting Hans de Goede (2021-02-09 11:46:46) > >> Hi, > >> > >> On 2/9/21 12:27 AM, Chris Wilson wrote: > >>> Quoting Hans de Goede (2021-02-08 2

[Intel-gfx] [CI] drm/i915/gt: Correct surface base address for renderclear

2021-02-10 Thread Chris Wilson
The surface_state_base is an offset into the batch, so we need to pass the correct batch address for STATE_BASE_ADDRESS. Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts") Signed-off-by: Chris Wilson Cc: Mika Kuoppala Cc: Prathap Kumar Valsan Cc: Akeem G Abo

Re: [Intel-gfx] [PATCH 2/2] drm/i915/gt: Correct surface base address

2021-02-10 Thread Chris Wilson
Quoting Mika Kuoppala (2021-02-10 10:50:18) > Chris Wilson writes: > > > The surface_state_base is an offset into the batch, so we need to pass > > the correct batch address for STATE_BASE_ADDRESS. > > > > Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Check for scratch page scribbling

2021-02-10 Thread Chris Wilson
Quoting Mika Kuoppala (2021-02-10 10:49:55) > Chris Wilson writes: > > diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c > > b/drivers/gpu/drm/i915/gt/intel_gtt.c > > index d34770ae4c9a..5ac9eb4a3a92 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_gtt.c > &

Re: [Intel-gfx] [PATCH i-g-t 2/3] intel_gpu_top: Aggregate clients by PID by default

2021-02-10 Thread Chris Wilson
; + return sort_clients(clients, client_cmp); Still two calls to return sort_clients(foo, client_cmp) in this function :) [a clients = aggregated; after processing would merge the two paths]. Reviewed-by: Chris Wilson -Chris ___ Intel-gf

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 2/3] intel_gpu_top: Aggregate clients by PID by default

2021-02-10 Thread Chris Wilson
Quoting Tvrtko Ursulin (2021-02-10 10:55:44) > > On 10/02/2021 10:35, Chris Wilson wrote: > > Quoting Tvrtko Ursulin (2021-02-10 09:37:55) > > Ok, that works very well. Hmm. The sort order does seem a little jumpy > > though. May I suggest ac->id = -c->pid; instead o

Re: [Intel-gfx] [PATCH] drm/i915/gem: Add a check for object size for corner cases

2021-02-10 Thread Chris Wilson
Quoting Anand Moon (2021-02-10 07:59:29) > Add check for object size to return appropriate error -E2BIG or -EINVAL > to avoid WARM_ON and sucessfull return for some testcase. No. You miss the point of having those warnings. We need to inspect the code to remove the last remaining "int pagenum",

Re: [Intel-gfx] [PATCH] drm/i915/gem: Add a check for object size for corner cases

2021-02-10 Thread Chris Wilson
Quoting Anand Moon (2021-02-10 07:59:29) > Add check for object size to return appropriate error -E2BIG or -EINVAL > to avoid WARM_ON and sucessfull return for some testcase. No. You miss the point of having those warnings. We need to inspect the code to remove the last remaining "int pagenum",

Re: [Intel-gfx] [PATCH i-g-t 1/3] intel_gpu_top: Wrap interactive header

2021-02-10 Thread Chris Wilson
. I'm not fond of this layout, but that's just a personal preference. Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 3/3] intel_gpu_top: Interactive help screen

2021-02-10 Thread Chris Wilson
Quoting Tvrtko Ursulin (2021-02-10 09:37:56) > From: Tvrtko Ursulin > > Show a list of supported interactive commands when pressing 'h'. > > Signed-off-by: Tvrtko Ursulin Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 2/3] intel_gpu_top: Aggregate clients by PID by default

2021-02-10 Thread Chris Wilson
Quoting Tvrtko Ursulin (2021-02-10 09:37:55) > +static struct clients *aggregated_clients(struct clients *clients) > +{ > + struct client *ac, *c, *cp = NULL; > + struct clients *aggregated; > + int tmp, num = 0; > + > + /* Sort by pid first to make it easy to aggregate

[Intel-gfx] [PATCH 2/2] drm/i915/gt: Correct surface base address

2021-02-10 Thread Chris Wilson
The surface_state_base is an offset into the batch, so we need to pass the correct batch address for STATE_BASE_ADDRESS. Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts") Signed-off-by: Chris Wilson Cc: Mika Kuoppala Cc: Prathap Kumar Valsan Cc: Akeem G

[Intel-gfx] [PATCH 1/2] drm/i915: Check for scratch page scribbling

2021-02-10 Thread Chris Wilson
Periodically check, for example when idling and upon closing user contexts, whether or not some client has written into unallocated PTE in their ppGTT. Signed-off-by: Chris Wilson --- .../drm/i915/gem/selftests/i915_gem_context.c | 19 +++-- drivers/gpu/drm/i915/gt/intel_engine_cs.c

[Intel-gfx] [PATCH] drm/i915: Check for scratch page scribbling

2021-02-10 Thread Chris Wilson
Periodically check, for example when idling and upon closing user contexts, whether or not some client has written into unallocated PTE in their ppGTT. Signed-off-by: Chris Wilson --- .../drm/i915/gem/selftests/i915_gem_context.c | 19 +++-- drivers/gpu/drm/i915/gt/intel_engine_cs.c

[Intel-gfx] [PATCH] drm/i915: Check for scratch page scribbling

2021-02-10 Thread Chris Wilson
Periodically check, for example when idling and upon closing user contexts, whether or not some client has written into unallocated PTE in their ppGTT. Signed-off-by: Chris Wilson --- .../drm/i915/gem/selftests/i915_gem_context.c | 19 +++-- drivers/gpu/drm/i915/gt/intel_engine_cs.c

Re: [Intel-gfx] [5.10.y regression] i915 clear-residuals mitigation is causing gfx issues

2021-02-09 Thread Chris Wilson
Quoting Hans de Goede (2021-02-09 11:46:46) > Hi, > > On 2/9/21 12:27 AM, Chris Wilson wrote: > > Quoting Hans de Goede (2021-02-08 20:38:58) > >> Hi All, > >> > >> We (Fedora) have been receiving reports from multiple users about gfx > >&

Re: [Intel-gfx] [5.10.y regression] i915 clear-residuals mitigation is causing gfx issues

2021-02-09 Thread Chris Wilson
Quoting Hans de Goede (2021-02-09 11:46:46) > Hi, > > On 2/9/21 12:27 AM, Chris Wilson wrote: > > Quoting Hans de Goede (2021-02-08 20:38:58) > >> Hi All, > >> > >> We (Fedora) have been receiving reports from multiple users about gfx > >&

Re: [Intel-gfx] [PATCH 10/31] drm/i915: Fair low-latency scheduling

2021-02-09 Thread Chris Wilson
Quoting Tvrtko Ursulin (2021-02-09 09:37:19) > > On 08/02/2021 10:52, Chris Wilson wrote: > > > diff --git a/drivers/gpu/drm/i915/Kconfig.profile > > b/drivers/gpu/drm/i915/Kconfig.profile > > index 35bbe2b80596..f1d009906f71 100644 > > --- a/drivers/gpu/d

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Disallow plane x+w>stride on ilk+ with X-tiling

2021-02-09 Thread Chris Wilson
Quoting Chris Wilson (2021-02-09 09:22:09) > Quoting Ville Syrjala (2021-02-09 02:19:16) > > + while ((src_x + src_w) * cpp > > > plane_state->color_plane[0].stride) { > > + if (offset == 0) { > > +

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Warn when releasing a frontbuffer while in use

2021-02-09 Thread Chris Wilson
and indeed they are cleared by intel_frontbuffer_track as the scanout is switched away from the object. A stacktrace here isn't particularly useful for tracking down the leak, but it is a trivial method to make CI pay attention. Reviewed-by: Chris Wilson -Chris _

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Disallow plane x+w>stride on ilk+ with X-tiling

2021-02-09 Thread Chris Wilson
was to reduce src_x/src_y to fit within the crtc limits. While remapping could be used to solve that, the aligned_offset computation allows reuse of a single view. Since offset, src_x are a function of the plane input parameters, this should be possible to exercise with carefully selected framebuffers and modesetting. Right? Is there a test case for this? Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Fix overlay frontbuffer tracking

2021-02-09 Thread Chris Wilson
this a bit more clear let's track the frontbuffer > explicitly instead of just grabbing it via the old vma. > > Cc: sta...@vger.kernel.org > Cc: Chris Wilson > Cc: Joonas Lahtinen > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/1136 > Fixes: da42104f589d ("d

Re: [Intel-gfx] [5.10.y regression] i915 clear-residuals mitigation is causing gfx issues

2021-02-08 Thread Chris Wilson
Quoting Hans de Goede (2021-02-08 20:38:58) > Hi All, > > We (Fedora) have been receiving reports from multiple users about gfx issues > / glitches > stating with 5.10.9. All reporters are users of Ivy Bridge / Haswell iGPUs > and all > reporters report that adding i915.mitigations=off to the

Re: [Intel-gfx] [PATCH 30/31] drm/i915: Support secure dispatch on gen6/gen7

2021-02-08 Thread Chris Wilson
Quoting Dave Airlie (2021-02-08 20:55:19) > On Mon, 8 Feb 2021 at 20:53, Chris Wilson wrote: > > > > Re-enable secure dispatch for gen6/gen7, primarily to workaround the > > command parser and overly zealous command validation on Haswell. For > > example this prevents m

Re: [Intel-gfx] [RFC 08/14] drm/i915/pxp: Implement arb session teardown

2021-02-08 Thread Chris Wilson
Quoting Daniele Ceraolo Spurio (2021-02-08 19:43:23) > > > On 2/6/2021 4:59 AM, Chris Wilson wrote: > > Is there any reason at all to use the batch and not just emit directly > > into the ring? The command sequence is short. And you probably want to > > disable arbitr

Re: [Intel-gfx] [PATCH 09/31] drm/i915: Replace priolist rbtree with a skiplist

2021-02-08 Thread Chris Wilson
Quoting Tvrtko Ursulin (2021-02-08 15:23:17) > > On 08/02/2021 10:52, Chris Wilson wrote: > > static struct list_head * > > lookup_priolist(struct i915_sched *se, int prio) > > { > > - struct i915_priolist *p; > > - struct rb_node **pare

Re: [Intel-gfx] [PATCH 10/31] drm/i915: Fair low-latency scheduling

2021-02-08 Thread Chris Wilson
Quoting Tvrtko Ursulin (2021-02-08 16:03:03) > > On 08/02/2021 15:29, Chris Wilson wrote: > > Quoting Tvrtko Ursulin (2021-02-08 14:56:31) > >> On 08/02/2021 10:52, Chris Wilson wrote: > >>> +static bool need_preempt(const struct intel_engine_cs *engine, > >

[Intel-gfx] [PATCH] drm/i915: Remove unused debug functions

2021-02-08 Thread Chris Wilson
Remove or hide unused debug functions from clang, or else it moans. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_sw_fence.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_sw_fence.c b/drivers/gpu/drm/i915/i915_sw_fence.c index

Re: [Intel-gfx] [PATCH 10/31] drm/i915: Fair low-latency scheduling

2021-02-08 Thread Chris Wilson
Quoting Tvrtko Ursulin (2021-02-08 14:56:31) > On 08/02/2021 10:52, Chris Wilson wrote: > > +static bool need_preempt(const struct intel_engine_cs *engine, > >const struct i915_request *rq) > > { > > const struct i915_sched *se = >

Re: [Intel-gfx] [PATCH 09/31] drm/i915: Replace priolist rbtree with a skiplist

2021-02-08 Thread Chris Wilson
Quoting Tvrtko Ursulin (2021-02-08 12:29:14) > > On 08/02/2021 10:52, Chris Wilson wrote: > > +static void remove_from_priolist(struct i915_sched *se, > > + struct i915_request *rq, > > +

[Intel-gfx] [PATCH] drm/i915/selftests: Allow the module to load even if live selftests fail

2021-02-08 Thread Chris Wilson
indicate something is amiss with the driver. But it does prevent the driver being used even with a minor fault, and so prevent further inspection of the driver state afterwards. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/selftests/i915_selftest.c | 18 +- 1 file changed

[Intel-gfx] [PATCH 14/31] drm/i915: Move saturated workload detection back to the context

2021-02-08 Thread Chris Wilson
the semaphores to lightly utilised system where the latency between requests is more noticeable, and curtail the bus-contention from checking for signaled semaphores. References: 44d89409a12e ("drm/i915: Make the semaphore saturation mask global") Signed-off-by: Chris Wilson --- drive

[Intel-gfx] [PATCH 03/31] drm/i915: Introduce the scheduling mode

2021-02-08 Thread Chris Wilson
-off-by: Chris Wilson --- drivers/gpu/drm/i915/gt/intel_engine.h| 7 +++ drivers/gpu/drm/i915/gt/intel_engine_cs.c | 1 + drivers/gpu/drm/i915/gt/intel_engine_types.h | 19 +++- drivers/gpu/drm/i915/gt/intel_engine_user.c | 34 +-- .../drm/i915/gt

[Intel-gfx] [PATCH 10/31] drm/i915: Fair low-latency scheduling

2021-02-08 Thread Chris Wilson
pecially around where we reset the deadlines. Testcase: igt/gem_exec_fair Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin --- drivers/gpu/drm/i915/Kconfig.profile | 62 +++ drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 - .../gpu/drm/i915/gt/intel_engine_heartbeat.c | 1 + drivers/gpu

[Intel-gfx] [PATCH 15/31] drm/i915: Bump default timeslicing quantum to 5ms

2021-02-08 Thread Chris Wilson
Primarily to smooth over differences with the guc backend that struggles with smaller quanta, bump the default timeslicing to 5ms from 1ms. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/Kconfig.profile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm

[Intel-gfx] [PATCH 11/31] drm/i915/gt: Specify a deadline for the heartbeat

2021-02-08 Thread Chris Wilson
to. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c | 13 + 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c index 1d0e7daa6285..47e1cd25a20e 100644

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