In the legacy ringbuffer submission, we still had an open-coded version
of intel_engine_stop_cs() with one additional verification step. Transfer
that verification to intel_engine_stop_cs() itself, and call it.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt
ast
failed with error -22
v2: More context from CI.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest
Inject a fault into the engine reset and check that the outstanding
requests are completed despite the failed reset.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 142 +++
1 file changed, 142 insertions(+)
diff --git
Quoting Daniel Vetter (2021-01-13 14:06:04)
> We have too many people abusing the struct page they can get at but
> really shouldn't in importers. Aside from that the backing page might
> simply not exist (for dynamic p2p mappings) looking at it and using it
> e.g. for mmap can also wreak the page
Quoting Daniel Vetter (2021-01-13 14:06:04)
> We have too many people abusing the struct page they can get at but
> really shouldn't in importers. Aside from that the backing page might
> simply not exist (for dynamic p2p mappings) looking at it and using it
> e.g. for mmap can also wreak the page
- 160+160
__set_pd_entry 214 69-145
clear_pd_entry 190 42-148
ring_request_alloc 2021 841 -1180
Total: Before=1605086, After=1604375, chg -0.04%
Signed-off-by: Chris Wilson
Cc
777-810
Total: Before=1605815, After=1605086, chg -0.05%
Signed-off-by: Chris Wilson
Cc: Jani Nikula
---
.../drm/i915/gt/intel_execlists_submission.c | 63 +--
1 file changed, 29 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
ast
failed with error -22
v2: More context from CI.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_heartbea
Quoting Jani Nikula (2021-01-13 14:13:17)
> Always prefer the kernel types over stdint types in i915.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Chris Wilson
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.
Hello to those that replied off group.
Tuesday, January 12, 2021
Many thanks for the replies, Time Nuts always confuses my mail app and I have
to check if replies are from an individual or via the reflector.
I eventually tracked the culprit down today. Getting on site and turning off
all
Quoting Mika Kuoppala (2021-01-13 14:13:57)
> Chris Wilson writes:
>
> > Since we are system_highpri_wq, we expected the heartbeat to be
> > scheduled promptly. However, we see delays of over 10ms upsetting our
> > assertions. Accept this as inevitable and bump the err
Since we are system_highpri_wq, we expected the heartbeat to be
scheduled promptly. However, we see delays of over 10ms upsetting our
assertions. Accept this as inevitable and bump the error threshold to
20ms (from 6ms).
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt
Since we are system_highpri_wq, we expected the heartbeat to be
scheduled promptly. However, we see delays of over 10ms upsetting our
assertions. Accept this as inevitable and bump the error threshold to
20ms (from 6ms).
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt
we are able to acquire a strong reference to it.
We do not need the signal->lock crutch anymore, nor want the contention.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_request.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/g
Take a snapshot of the ctx->engines, so we can avoid taking the
ctx->engines_mutex for a mere read in get_engines().
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 39 +
1 file changed, 8 insertions(+), 31 deletions(-)
diff --git a/drive
Since schedule-in/out is now entirely serialised by the tasklet bitlock,
we do not need to worry about concurrent in/out operations and so reduce
the atomic operations to plain instructions.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 2 +-
drivers/gpu
When we know that we are inside the timeline mutex, or inside the
submission flow (under active.lock or the holder's rcu lock), we know
that the rq->hwsp is stable and we can use the simpler direct version.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_context.c |
Lift the busy-stats context-in/out implementation out of intel_lrc, so
that we can reuse it for other scheduler implementations.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine_stats.h | 49 +++
.../drm/i915/gt/intel_execlists_submission.c | 34
Avoid the full blown memory barrier of test_and_set_bit() by noting the
completed request and removing it from the lists.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_request.c | 16 +---
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915
src->engine_mutex, so long as we verify that nothing changed under the
read.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 24 +
1 file changed, 15 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/g
As context-in/out is now always serialised, we do not have to worry
about concurrent enabling/disable of the busy-stats and can reduce the
atomic_t active to a plain unsigned int, and the seqlock to a seqcount.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 8
.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_gt_pm.c| 34 ++--
drivers/gpu/drm/i915/gt/intel_gt_types.h | 5
2 files changed, 8 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
b/drivers/gpu/drm/i915/gt
.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 33 ++--
drivers/gpu/drm/i915/gt/intel_engine_stats.h | 24 +++---
drivers/gpu/drm/i915/gt/intel_engine_types.h | 5 ---
3 files changed, 14 insertions(+), 48 deletions(-)
diff --git
in some way please? I can't think of any other 10Mhz source at the
location. Thanks and a belated happy and healthy New Year to all.
The Kiwi can be accessed at:
http://82.70.254.222:8073/
--
Best Regards,
Chris Wilson.
mailto: ch...@chriswilson.tv
Quoting Matthew Auld (2021-01-12 17:26:41)
> On Tue, 12 Jan 2021 at 17:23, Jani Nikula wrote:
> >
> > There are no users outside of intel_region_lmem.c.
> >
> > Signed-off-by: Jani Nikula
> Reviewed-by: Matthew Auld
I pushed this and its companion, and then applied Matthew's git mv.
Thanks,
Quoting Matthew Auld (2021-01-12 16:43:00)
> Device local-memory should be thought of as part the GT, which means it
> should also sit under gt/.
>
> Suggested-by: Chris Wilson
> Signed-off-by: Matthew Auld
No significant change, yet.
Reviewed-by: Chris
Quoting Mika Kuoppala (2021-01-12 17:07:13)
> > + if (count & 1) {
> > + err = intel_engine_reset(engine, NULL);
> > + if (err) {
> > + GEM_TRACE_ERR("intel_engine_reset(%s)
> > failed,
Quoting Mika Kuoppala (2021-01-12 19:19:34)
> Chris Wilson writes:
>
> > In our tests where we measure the elapsed time on both the CPU and CS
> > using a udelay, our CS results match the udelay much more accurately
> > than the ktime (even when using ktime_get_f
Inject a fault into the engine reset and check that the outstanding
requests are completed despite the failed reset.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 133 +++
1 file changed, 133 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt
. The explicit MI_ARB_CHECK
should always ensure that there is at least one arbitration point in the
request before the MI_SEMAPHORE_WAIT to trigger the IDLE->ACTIVE event.
Upon processing that event, we will clear the stop-ring flag and release
the semaphore from its busywait.
Signed-off-by: Chris Wil
event.
v2: More commentary about the users of i915_request_started() as a
reminder about why we are marking the initial breadcrumb.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 23 +--
1 file changed, 17 insertions
-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/selftests/huge_gem_object.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_gem_object.c
b/drivers/gpu/drm/i915/gem/selftests/huge_gem_object.c
index a768ec61e966..2fb501a78a85 100644
stack+0x12/0x20
<4> [431.682214] ---[ end trace 5d3bcd818e2e3816 ]---
<3> [431.686188] [drm:drm_mm_takedown] *ERROR* node [0002d000 + 4000]:
inserted at
drm_mm_insert_node_in_range+0x34a/0x5b0
i915_gem_stolen_insert_node_in_range+0x7b/0xa0 [i915]
_i915_gem_object_create
just the clear-residuals mitigation (on Ivybridge, Baytrail,
or Haswell) use the module parameter: i915.mitigations=auto,!residuals
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/1858
Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
Signed-off-by: Chris
The mitigation is required for all gen7 platforms, now that it does not
cause GPU hangs, restore it for Ivybridge and Baytrail.
Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Prathap Kumar Valsan
Cc: Akeem G
: STATE_CACHE_INVALIDATE requires a stall on Ivybridge
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2024
Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Prathap Kumar Valsan
Cc: Akeem G Abodunrin
Cc: Jon Bloo
Quoting Tvrtko Ursulin (2021-01-11 17:12:57)
>
> On 11/01/2021 16:27, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2021-01-11 16:19:40)
> >>
> >> On 11/01/2021 10:57, Chris Wilson wrote:
> >>> During igt_reset_nop_engine, it was observed that an unexp
Quoting Abodunrin, Akeem G (2021-01-11 20:58:42)
>
>
> > -Original Message-
> > From: Intel-gfx On Behalf Of Chris
> > Wilson
> > Sent: Sunday, January 10, 2021 7:04 AM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: sta...@vger.kernel.org; Chr
Quoting Abodunrin, Akeem G (2021-01-11 20:25:34)
> > static void
> > batch_get_defaults(struct drm_i915_private *i915, struct batch_vals *bv) {
> > if (IS_HASWELL(i915)) {
> > - bv->max_primitives = 280;
> > - bv->max_urb_entries = MAX_URB_ENTRIES;
> > +
Quoting Rodrigo Vivi (2021-01-11 17:35:12)
> On Sun, Jan 10, 2021 at 03:03:54PM +0000, Chris Wilson wrote:
> > MEDIA_STATE_VFE only accepts the 'maximum number of threads' in the
> > range [0, n-1] where n is #EU * (#threads/EU) with the number of threads
> > based on plaform
Quoting Tvrtko Ursulin (2021-01-11 16:19:40)
>
> On 11/01/2021 10:57, Chris Wilson wrote:
> > During igt_reset_nop_engine, it was observed that an unexpected failed
> > engine reset lead to us busywaiting on the stop-ring semaphore (set
> > during the reset preparatio
Quoting Tvrtko Ursulin (2021-01-11 16:03:48)
>
> On 11/01/2021 10:57, Chris Wilson wrote:
> > On the off chance that we need to arbitrate before launching the
> > payload, perform the check after we signal the request is ready to
> > start. Assuming instantaneous pr
Quoting Tvrtko Ursulin (2021-01-11 15:53:47)
>
> On 11/01/2021 10:57, Chris Wilson wrote:
> > Braswell's pdp workaround is full of dragons, that may be being angered
> > when they are interrupted. Let's not take that risk and disable
> > arbitrartion during the upd
Quoting Patchwork (2021-01-11 14:52:15)
> == Series Details ==
>
> Series: drm/i915/selftests: Fix some error codes (rev2)
> URL : https://patchwork.freedesktop.org/series/85704/
> State : failure
>
> == Summary ==
>
> Applying: drm/i915: selftest_lrc: Fix error code in live_preempt_user()
>
reate_gpr_client(engine, global,
>NUM_GPR * i * sizeof(u32));
> - if (IS_ERR(rq))
> + if (IS_ERR(rq)) {
> + err = PTR_ERR(rq);
> goto en
MI_SEMAPHORE_WAIT would itself act as an arbitration point.
It did not in this circumstance, so force it.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
b/drivers
event.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 2e36e0a9d8a6..9a182652a35e 100644
During igt_reset_nop_engine, an engine reset unexpectedly failed. For the
next time this happens, mention which engine that was.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm
Braswell's pdp workaround is full of dragons, that may be being angered
when they are interrupted. Let's not take that risk and disable
arbitrartion during the update.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 11 ++-
1 file changed, 10
: https://gitlab.freedesktop.org/drm/intel/-/issues/1858
Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Jon Bloomfield
Cc: Rodrigo Vivi
Cc: sta...@vger.kernel.org # v5.7
---
drivers/gpu/drm/i91
: STATE_CACHE_INVALIDATE requires a stall on Ivybridge
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2024
Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Prathap Kumar Valsan
Cc: Akeem G Abodunrin
Cc: Jon Bloo
The mitigation is required for all gen7 platforms, now that it does not
cause GPU hangs, restore it for Ivybridge and Baytrail.
Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Prathap Kumar Valsan
Cc: Akeem G
as how to unravel some global state that appears to
be reset along with an engine (in particular the ppgtt enabling in
GFX_MODE).
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_pci.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c
The GFX_MODE is reset along with the engine, turning off ppGTT. We need
to re-enable it upon resume.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/gen6_ppgtt.c| 9 -
drivers/gpu/drm/i915/gt/intel_ring_submission.c | 13 ++---
2 files changed, 10 insertions
The engine resets selftests kick the tasklets, safe up until now as only
execlists supported engine resets.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 18 ++
drivers/gpu/drm/i915/gt/selftest_reset.c | 11 ---
2 files changed, 22
Push the sleeping stop_ring() out of the reset resume function to reset
prepare; we are not allowed to sleep in the former.
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gt/intel_ring_submission.c | 97 +++
1 file changed, 36 insertions(+), 61 deletions(-)
diff --git
Take advantage of calling xcs_resume under a forcewake by using direct
mmio access. In particular, we can avoid the sleeping variants to allow
resume to be called from softirq context, required for engine resets.
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gt/intel_ring_submission.c | 96
In the legacy ringbuffer submission, we still had an open-coded version
of intel_engine_stop_cs() with one addition verification step. Transfer
that verification to intel_engine_stop_cs() itself, and call it.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 15
Some rcs0 workarounds were being incorrectly applied to the GT, and so
we failed to restore the expected register settings after a reset.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 122
1 file changed, 49 insertions(+), 73 deletions
Some rcs0 workarounds were being incorrectly applied to the GT, and so
we failed to restore the expected register settings after a reset.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 95 +++--
1 file changed, 51 insertions(+), 44 deletions
event.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 2e36e0a9d8a6..9a182652a35e 100644
MI_SEMAPHORE_WAIT would itself act as an arbitration point.
It did not in this circumstance, so force it.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
b/drivers
During igt_reset_nop_engine, an engine reset unexpectedly failed. For the
next time this happens, mention which engine that was.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm
When wedging the device, we cancel all outstanding requests and mark
them as EIO. Rather than duplicate the small function to do so between
each submission backend, export one.
Signed-off-by: Chris Wilson
Cc: Andi Shyti
Reviewed-by: Andi Shyti
---
.../drm/i915/gt/intel_execlists_submission.c
>> drivers/gpu/drm/i915/gt/intel_lrc.c:17:28: error: unused function
>> 'dword_in_page' [-Werror,-Wunused-function]
static inline unsigned int dword_in_page(void *addr)
Reported-by: kernel test robot
Signed-off-by: Chris Wilson
Reviewed-by: Andi Shyti
---
drivers/gpu
to keep the
compiler from complaining.
Signed-off-by: Chris Wilson
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index c21a9726326a
: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Jon Bloomfield
Cc: Rodrigo Vivi
Cc: sta...@vger.kernel.org # v5.7
---
drivers/gpu/drm/i915/Makefile | 1 +
.../gpu/drm/i915/gt/intel_ring_submission
: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Jon Bloomfield
Cc: Rodrigo Vivi
Cc: sta...@vger.kernel.org # v5.7
---
drivers/gpu/drm/i915/Makefile | 1 +
.../gpu/drm/i915/gt/intel_ring_submission
("drm/i915/gen7: Clear all EU/L3 residual contexts")
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Prathap Kumar Valsan
Cc: Akeem G Abodunrin
Cc: Jon Bloomfield
Cc: Rodrigo Vivi
Cc: Randy Wright
Cc: sta...@vger.kernel.org # v5.7+
---
drivers/gpu/drm/i915/gt/gen7_rendercl
The mitigation is required for all gen7 platforms, now that it does not
cause GPU hangs, restore it for Ivybridge and Baytrail.
Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Prathap Kumar Valsan
Cc: Akeem G
Inject a fault into lrc_init_wa_ctx() to ensure that we can tolerate a
failure to construct the workarounds.
v2: Avoid mentioning an error for fault-injection, other CI will
complain about the dmesg spam.
Signed-off-by: Chris Wilson
Cc: Matt Roper
Reviewed-by: Matt Roper
---
.../drm/i915/gt
to keep the
compiler from complaining.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index c21a9726326a..c52433914d52 100644
Quoting Hans de Goede (2021-01-05 15:25:56)
> Hi,
>
> On 1/4/21 9:39 PM, Chris Wilson wrote:
> > As with the regular suspend paths, also disable the wakeref assertions
> > as we disable the driver during shutdown.
> >
> > Reported-by: Hans de Goede
> > Clo
>> drivers/gpu/drm/i915/gt/intel_lrc.c:17:28: error: unused function
>> 'dword_in_page' [-Werror,-Wunused-function]
static inline unsigned int dword_in_page(void *addr)
Reported-by: kernel test robot
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 5 -
Inject a fault into lrc_init_wa_ctx() to ensure that we can tolerate a
failure to construct the workarounds.
Signed-off-by: Chris Wilson
Cc: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers
remaining ce->signals
Fixes: bab0557c8dca ("drm/i915/gt: Remove virtual breadcrumb before transfer")
Signed-off-by: Chris Wilson
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 33 +++
drivers/gpu/drm/i915/gt/intel_breadcrumbs.h
If any of the perf tests run into 0 time, not only are we liable to
divide by zero, but the result would be highly questionable.
Nevertheless, let's not have a div-by-zero error.
Signed-off-by: Chris Wilson
Cc: Andi Shyti
Reviewed-by: Andi Shyti
---
.../drm/i915/selftests
If a request is submitted and known to require no preemption, disable
arbitration around the batch which prevents the HW from handling a
preemption request during the payload.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Matthew Brost
Cc: Lionel Landwerlin
Reviewed-by: Andi Shyti
on whether to use
timeslicing and semaphores between individual engines.
Signed-off-by: Chris Wilson
Reviewed-by: Andi Shyti
---
.../drm/i915/gt/intel_execlists_submission.c | 11 -
drivers/gpu/drm/i915/gt/selftest_execlists.c | 40 +++
drivers/gpu/drm/i915/i915_drv.h
://gitlab.freedesktop.org/drm/intel/-/issues/2919
Signed-off-by: Chris Wilson
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
b/drivers/gpu/drm/i915/gt
for legacy ringbuffer
submission.
Signed-off-by: Chris Wilson
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 10 +-
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 +-
drivers/gpu/drm/i915/gt/intel_timeline.h | 7 +++
3 files
-by: Matt Roper
Fixes: 604a8f6f1e33 ("drm/i915/lrc: Only enable per-context and per-bb buffers
if set")
Signed-off-by: Chris Wilson
Cc: Matt Roper
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
Cc: # v4.15+
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 3 +++
1 file
Quoting Andi Shyti (2021-01-08 15:18:22)
> Hi Chris,
>
> > +void intel_context_remove_breadcrumbs(struct intel_context *ce,
> > + struct intel_breadcrumbs *b)
> > +{
> > + struct i915_request *rq, *rn;
> > + bool release = false;
> > + unsigned long
If any of the perf tests run into 0 time, not only are we liable to
divide by zero, but the result would be highly questionable.
Nevertheless, let's not have a div-by-zero error.
Signed-off-by: Chris Wilson
Cc: Andi Shyti
---
.../drm/i915/selftests/intel_memory_region.c | 20
-by: Matt Roper
Fixes: 604a8f6f1e33 ("drm/i915/lrc: Only enable per-context and per-bb buffers
if set")
Signed-off-by: Chris Wilson
Cc: Matt Roper
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
Cc: # v4.15+
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 3 +++
1 file changed, 3 insertions(+)
Verify that we do not run a later request before its dependency on the
same engine, even if the linkage is looped around all the other engines.
Signed-off-by: Chris Wilson
---
tests/i915/gem_exec_schedule.c | 117 +
1 file changed, 117 insertions(+)
diff --git
Quoting Andi Shyti (2021-01-08 13:51:54)
> Hi Chris,
>
> > > > diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
> > > > b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
> > > > index 75839db63bea..59c58a276677 100644
> > > > ---
If any of the perf tests run into 0 time, not only are we liable to
divide by zero, but the result would be highly questionable.
Nevertheless, let's not have a div-by-zero error.
Signed-off-by: Chris Wilson
Cc: Andi Shyti
---
drivers/gpu/drm/i915/selftests/intel_memory_region.c | 3 +++
1 file
Quoting Andi Shyti (2021-01-08 12:26:45)
> Hi Chris,
>
> > diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
> > b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
> > index 75839db63bea..59c58a276677 100644
> > --- a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
> >
://gitlab.freedesktop.org/drm/intel/-/issues/2919
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
index
Combine our per-engine metrics to track begin/end of the class as a
whole and present that as culmulative runtime via PMU.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 18 +++
drivers/gpu/drm/i915/gt
If a request is submitted and known to require no preemption, disable
arbitration around the batch which prevents the HW from handling a
preemption request during the payload.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Matthew Brost
Cc: Lionel Landwerlin
---
drivers/gpu/drm/i915/gem
on whether to use
timeslicing and semaphores between individual engines.
Signed-off-by: Chris Wilson
---
.../drm/i915/gt/intel_execlists_submission.c | 11 -
drivers/gpu/drm/i915/gt/selftest_execlists.c | 40 +++
drivers/gpu/drm/i915/i915_drv.h | 2 -
drivers/gpu
If any of the perf tests run into 0 time, not only are we liable to
divide by zero, but the result would be highly questionable.
Nevertheless, let's not have a div-by-zero error.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/intel_memory_region.c | 3 +++
1 file changed, 3
remaining ce->signals
Fixes: bab0557c8dca ("drm/i915/gt: Remove virtual breadcrumb before transfer")
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 33 +++
drivers/gpu/drm/i915/gt/intel_breadcrumbs.h | 4 +++
.../drm/i915/gt/intel_ex
submission.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
index 7137b6f24f55..6996e22ba65b
Quoting Rodrigo Vivi (2021-01-07 19:50:37)
> On Fri, Oct 16, 2020 at 06:54:11PM +0100, Chris Wilson wrote:
> > MEDIA_STATE_VFE only accepts the 'maximum number of threads' in the
> > range [0, n-1] where n is #EU * (#threads/EU) with the number of threads
> > based on plaform
Quoting Matthew Brost (2021-01-07 16:05:07)
> On Tue, Dec 29, 2020 at 12:01:25PM +0000, Chris Wilson wrote:
> > The first "scheduler" was a topographical sorting of requests into
> > priority order. The execution order was deterministic, the earliest
> > submitted,
: Commentary for the right cancel_timer()
v4: Add tracing for why we need a timeslice
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2802
Testcase: igt/gem_exec_balancer/fairslice
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Andi Shyti
Reviewed-by: Tvrtko Ursulin
: Commentary for the right cancel_timer()
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2802
Testcase: igt/gem_exec_balancer/fairslice
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_engine_types.h | 10 -
.../drm/i915/gt
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