[clang] [llvm] Reapply "InstCombine: Introduce SimplifyDemandedUseFPClass"" (PR #74056)

@@ -1877,3 +1877,139 @@ Value *InstCombinerImpl::SimplifyDemandedVectorElts(Value *V, return MadeChange ? I : nullptr; } + +/// For floating-point classes that resolve to a single bit pattern, return that +/// value. +static Constant *getFPClassConstant(Type *Ty, FPClassTe

[clang] [llvm] Reapply "InstCombine: Introduce SimplifyDemandedUseFPClass"" (PR #74056)

@@ -1877,3 +1877,139 @@ Value *InstCombinerImpl::SimplifyDemandedVectorElts(Value *V, return MadeChange ? I : nullptr; } + +/// For floating-point classes that resolve to a single bit pattern, return that +/// value. +static Constant *getFPClassConstant(Type *Ty, FPClassTe

[clang] [llvm] Reapply "InstCombine: Introduce SimplifyDemandedUseFPClass"" (PR #74056)

@@ -1877,3 +1877,139 @@ Value *InstCombinerImpl::SimplifyDemandedVectorElts(Value *V, return MadeChange ? I : nullptr; } + +/// For floating-point classes that resolve to a single bit pattern, return that +/// value. +static Constant *getFPClassConstant(Type *Ty, FPClassTe

[clang] [llvm] Reapply "InstCombine: Introduce SimplifyDemandedUseFPClass"" (PR #74056)

@@ -1877,3 +1877,139 @@ Value *InstCombinerImpl::SimplifyDemandedVectorElts(Value *V, return MadeChange ? I : nullptr; } + +/// For floating-point classes that resolve to a single bit pattern, return that +/// value. +static Constant *getFPClassConstant(Type *Ty, FPClassTe

[clang] [llvm] [transforms] Inline simple variadic functions (PR #81058)

@@ -0,0 +1,698 @@ +//===-- ExpandVariadicsPass.cpp *- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache

[clang] [llvm] [transforms] Inline simple variadic functions (PR #81058)

@@ -0,0 +1,698 @@ +//===-- ExpandVariadicsPass.cpp *- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache

[clang] [llvm] [transforms] Inline simple variadic functions (PR #81058)

@@ -0,0 +1,698 @@ +//===-- ExpandVariadicsPass.cpp *- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache

[clang] [llvm] [transforms] Inline simple variadic functions (PR #81058)

@@ -0,0 +1,698 @@ +//===-- ExpandVariadicsPass.cpp *- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache

[clang] [llvm] [transforms] Inline simple variadic functions (PR #81058)

@@ -0,0 +1,698 @@ +//===-- ExpandVariadicsPass.cpp *- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache

[clang] [llvm] [transforms] Inline simple variadic functions (PR #81058)

@@ -0,0 +1,589 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: -p --function-signature +; RUN: opt -S --passes=expand-variadics < %s | FileCheck %s +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:

[clang] [llvm] [transforms] Inline simple variadic functions (PR #81058)

@@ -0,0 +1,698 @@ +//===-- ExpandVariadicsPass.cpp *- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache

[clang] [llvm] [transforms] Inline simple variadic functions (PR #81058)

@@ -0,0 +1,589 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: -p --function-signature +; RUN: opt -S --passes=expand-variadics < %s | FileCheck %s +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:

[clang] [llvm] [transforms] Inline simple variadic functions (PR #81058)

@@ -0,0 +1,698 @@ +//===-- ExpandVariadicsPass.cpp *- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache

[clang] [llvm] [transforms] Inline simple variadic functions (PR #81058)

@@ -0,0 +1,698 @@ +//===-- ExpandVariadicsPass.cpp *- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache

[clang] [llvm] [transforms] Inline simple variadic functions (PR #81058)

@@ -0,0 +1,698 @@ +//===-- ExpandVariadicsPass.cpp *- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache

[clang] [llvm] [transforms] Inline simple variadic functions (PR #81058)

@@ -0,0 +1,589 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: -p --function-signature +; RUN: opt -S --passes=expand-variadics < %s | FileCheck %s +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:

[clang] [llvm] [transforms] Inline simple variadic functions (PR #81058)

@@ -0,0 +1,117 @@ +// RUN: %clang_cc1 -triple i386-unknown-linux-gnu -Wno-varargs -O1 -disable-llvm-passes -emit-llvm -o - %s | opt --passes=instcombine | opt -passes="expand-variadics,default" -S | FileCheck %s --check-prefixes=CHECK,X86Linux arsenm wrote: ca

[clang] [llvm] [transforms] Inline simple variadic functions (PR #81058)

@@ -0,0 +1,273 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py + +// REQUIRES: x86-registered-target +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -target-cpu x86-64-v4 -std=c23 -O1 -ffreestanding -emit-llvm -o - %s | FileCheck %s + +// Th

[clang] [llvm] Reapply "InstCombine: Introduce SimplifyDemandedUseFPClass"" (PR #74056)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/74056 >From 9be777d5b39852cf3c0b2538fd5f712922672caa Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Fri, 1 Dec 2023 18:00:13 +0900 Subject: [PATCH 1/4] Reapply "InstCombine: Introduce SimplifyDemandedUseFPClass""

[clang] [llvm] Reapply "InstCombine: Introduce SimplifyDemandedUseFPClass"" (PR #74056)

https://github.com/arsenm closed https://github.com/llvm/llvm-project/pull/74056 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] InstCombine: Enable SimplifyDemandedUseFPClass and remove flag (PR #81108)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/81108 This completes the unrevert of ef388334ee5a3584255b9ef5b3fefdb244fa3fd7. >From 7b5b50597e13c647ec70beab35dcc9b643bff42f Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 8 Feb 2024 14:15:33 +0530 Subject:

[clang] [llvm] Reapply "InstCombine: Introduce SimplifyDemandedUseFPClass"" (PR #74056)

arsenm wrote: Next piece in #81108 https://github.com/llvm/llvm-project/pull/74056 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RFC][WIP][AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)

@@ -1562,8 +1562,9 @@ bool IRTranslator::translateBitCast(const User &U, bool IRTranslator::translateCast(unsigned Opcode, const User &U, MachineIRBuilder &MIRBuilder) { - if (U.getType()->getScalarType()->isBFloatTy() || - U.getOperand(0

[clang] [llvm] [RFC][WIP][AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)

@@ -0,0 +1,8 @@ +// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck %s +// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -show-encoding %s | FileCheck %s + +v_dot2_bf16_bf16 v5, v1, v2, 100.0 arsenm wrote: does this help with #79369 at all? http

[clang] [llvm] [RFC][WIP][AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)

@@ -1562,8 +1562,9 @@ bool IRTranslator::translateBitCast(const User &U, bool IRTranslator::translateCast(unsigned Opcode, const User &U, MachineIRBuilder &MIRBuilder) { - if (U.getType()->getScalarType()->isBFloatTy() || - U.getOperand(0

[clang] [llvm] [RFC][WIP][AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)

@@ -2835,8 +2835,8 @@ def int_amdgcn_fdot2_f32_bf16 : DefaultAttrsIntrinsic< [llvm_float_ty], // %r [ - llvm_v2i16_ty, // %a - llvm_v2i16_ty, // %b + llvm_v2bf16_ty, // %a + llvm_v2bf16_ty, // %b arsenm wrote: For potential revert

[clang] [llvm] [RFC][WIP][AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)

@@ -2819,11 +2819,11 @@ def int_amdgcn_fdot2_f16_f16 : def int_amdgcn_fdot2_bf16_bf16 : ClangBuiltin<"__builtin_amdgcn_fdot2_bf16_bf16">, DefaultAttrsIntrinsic< -[llvm_i16_ty], // %r +[llvm_bfloat_ty], // %r arsenm wrote: Changing the clang bui

[clang] [llvm] [AMDGPU] Introduce GFX9/10.1/10.3/11 Generic Targets (PR #76955)

https://github.com/arsenm commented: I think this needs codegen tests for the gfx900 vs. gfx906 mad_mix/fma_fix issue https://github.com/llvm/llvm-project/pull/76955 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-b

[clang] [llvm] [AMDGPU] Emit a waitcnt instruction after each memory instruction (PR #79236)

@@ -0,0 +1,199 @@ +; Testing the -amdgpu-precise-memory-op option +; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=+amdgpu-precise-memory-op -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GFX9 +; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -mattr=+amdgpu-precise-memory-op -v

[clang] [llvm] [AMDGPU] Emit a waitcnt instruction after each memory instruction (PR #79236)

@@ -167,6 +167,10 @@ def FeatureCuMode : SubtargetFeature<"cumode", "Enable CU wavefront execution mode" >; +def FeaturePreciseMemory arsenm wrote: The subtarget feature prefix should be removed. The subtarget feature name is not the user facing component

[clang] [Clang] Fix a non-effective assertion (PR #81083)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/81083 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang] Fix a non-effective assertion (PR #81083)

https://github.com/arsenm edited https://github.com/llvm/llvm-project/pull/81083 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang] Fix a non-effective assertion (PR #81083)

@@ -5908,7 +5908,7 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID, } } -assert(PTy->canLosslesslyBitCastTo(FTy->getParamType(i)) && +assert(ArgValue->getType()->canLosslesslyBitCastTo(PTy) && --

[clang] [llvm] [AMDGPU] Introduce GFX9/10.1/10.3/11 Generic Targets (PR #76955)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/76955 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] LLVM] Add `__builtin_readfixedtimer` intrinsic and buiiltin for realtime clocks (PR #81331)

https://github.com/arsenm edited https://github.com/llvm/llvm-project/pull/81331 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] LLVM] Add `__builtin_readfixedtimer` intrinsic and buiiltin for realtime clocks (PR #81331)

https://github.com/arsenm commented: Missing the clang builtin test https://github.com/llvm/llvm-project/pull/81331 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] LLVM] Add `__builtin_readfixedtimer` intrinsic and buiiltin for realtime clocks (PR #81331)

@@ -3759,7 +3759,6 @@ def CALL_PROTOTYPE : include "NVPTXIntrinsics.td" - arsenm wrote: Random whitespace change https://github.com/llvm/llvm-project/pull/81331 ___ cfe-commits mailing list cfe-commits@lists.llvm

[clang] [llvm] LLVM] Add `__builtin_readfixedtimer` intrinsic and buiiltin for realtime clocks (PR #81331)

@@ -312,6 +312,12 @@ void IntrinsicLowering::LowerIntrinsicCall(CallInst *CI) { CI->replaceAllUsesWith(ConstantInt::get(Type::getInt64Ty(Context), 0)); break; } + case Intrinsic::readfixedtimer: { +errs() << "WARNING: this target does not support the llvm.readfix

[libclc] libclc: add missing AMD gfx symlinks (PR #78884)

=?utf-8?b?Wm9sdMOhbiBCw7ZzesO2cm3DqW55aQ==?= Message-ID: In-Reply-To: https://github.com/arsenm approved this pull request. can probably drop all the versioning handling here https://github.com/llvm/llvm-project/pull/78884 ___ cfe-commits mailing li

[libclc] libclc: add missing AMD gfx symlinks (PR #78884)

=?utf-8?b?Wm9sdMOhbiBCw7ZzesO2cm3DqW55aQ=?Message-ID: In-Reply-To: https://github.com/arsenm edited https://github.com/llvm/llvm-project/pull/78884 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/

[libclc] libclc: add missing AMD gfx symlinks (PR #78884)

=?utf-8?b?Wm9sdMOhbiBCw7ZzesO2cm3DqW55aQ=?Message-ID: In-Reply-To: @@ -154,6 +154,46 @@ if( ${LLVM_PACKAGE_VERSION} VERSION_GREATER "6.99.99" ) set( tahiti_aliases ${tahiti_aliases} gfx904 gfx906 ) endif() +# Support for gfx909, gfx1010, gfx1011 and gfx1012 was added

[libclc] libclc: add missing AMD gfx symlinks (PR #78884)

=?utf-8?b?Wm9sdMOhbiBCw7ZzesO2cm3DqW55aQ=?Message-ID: In-Reply-To: @@ -154,6 +154,46 @@ if( ${LLVM_PACKAGE_VERSION} VERSION_GREATER "6.99.99" ) set( tahiti_aliases ${tahiti_aliases} gfx904 gfx906 ) endif() +# Support for gfx909, gfx1010, gfx1011 and gfx1012 was added

[libclc] libclc: add missing AMD gfx symlinks (PR #78884)

=?utf-8?b?Wm9sdMOhbiBCw7ZzesO2cm3DqW55aQ=?=, =?utf-8?b?Wm9sdMOhbiBCw7ZzesO2cm3DqW55aQ=?Message-ID: In-Reply-To: https://github.com/arsenm closed https://github.com/llvm/llvm-project/pull/78884 ___ cfe-commits mailing list cfe-commits@lists.llvm.org htt

[lldb] [libcxx] [libc] [compiler-rt] [flang] [llvm] [clang] [clang-tools-extra] [lld] [AMDGPU][GFX12] VOP encoding and codegen - add support for v_cvt fp8/… (PR #78414)

https://github.com/arsenm commented: Why is so there so much special casing in the assembler/disassembler? https://github.com/llvm/llvm-project/pull/78414 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/li

[llvm] [mlir] [clang] [AMDGPU] Change default AMDHSA Code Object version to 5 (PR #79038)

arsenm wrote: Should get a mention in the release notes https://github.com/llvm/llvm-project/pull/79038 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [mlir] [llvm] [AMDGPU] Add GFX12 WMMA and SWMMAC instructions (PR #77795)

@@ -2601,67 +2601,73 @@ def int_amdgcn_ds_bvh_stack_rtn : [ImmArg>, IntrWillReturn, IntrNoCallback, IntrNoFree] >; +def int_amdgcn_s_wait_event_export_ready : + ClangBuiltin<"__builtin_amdgcn_s_wait_event_export_ready">, + Intrinsic<[], [], [IntrNoMem, IntrHasSideEffec

[compiler-rt] [libcxx] [lldb] [flang] [libc] [lld] [llvm] [clang-tools-extra] [clang] [AMDGPU][GFX12] VOP encoding and codegen - add support for v_cvt fp8/… (PR #78414)

Mirko =?utf-8?q?Brkušanin?= , Mirko =?utf-8?q?Brkušanin?= ,Mirko Brkusanin ,Mariusz Sikora Message-ID: In-Reply-To: @@ -8770,6 +8781,22 @@ void AMDGPUAsmParser::cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands, } } +int VdstInIdx = AMDGPU::getNamedOper

[libc] [flang] [clang] [clang-tools-extra] [lldb] [libcxx] [lld] [compiler-rt] [llvm] [AMDGPU][GFX12] VOP encoding and codegen - add support for v_cvt fp8/… (PR #78414)

Mirko =?utf-8?q?Brku=C5=A1anin?= , Mirko =?utf-8?q?Brku=C5=A1anin?= ,Mirko Brkusanin ,Mariusz Sikora Message-ID: In-Reply-To: https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/78414 ___ cfe-commits mail

[flang] [libc] [clang-tools-extra] [libcxx] [llvm] [clang] [compiler-rt] [lldb] [lld] [AMDGPU][GFX12] VOP encoding and codegen - add support for v_cvt fp8/… (PR #78414)

Mirko =?utf-8?q?Brkušanin?= , Mirko =?utf-8?q?Brkušanin?= ,Mirko Brkusanin ,Mariusz Sikora Message-ID: In-Reply-To: https://github.com/arsenm edited https://github.com/llvm/llvm-project/pull/78414 ___ cfe-commits mailing list cfe-commits@lists.llvm.o

[clang] [mlir] [llvm] [AMDGPU] Add GFX12 WMMA and SWMMAC instructions (PR #77795)

@@ -2601,67 +2601,73 @@ def int_amdgcn_ds_bvh_stack_rtn : [ImmArg>, IntrWillReturn, IntrNoCallback, IntrNoFree] >; +def int_amdgcn_s_wait_event_export_ready : + ClangBuiltin<"__builtin_amdgcn_s_wait_event_export_ready">, + Intrinsic<[], [], [IntrNoMem, IntrHasSideEffec

[clang] [NVPTX][AMDGPU][CodeGen] Fix `local_space nullptr` handling for NVPTX and local/private `nullptr` value for AMDGPU. (PR #78759)

@@ -418,8 +418,10 @@ class LLVM_LIBRARY_VISIBILITY AMDGPUTargetInfo final : public TargetInfo { // value ~0. uint64_t getNullPointerValue(LangAS AS) const override { // FIXME: Also should handle region. -return (AS == LangAS::opencl_local || AS == LangAS::opencl_pr

[llvm] [clang] [CodeGen] Port AtomicExpand to new Pass Manager (PR #71220)

@@ -429,6 +429,7 @@ FUNCTION_PASS("strip-gc-relocates", StripGCRelocates()) FUNCTION_PASS("structurizecfg", StructurizeCFGPass()) FUNCTION_PASS("tailcallelim", TailCallElimPass()) FUNCTION_PASS("typepromotion", TypePromotionPass(TM)) +FUNCTION_PASS("atomicexpand", AtomicExpandP

[llvm] [clang] [clang-tools-extra] [AMDGPU][GFX12] Add 16 bit atomic fadd instructions (PR #75917)

@@ -27,34 +27,23 @@ main_body: ret float %out0 } -define amdgpu_ps float @atomic_pk_add_bf16_1d_v2(<8 x i32> inreg %rsrc, <2 x i16> %data, i32 %s) { +define amdgpu_ps float @atomic_pk_add_bf16_1d_v2(<8 x i32> inreg %rsrc, <2 x bfloat> %data, i32 %s) { ; GFX12-LABEL: atomi

[llvm] [clang] [clang-tools-extra] [AMDGPU][GFX12] Add Atomic cond_sub_u32 (PR #76224)

https://github.com/arsenm commented: Missing UniformityAnalysis test for these https://github.com/llvm/llvm-project/pull/76224 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] AMDGPU/GFX12: Add new dot4 fp8/bf8 instructions (PR #77892)

@@ -2696,6 +2696,25 @@ def int_amdgcn_udot8 : ImmArg>, ImmArg>, ImmArg>] >; +// f32 %r = llvm.amdgcn.dot4.f32.type_a.type_b (v4type_a (as i32) %a, v4type_b (as i32) %b, f32 %c) +// %r = %a[0] * %b[0] + %a[1] * %b[1] + %a[2] * %b[2] + %a[3] * %b[3] + %c +class AMDGPU

[clang-tools-extra] [llvm] [clang] [AMDGPU][GFX12] Add Atomic cond_sub_u32 (PR #76224)

@@ -2502,10 +2500,9 @@ def int_amdgcn_flat_atomic_fmax_num : AMDGPUAtomicRtn; def int_amdgcn_global_atomic_fmin_num : AMDGPUAtomicRtn; def int_amdgcn_global_atomic_fmax_num : AMDGPUAtomicRtn; -def int_amdgcn_flat_atomic_cond_sub_u32 : AMDGPUAtomicRtn; -def int_amdgcn_global

[llvm] [clang] [AMDGPU] Add global_load_tr for GFX12 (PR #77772)

@@ -18178,6 +18178,51 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned BuiltinID, llvm::Function *F = CGM.getIntrinsic(IID, {ArgTy}); return Builder.CreateCall(F, {Addr, Val, ZeroI32, ZeroI32, ZeroI1}); } + case AMDGPU::BI__builtin_amdgcn_global_load_tr_b64

[llvm] [clang] [AMDGPU] Add global_load_tr for GFX12 (PR #77772)

@@ -18178,6 +18178,51 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned BuiltinID, llvm::Function *F = CGM.getIntrinsic(IID, {ArgTy}); return Builder.CreateCall(F, {Addr, Val, ZeroI32, ZeroI32, ZeroI1}); } + case AMDGPU::BI__builtin_amdgcn_global_load_tr_b64

[llvm] [clang] [mlir] [clang-tools-extra] [ASan][AMDGPU] Fix Assertion Failure. (PR #78242)

@@ -1254,9 +1254,11 @@ Value *AddressSanitizer::memToShadow(Value *Shadow, IRBuilder<> &IRB) { void AddressSanitizer::instrumentMemIntrinsic(MemIntrinsic *MI) { InstrumentationIRBuilder IRB(MI); if (isa(MI)) { -IRB.CreateCall(isa(MI) ? AsanMemmove : AsanMemcpy, -

[llvm] [clang] [LinkerWrapper] Handle AMDGPU Target-IDs correctly when linking (PR #78359)

@@ -162,6 +162,19 @@ class OffloadFile : public OwningBinary { std::unique_ptr Buffer) : OwningBinary(std::move(Binary), std::move(Buffer)) {} + /// Make a deep copy of this offloading file. + OffloadFile copy() const { +std::unique_ptr Buffer = Memor

[libc] [clang] [compiler-rt] [clang-tools-extra] [libcxxabi] [libunwind] [lldb] [mlir] [flang] [llvm] [libcxx] [ASan][AMDGPU] Fix Assertion Failure. (PR #78242)

@@ -0,0 +1,48 @@ +;RUN: opt < %s -passes=asan -S | FileCheck %s + +target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-

[libc] [clang] [compiler-rt] [clang-tools-extra] [lld] [lldb] [flang] [llvm] [libcxx] [AMDGPU] Use alias info to relax waitcounts for LDS DMA (PR #74537)

https://github.com/arsenm edited https://github.com/llvm/llvm-project/pull/74537 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[lldb] [llvm] [libcxx] [clang-tools-extra] [compiler-rt] [clang] [lld] [libc] [flang] [AMDGPU] Use alias info to relax waitcounts for LDS DMA (PR #74537)

@@ -707,7 +723,40 @@ void WaitcntBrackets::updateByEvent(const SIInstrInfo *TII, (TII->isDS(Inst) || TII->mayWriteLDSThroughDMA(Inst))) { // MUBUF and FLAT LDS DMA operations need a wait on vmcnt before LDS // written can be accessed. A load from LDS to VMEM

[clang] [compiler-rt] [lld] [libc] [libcxx] [llvm] [clang-tools-extra] [lldb] [flang] [AMDGPU] Use alias info to relax waitcounts for LDS DMA (PR #74537)

https://github.com/arsenm approved this pull request. lgtm, but can still fix the -O0 thing https://github.com/llvm/llvm-project/pull/74537 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-com

[clang] [lldb] [clang-tools-extra] [llvm] [flang] [lld] [compiler-rt] [libcxx] [libc] [AMDGPU] Use alias info to relax waitcounts for LDS DMA (PR #74537)

@@ -130,6 +130,8 @@ ; GCN-O0-NEXT:MachineDominator Tree Construction ; GCN-O0-NEXT:Machine Natural Loop Construction ; GCN-O0-NEXT:MachinePostDominator Tree Construction +; GCN-O0-NEXT:Basic Alias Analysis (stateless AA impl) +; GCN-O0-NEXT:

[clang] [clang][ExprConst] allow single element access of vector object to be constant expression (PR #72607)

@@ -437,6 +442,16 @@ namespace { MostDerivedArraySize = 2; MostDerivedPathLength = Entries.size(); } +void addVectorUnchecked(QualType EltTy, uint64_t Size, uint64_t Idx) { + Entries.push_back(PathEntry::ArrayIndex(Idx)); + + // This is technically

[clang-tools-extra] [clang] [llvm] [AMDGPU][GFX12] Add Atomic cond_sub_u32 (PR #76224)

@@ -1182,6 +1182,11 @@ The AMDGPU backend implements the following LLVM IR intrinsics. The iglp_opt strategy implementations are subject to change. + llvm.atomic.cond.sub.u32 Provides direct access

[clang] [llvm] [AMDGPU] Add GFX12 WMMA and SWMMAC instructions (PR #77795)

@@ -423,6 +423,67 @@ TARGET_BUILTIN(__builtin_amdgcn_s_wakeup_barrier, "vi", "n", "gfx12-insts") TARGET_BUILTIN(__builtin_amdgcn_s_barrier_leave, "b", "n", "gfx12-insts") TARGET_BUILTIN(__builtin_amdgcn_s_get_barrier_state, "Uii", "n", "gfx12-insts") +//===---

[clang-tools-extra] [llvm] [clang] DAG: Fix ABI lowering with FP promote in strictfp functions (PR #74405)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/74405 >From cdafeff37cd20e8cb8cdcf6ac8561455d5c9a30a Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Sat, 2 Dec 2023 20:49:51 +0700 Subject: [PATCH] DAG: Fix ABI lowering with FP promote in strictfp functions This

[clang] [llvm] [AMDGPU] Add InstCombine rule for ballot.i64 intrinsic in wave32 mode. (PR #71556)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/71556 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [AMDGPU] Add InstCombine rule for ballot.i64 intrinsic in wave32 mode. (PR #71556)

https://github.com/arsenm closed https://github.com/llvm/llvm-project/pull/71556 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[compiler-rt] [lldb] [flang] [clang-tools-extra] [libc] [libcxxabi] [llvm] [clang] [libunwind] [libcxx] [ASan][AMDGPU] Fix Assertion Failure. (PR #78410)

@@ -0,0 +1,23 @@ +;RUN: opt < %s -passes=asan -S | FileCheck %s + +target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-

[clang-tools-extra] [llvm] [clang] DAG: Fix ABI lowering with FP promote in strictfp functions (PR #74405)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/74405 >From cdafeff37cd20e8cb8cdcf6ac8561455d5c9a30a Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Sat, 2 Dec 2023 20:49:51 +0700 Subject: [PATCH 1/2] DAG: Fix ABI lowering with FP promote in strictfp functions

[clang] [clang-tools-extra] [llvm] DAG: Fix ABI lowering with FP promote in strictfp functions (PR #74405)

https://github.com/arsenm closed https://github.com/llvm/llvm-project/pull/74405 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [CodeGen] Port AtomicExpand to new Pass Manager (PR #71220)

https://github.com/arsenm edited https://github.com/llvm/llvm-project/pull/71220 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [CodeGen] Port AtomicExpand to new Pass Manager (PR #71220)

https://github.com/arsenm requested changes to this pull request. https://github.com/llvm/llvm-project/pull/71220 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [CodeGen] Port AtomicExpand to new Pass Manager (PR #71220)

@@ -340,7 +342,33 @@ bool AtomicExpand::runOnFunction(Function &F) { return MadeChange; } -bool AtomicExpand::bracketInstWithFences(Instruction *I, AtomicOrdering Order) { +bool AtomicExpandLegacy::runOnFunction(Function &F) { + if (skipFunction(F)) +return false;

[clang] [AMDGPU] Add GFX12 __builtin_amdgcn_s_sleep_var (PR #77926)

@@ -0,0 +1,11 @@ +// REQUIRES: amdgpu-registered-target + +// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx1100 -verify -S -emit-llvm -o - %s + +typedef unsigned int uint; +typedef uint uint2 __attribute__((ext_vector_type(2))); +typedef uint uint4 __attribute__(

[clang] [AMDGPU] Add GFX12 __builtin_amdgcn_s_sleep_var (PR #77926)

@@ -0,0 +1,11 @@ +// REQUIRES: amdgpu-registered-target + +// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx1100 -verify -S -emit-llvm -o - %s + +typedef unsigned int uint; +typedef uint uint2 __attribute__((ext_vector_type(2))); +typedef uint uint4 __attribute__(

[clang] [AMDGPU] Add GFX12 __builtin_amdgcn_s_sleep_var (PR #77926)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/77926 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [AMDGPU][NFC] Rename feature FP8Insts to FP8ConversionInsts (PR #78439)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/78439 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [flang] [compiler-rt] [clang-tools-extra] [llvm] [AMDGPU][GFX12] Add 16 bit atomic fadd instructions (PR #75917)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/75917 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang-tools-extra] [llvm] [flang] [compiler-rt] [AMDGPU][GFX12] Add 16 bit atomic fadd instructions (PR #75917)

@@ -1,56 +1,244 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX12 %s -; RUN: llc -march=amdgcn -global-isel=1 -mcpu=gfx1200 -verify-machineinstrs <

[llvm] [compiler-rt] [clang] [clang-tools-extra] [flang] [AMDGPU][GFX12] Add 16 bit atomic fadd instructions (PR #75917)

https://github.com/arsenm edited https://github.com/llvm/llvm-project/pull/75917 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang-tools-extra] [clang] [AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (PR #77438)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/77438 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [libcxx] [clang-tools-extra] [llvm] [flang] [lld] [compiler-rt] [libc] [lldb] [AMDGPU] Use alias info to relax waitcounts for LDS DMA (PR #74537)

arsenm wrote: > > lgtm, but can still fix the -O0 thing > > But where do I get TM in the getAnalysisUsage? MF.getTarget() https://github.com/llvm/llvm-project/pull/74537 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/c

[compiler-rt] [llvm] [flang] [lldb] [clang] [libcxx] [clang-tools-extra] [libc] [lld] [AMDGPU] Use alias info to relax waitcounts for LDS DMA (PR #74537)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/74537 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang-tools-extra] [clang] DAG: Fix chain mismanagement in SoftenFloatRes_FP_EXTEND (PR #74558)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/74558 >From cdafeff37cd20e8cb8cdcf6ac8561455d5c9a30a Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Sat, 2 Dec 2023 20:49:51 +0700 Subject: [PATCH 1/2] DAG: Fix ABI lowering with FP promote in strictfp functions

[clang] [llvm] [clang-tools-extra] DAG: Fix chain mismanagement in SoftenFloatRes_FP_EXTEND (PR #74558)

https://github.com/arsenm closed https://github.com/llvm/llvm-project/pull/74558 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [CodeGen] Port AtomicExpand to new Pass Manager (PR #71220)

@@ -340,7 +342,31 @@ bool AtomicExpand::runOnFunction(Function &F) { return MadeChange; } -bool AtomicExpand::bracketInstWithFences(Instruction *I, AtomicOrdering Order) { +bool AtomicExpandLegacy::runOnFunction(Function &F) { + i arsenm wrote: Stray char

[llvm] [clang] [CodeGen] Port AtomicExpand to new Pass Manager (PR #71220)

@@ -457,7 +457,7 @@ TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) { void PPCPassConfig::addIRPasses() { if (TM->getOptLevel() != CodeGenOptLevel::None) addPass(createPPCBoolRetToIntPass()); - addPass(createAtomicExpandPass()); + addPass(crea

[clang] [llvm] [docs] Add llvm and clang release notes for the global-var code model attribute (PR #78664)

@@ -70,6 +70,8 @@ Changes to the LLVM IR * Added `llvm.exp10` intrinsic. +* Added a code model attribute for the global variable. arsenm wrote: Helpful to include link to the LangRef reference https://github.com/llvm/llvm-project/pull/78664 ___

[llvm] [clang] [AMDGPU] Remove gws feature from GFX12 (PR #78711)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/78711 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [CUDA][NFC] CudaArch to GpuArch rename (PR #97028)

@@ -52,7 +52,7 @@ const char *CudaVersionToString(CudaVersion V); // Input is "Major.Minor" CudaVersion CudaStringToVersion(const llvm::Twine &S); -enum class CudaArch { +enum class GpuArch { arsenm wrote: Probably should call this OffloadArch to match --offl

[clang] [CUDA][NFC] CudaArch to OffloadArch rename (PR #97028)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/97028 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [libc] [llvm] AMDGPU: Add a subtarget feature for fine-grained remote memory support (PR #96442)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/96442 >From 03be6a1847ff90955413d1d488e2619036ffbceb Mon Sep 17 00:00:00 2001 From: martinboehme Date: Wed, 26 Jun 2024 15:01:57 +0200 Subject: [PATCH 01/14] [clang][dataflow] Teach `AnalysisASTVisitor` that `typeid()`

[clang] [clang][CodeGen] Add query for a target's flat address space (PR #95728)

arsenm wrote: I still think we should not need this. DefaultIsPrivate is junk that needs to be deleted. Querying for LangAS::Default should always give the answer 0 for AMDGPU, which is what this is working around. This clang notion of address space has nothing to do with your troubles with l

[clang] [llvm] [clang][CodeGen][AMDGPU] Enable AMDGPU `printf` for `spirv64-amd-amdhsa` (PR #97132)

@@ -5888,12 +5888,16 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID, case Builtin::BI__builtin_printf: case Builtin::BIprintf: if (getTarget().getTriple().isNVPTX() || -getTarget().getTriple().isAMDGCN()) { +getTarget

[clang] [llvm] Add f8E4M3 IEEE 754 type to llvm (PR #97179)

arsenm wrote: Title and description needs rewording. This isn't adding the type "to llvm" which would imply adding the IR type, but only to APFloat https://github.com/llvm/llvm-project/pull/97179 ___ cfe-commits mailing list cfe-commits@lists.llvm.or

[clang] [libc] [llvm] AMDGPU: Add a subtarget feature for fine-grained remote memory support (PR #96442)

https://github.com/arsenm edited https://github.com/llvm/llvm-project/pull/96442 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

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