@@ -35971,6 +35971,15 @@ X86TargetLowering::EmitLoweredTLSAddr(MachineInstr &MI,
// inside MC, therefore without the two markers shrink-wrapping
// may push the prologue/epilogue pass them.
const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
+
arsenm
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/109410
>From d281cf9a6f7c67fdcb86ca2eb3af843f0297e457 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 14 Aug 2024 13:57:14 +0400
Subject: [PATCH 1/2] AMDGPU: Custom expand flat cmpxchg which may access
private
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/109408
>From 899877cef75cfe8818c2cb773d78dd165474e863 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Thu, 12 Sep 2024 12:44:04 +0400
Subject: [PATCH] AMDGPU: Add baseline tests for cmpxchg custom expansion
We need
arsenm wrote:
> Did you address [#109409
> (review)](https://github.com/llvm/llvm-project/pull/109409#pullrequestreview-2332197449)
> ?
I switched this over to copyMetadataForAtomic but I guess I never uploaded the
change
https://github.com/llvm/llvm-project/pull/109409
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/111730
>From 90a347159e1e6494bf95bcaf87e897e553ecc0f5 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 9 Oct 2024 22:05:48 +0400
Subject: [PATCH 1/2] GlobalISel: Fix combine duplicating atomic loads
The sext_in
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/111730
>From 90a347159e1e6494bf95bcaf87e897e553ecc0f5 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 9 Oct 2024 22:05:48 +0400
Subject: [PATCH 1/2] GlobalISel: Fix combine duplicating atomic loads
The sext_in
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/111730
>From 8c604131e334429111df841f00e810a3084a9956 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 9 Oct 2024 22:05:48 +0400
Subject: [PATCH] GlobalISel: Fix combine duplicating atomic loads
The sext_inreg
arsenm wrote:
> The duplicating is only due to atomicity of the load?
The duplicating is the apparent effect because the non-atomic load can be
deleted. There's no plus to keeping it around
> if (atomic)
> EraseFromParent();
> ```
This just adds extra work for later code to delete. The zex
arsenm wrote:
> Standard question: Could you add/extend a mir file for showing the different
> cases and should the erase be conditional on the type?
The type doesn't matter. The original load always has to be removed. This is
only done for hasOneUse anyway
https://github.com/llvm/llvm-proje
arsenm wrote:
> But patch adds several MUBUF_Pseudo_Load_Pats which are not covered by tests?
The only cases that might have missing coverage is extend to 16-bit register
cases. In the DAG we didn't have legal 16-bit types on gfx6/7, but we could
handle the loads here
https://github.com/ll
arsenm wrote:
> The original test files look unaffected? https://reviews.llvm.org/D85966
I don't think AArch64 will pass the legality check for the atomic sextload
https://github.com/llvm/llvm-project/pull/111730
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https://github.com/arsenm ready_for_review
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arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/111730?utm_source=stack-comment-downstack-mergeability-warning";
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/111730
The sext_inreg (load) combine was not deleting the old load instruction,
and it would never be deleted if volatile or atomic.
>From 5a23c2797ae59eb493fb9804ec32a1b8dc7755b2 Mon Sep 17 00:00:00 2001
From: Matt Ars
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/111721
>From 81dad077b21128cfc827ffb18b12631407a2bde4 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 9 Oct 2024 19:35:29 +0400
Subject: [PATCH] AMDGPU/GlobalISel: Handle atomic sextload and zextload
Atomic lo
@@ -0,0 +1,331 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri < %s |
FileCheck -check-prefixes=GCN,GFX7 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhs
arsenm wrote:
> Missing test for buffer loads?
Those are the gfx7 global cases. There aren't any atomic buffer load intrinsics
https://github.com/llvm/llvm-project/pull/111721
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ht
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https://github.com/llvm/llvm-project/pull/111721
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arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/111721?utm_source=stack-comment-downstack-mergeability-warning";
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/111721
Atomic loads are handled differently from the DAG, and have separate opcodes
and explicit control over the extensions, like ordinary loads. Add
new patterns for these.
There's room for cleanup and improvement. d1
arsenm wrote:
ping
https://github.com/llvm/llvm-project/pull/109409
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arsenm wrote:
### Merge activity
* **Oct 9, 5:42 AM EDT**: @arsenm started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/110815).
https://github.com/llvm/llvm-project/pull/110815
_
https://github.com/arsenm ready_for_review
https://github.com/llvm/llvm-project/pull/111652
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arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/111652?utm_source=stack-comment-downstack-mergeability-warning";
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/111652
These should be well behaved address computations.
>From 61f32fccd4cb7f8ef167ea5e6a7fb8e820a459b2 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 9 Oct 2024 13:11:16 +0400
Subject: [PATCH] AMDGPU: Add i
https://github.com/arsenm closed
https://github.com/llvm/llvm-project/pull/103939
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https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/103939
>From b655b4c3d3be5f8347ff4bc8fa37c1553f1fd980 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 14 Aug 2024 16:51:08 +0400
Subject: [PATCH 1/2] Local: Handle noalias.addrspace in copyMetadataForLoad
---
https://github.com/arsenm edited
https://github.com/llvm/llvm-project/pull/103939
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@@ -177,7 +177,7 @@ define i32 @test_load_cast_combine_noalias_addrspace(ptr
%ptr) {
; Ensure (cast (load (...))) -> (load (cast (...))) preserves TBAA.
arsenm wrote:
```suggestion
; Ensure (cast (load (...))) -> (load (cast (...))) preserves no
alias.addrspac
arsenm wrote:
> ping
Fix the description
https://github.com/llvm/llvm-project/pull/109937
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https://github.com/arsenm approved this pull request.
https://github.com/llvm/llvm-project/pull/110229
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@@ -3851,3 +3851,14 @@ SIRegisterInfo::getSubRegAlignmentNumBits(const
TargetRegisterClass *RC,
}
return 0;
}
+
+SmallVector
+SIRegisterInfo::getVRegFlagsOfReg(Register Reg,
+ const MachineFunction &MF) const {
+ SmallVector RegFlags;
+ c
@@ -1716,6 +1716,19 @@ bool GCNTargetMachine::parseMachineFunctionInfo(
MFI->reserveWWMRegister(ParsedReg);
}
+ auto setRegisterFlags = [&](const VRegInfo &Info) {
+for (uint8_t Flag : Info.Flags) {
+ MFI->setFlag(Info.VReg, Flag);
+}
arsen
https://github.com/arsenm approved this pull request.
https://github.com/llvm/llvm-project/pull/111634
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arsenm wrote:
ping
https://github.com/llvm/llvm-project/pull/103939
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https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/110815
>From 078f5f02502edadcc9c86f3e45f69e9fac918656 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 2 Oct 2024 11:20:23 +0400
Subject: [PATCH 1/3] DAG: Preserve more flags when expanding gep
This allows sele
@@ -454,6 +454,14 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
// No check if the subreg is supported by the current RC is made.
unsigned getSubRegAlignmentNumBits(const TargetRegisterClass *RC,
unsigned SubReg) const;
@@ -3839,3 +3839,14 @@ SIRegisterInfo::getSubRegAlignmentNumBits(const
TargetRegisterClass *RC,
}
return 0;
}
+
+SmallVector>
+SIRegisterInfo::getVRegFlagsOfReg(Register Reg,
+ const MachineFunction &MF) const {
+ SmallVector> RegFlags;
+
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/103939
>From b655b4c3d3be5f8347ff4bc8fa37c1553f1fd980 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 14 Aug 2024 16:51:08 +0400
Subject: [PATCH] Local: Handle noalias.addrspace in copyMetadataForLoad
---
llv
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/109410
>From b695265d5a72bf3c6ebe137df4d730fb92df08c5 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 14 Aug 2024 13:57:14 +0400
Subject: [PATCH 1/2] AMDGPU: Custom expand flat cmpxchg which may access
private
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/109408
>From fe3d55c18a74cc418315f7b04ae8390a638e2efd Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Thu, 12 Sep 2024 12:44:04 +0400
Subject: [PATCH] AMDGPU: Add baseline tests for cmpxchg custom expansion
We need
@@ -3839,3 +3839,14 @@ SIRegisterInfo::getSubRegAlignmentNumBits(const
TargetRegisterClass *RC,
}
return 0;
}
+
+SmallVector>
+SIRegisterInfo::getVRegFlagsOfReg(Register Reg,
+ const MachineFunction &MF) const {
+ SmallVector> RegFlags;
+
@@ -454,6 +454,16 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
// No check if the subreg is supported by the current RC is made.
unsigned getSubRegAlignmentNumBits(const TargetRegisterClass *RC,
unsigned SubReg) const;
@@ -3839,3 +3839,14 @@ SIRegisterInfo::getSubRegAlignmentNumBits(const
TargetRegisterClass *RC,
}
return 0;
}
+
+SmallVector>
+SIRegisterInfo::getVRegFlagsOfReg(Register Reg,
+ const MachineFunction &MF) const {
+ SmallVector> RegFlags;
+
@@ -684,8 +684,8 @@ class SIMachineFunctionInfo final : public
AMDGPUMachineFunction,
void setFlag(Register Reg, uint8_t Flag) {
assert(Reg.isVirtual());
-if (VRegFlags.inBounds(Reg))
- VRegFlags[Reg] |= Flag;
+VRegFlags.grow(Reg);
arsenm w
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/109410
>From 6c633b7f9acbc000dac2df4ac2eab630eb16e188 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 14 Aug 2024 13:57:14 +0400
Subject: [PATCH 1/2] AMDGPU: Custom expand flat cmpxchg which may access
private
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/109408
>From b69ead1780d39a41821fd0cd65326fba5c58673f Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Thu, 12 Sep 2024 12:44:04 +0400
Subject: [PATCH] AMDGPU: Add baseline tests for cmpxchg custom expansion
We need
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/103939
>From 7dcad206090561d7a46f853df8e67ad02bda8a72 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 14 Aug 2024 16:51:08 +0400
Subject: [PATCH] Local: Handle noalias.addrspace in copyMetadataForLoad
---
llv
arsenm wrote:
> Description needs to be more specific
Bump
https://github.com/llvm/llvm-project/pull/109937
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https://github.com/arsenm approved this pull request.
https://github.com/llvm/llvm-project/pull/109939
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@@ -0,0 +1,43 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs
-run-pass=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -verify-mac
https://github.com/arsenm approved this pull request.
https://github.com/llvm/llvm-project/pull/109938
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https://github.com/arsenm approved this pull request.
https://github.com/llvm/llvm-project/pull/111357
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https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/109410
>From d1c280fc9477f6dc9d8d88b223523cc941f504e6 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 14 Aug 2024 13:57:14 +0400
Subject: [PATCH 1/2] AMDGPU: Custom expand flat cmpxchg which may access
private
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/109408
>From 4934c7dfffd890420a433c30e6375f42bfa76596 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Thu, 12 Sep 2024 12:44:04 +0400
Subject: [PATCH] AMDGPU: Add baseline tests for cmpxchg custom expansion
We need
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/102599
>From 3415e01b8a510a3750ea55767c3f206c4e1a3e61 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 9 Aug 2024 14:51:41 +0400
Subject: [PATCH] AMDGPU: Add noalias.addrspace metadata when autoupgrading
atomic
@@ -578,3 +578,18 @@ body: |
SI_RETURN
...
+---
arsenm wrote:
Should add an error test where the flag name is unrecognized
https://github.com/llvm/llvm-project/pull/110229
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https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/111002
>From ac0b62834e39264a02656301515c8023b350b33d Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Thu, 3 Oct 2024 16:06:49 +0400
Subject: [PATCH] AMDGPU: Do not tail call if an inreg argument requires
waterfall
arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/111002?utm_source=stack-comment-downstack-mergeability-warning";
https://github.com/arsenm ready_for_review
https://github.com/llvm/llvm-project/pull/111002
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https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/111002
If we have a divergent value passed to an outgoing inreg argument,
the call needs to be executed in a waterfall loop and thus cannot
be tail called.
The waterfall handling of arbitrary calls is broken on the sele
@@ -4386,34 +4386,59 @@ void SelectionDAGBuilder::visitGetElementPtr(const User
&I) {
// it.
IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType());
+ SDNodeFlags ScaleFlags;
+ // The multiplication of an index by the type size does not wrap the
+ //
https://github.com/arsenm edited
https://github.com/llvm/llvm-project/pull/110827
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https://github.com/arsenm closed
https://github.com/llvm/llvm-project/pull/110490
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arsenm wrote:
New version in #110827
https://github.com/llvm/llvm-project/pull/110490
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https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/110827
This was using the default address space instead of the correct one.
Fixes #56055
Keep old method around for ABI compatibility on the release branch.
(cherry picked from commit 81ba95cefe1b5a12f0a7d8e6a383bcce9
https://github.com/arsenm milestoned
https://github.com/llvm/llvm-project/pull/110827
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@@ -4386,34 +4386,59 @@ void SelectionDAGBuilder::visitGetElementPtr(const User
&I) {
// it.
IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType());
+ SDNodeFlags ScaleFlags;
+ // The multiplication of an index by the type size does not wrap the
+ //
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/110815
>From 56474dac206d8592229cb56e1f12b543ec97 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 2 Oct 2024 11:20:23 +0400
Subject: [PATCH 1/2] DAG: Preserve more flags when expanding gep
This allows sele
https://github.com/arsenm ready_for_review
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arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/110815?utm_source=stack-comment-downstack-mergeability-warning";
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/110815
This allows selecting the addressing mode for stack instructions
in cases where we need to prove the sign bit is zero.
>From 56474dac206d8592229cb56e1f12b543ec97 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
@@ -43,7 +43,7 @@ define i64 @test_flat_atomicrmw_sub_0_i64_agent(ptr %ptr) {
; ALL: [[ATOMICRMW_PRIVATE]]:
; ALL-NEXT:[[TMP1:%.*]] = addrspacecast ptr [[PTR]] to ptr addrspace(5)
; ALL-NEXT:[[LOADED_PRIVATE:%.*]] = load i64, ptr addrspace(5) [[TMP1]],
align 8
-;
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/110738
>From 295561a4936e932aa41fe7d80ec2aafb94f49a8e Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Tue, 1 Oct 2024 23:53:51 +0400
Subject: [PATCH 1/2] AMDGPU: Handle folding frame indexes into add with
immediate
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/110738
>From 295561a4936e932aa41fe7d80ec2aafb94f49a8e Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Tue, 1 Oct 2024 23:53:51 +0400
Subject: [PATCH 1/2] AMDGPU: Handle folding frame indexes into add with
immediate
arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/110738?utm_source=stack-comment-downstack-mergeability-warning";
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/110738
Frame index materialization can fold the constant offset into
adds with immediates. The mubuf expansion is more complicated because
we have to also insert the shift, so restrict this to one use for now.
This is pr
https://github.com/arsenm approved this pull request.
https://github.com/llvm/llvm-project/pull/109295
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@@ -1628,6 +1628,21 @@ bool GCNTargetMachine::parseMachineFunctionInfo(
MFI->reserveWWMRegister(ParsedReg);
}
+ auto setRegisterFlags = [&](const VRegInfo &Info) {
+for (const auto &Flag : Info.Flags) {
arsenm wrote:
No auto, no reference. This is
@@ -1628,6 +1628,21 @@ bool GCNTargetMachine::parseMachineFunctionInfo(
MFI->reserveWWMRegister(ParsedReg);
}
+ auto setRegisterFlags = [&](const VRegInfo &Info) {
+for (const auto &Flag : Info.Flags) {
+ MFI->setFlag(Info.VReg, Flag);
+}
+ };
+
+ for (co
@@ -1628,6 +1628,21 @@ bool GCNTargetMachine::parseMachineFunctionInfo(
MFI->reserveWWMRegister(ParsedReg);
}
+ auto setRegisterFlags = [&](const VRegInfo &Info) {
+for (const auto &Flag : Info.Flags) {
+ MFI->setFlag(Info.VReg, Flag);
+}
+ };
+
+ for (co
@@ -3614,3 +3614,14 @@ SIRegisterInfo::getSubRegAlignmentNumBits(const
TargetRegisterClass *RC,
}
return 0;
}
+
+SmallVector
arsenm wrote:
probably should just be const char*, this will probably only ever be used with
literals
https://github.com/llvm/l
@@ -0,0 +1,16 @@
+# RUN: llc -mtriple=amdgcn -run-pass=none -o - %s | FileCheck %s
+# This test ensures that the MIR parser parses virtual register flags correctly
+
+---
+name: vregs
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: vgpr_32, preferred-register: '$vgpr1',
f
@@ -0,0 +1,26 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs
-run-pass=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s | FileCheck %s
+
+---
+
+name: pre_allocate_wwm_regs_s
@@ -10616,19 +10616,43 @@ SDValue SITargetLowering::LowerFDIV16(SDValue Op,
SelectionDAG &DAG) const {
return FastLowered;
SDLoc SL(Op);
- SDValue Src0 = Op.getOperand(0);
- SDValue Src1 = Op.getOperand(1);
-
- SDValue CvtSrc0 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f
@@ -4903,16 +4903,40 @@ bool AMDGPULegalizerInfo::legalizeFDIV16(MachineInstr
&MI,
LLT S16 = LLT::scalar(16);
LLT S32 = LLT::scalar(32);
+ // a32.u = opx(V_CVT_F32_F16, a.u); // CVT to F32
+ // b32.u = opx(V_CVT_F32_F16, b.u); // CVT to F32
+ // r32.u = opx(V_RCP_F32,
https://github.com/arsenm approved this pull request.
https://github.com/llvm/llvm-project/pull/110470
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https://github.com/arsenm approved this pull request.
https://github.com/llvm/llvm-project/pull/110256
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https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/109410
>From 831b4a6dde281d7cd3b95557c15cb417d278d568 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 14 Aug 2024 13:57:14 +0400
Subject: [PATCH 1/2] AMDGPU: Custom expand flat cmpxchg which may access
private
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/109408
>From caecd58b94c52b5568fc0014dad1c51796e4d36e Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Thu, 12 Sep 2024 12:44:04 +0400
Subject: [PATCH] AMDGPU: Add baseline tests for cmpxchg custom expansion
We need
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/102599
>From a2719d4938a1eaf135c275257b1b6c0318ccc801 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 9 Aug 2024 14:51:41 +0400
Subject: [PATCH] AMDGPU: Add noalias.addrspace metadata when autoupgrading
atomic
@@ -0,0 +1,21 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs
-amdgpu-prealloc-sgpr-spill-vgprs -run-pass=si-pre-allocate-wwm-regs -o -
-mcpu=tahiti %s | FileCheck %s
+
---
@@ -0,0 +1,26 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs
-run-pass=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s | FileCheck %s
+
+---
+
+name: pre_allocate_wwm_regs_s
@@ -0,0 +1,21 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs
-amdgpu-prealloc-sgpr-spill-vgprs -run-pass=si-pre-allocate-wwm-regs -o -
-mcpu=tahiti %s | FileCheck %s
+
+--
@@ -0,0 +1,26 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs
-run-pass=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s | FileCheck %s
+
+---
+
+name: pre_allocate_wwm_regs_s
@@ -0,0 +1,25 @@
+//===--- SIPreAllocateWWMRegs.h
---===//
arsenm wrote:
Missing C++ mode comment
https://github.com/llvm/llvm-project/pull/109939
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@@ -254,3 +262,13 @@ bool
SIPreAllocateWWMRegs::runOnMachineFunction(MachineFunction &MF) {
rewriteRegs(MF);
return true;
}
+
+PreservedAnalyses
+SIPreAllocateWWMRegsPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ au
@@ -97,6 +97,7 @@ LOOP_PASS("loop-term-fold", LoopTermFoldPass())
// preferably fix the scavenger to not depend on them).
MACHINE_FUNCTION_ANALYSIS("live-intervals", LiveIntervalsAnalysis())
MACHINE_FUNCTION_ANALYSIS("live-vars", LiveVariablesAnalysis())
+MACHINE_FUNCTION_ANALY
@@ -156,7 +156,7 @@ void initializeLiveDebugValuesPass(PassRegistry &);
void initializeLiveDebugVariablesPass(PassRegistry &);
void initializeLiveIntervalsWrapperPassPass(PassRegistry &);
void initializeLiveRangeShrinkPass(PassRegistry &);
-void initializeLiveRegMatrixPass(Pass
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