@@ -2,12 +2,20 @@
// RUN: %clang_cc1 -E -triple i386 -dM -o - -fcf-protection=branch %s |
FileCheck %s --check-prefix=BRANCH
// RUN: %clang_cc1 -E -triple i386 -dM -o - -fcf-protection=full %s |
FileCheck %s --check-prefix=FULL
// RUN: not %clang_cc1 -emit-llvm-only
https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/88245
This is a second try to reland https://github.com/llvm/llvm-project/pull/87149.
The previous commit exposed failures on some targets. The reason is only a few
targets support COFF ObjectFormatType on
Author: Phoebe Wang
Date: 2024-04-10T14:40:07+08:00
New Revision: 299b636a8f1c9cb2382f9dce4cdf6ec6330a79c6
URL:
https://github.com/llvm/llvm-project/commit/299b636a8f1c9cb2382f9dce4cdf6ec6330a79c6
DIFF:
https://github.com/llvm/llvm-project/commit/299b636a8f1c9cb2382f9dce4cdf6ec6330a79c6.diff
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/87987
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https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/88101
Fixes #62449
>From 66c4383e58cab7cf893edfa3f3507be166116fa6 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Tue, 9 Apr 2024 16:08:55 +0800
Subject: [PATCH] [SEH] Ignore async exception flag when the
https://github.com/phoebewang edited
https://github.com/llvm/llvm-project/pull/87987
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https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/87987
This relands #87149.
The previous commit exposed failures on some targets. The reason is only a few
targets support COFF ObjectFormatType on Windows:
Author: Phoebe Wang
Date: 2024-04-03T16:10:19+08:00
New Revision: cd7517859eef14d8b38cec2d52c0625a58c645a2
URL:
https://github.com/llvm/llvm-project/commit/cd7517859eef14d8b38cec2d52c0625a58c645a2
DIFF:
https://github.com/llvm/llvm-project/commit/cd7517859eef14d8b38cec2d52c0625a58c645a2.diff
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/87149
>From 16fea4659909423319f0107b2a4d5bcc31185299 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Sat, 30 Mar 2024 17:29:06 +0800
Subject: [PATCH] [Win32][ELF] Make CodeView a DebugInfoFormat only for COFF
https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/87149
We have many problems to use CodeView for a win32-elf target, e.g., #87140 and
`error: .seh_* directives are not supported on this target`.
Fixes: #87140
>From 745b2acb9dafbb54b00353f71dee464b3617c13a Mon
https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/85862
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@@ -207,6 +207,8 @@ _mm256_div_ps(__m256 __a, __m256 __b)
/// Compares two 256-bit vectors of [4 x double] and returns the greater
///of each pair of values.
///
+///If either value in a comparison is NaN, returns the value from \a __b.
phoebewang
phoebewang wrote:
Checked both pr77036.cpp and pr77036.c get the same result, so looks like a
right fix. But I want to wait @efriedma-quic to sign off.
https://github.com/llvm/llvm-project/pull/77907
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@@ -3014,6 +3014,11 @@ Address X86_64ABIInfo::EmitVAArg(CodeGenFunction ,
Address VAListAddr,
ABIArgInfo AI = classifyArgumentType(Ty, 0, neededInt, neededSSE,
/*isNamedArg*/false);
+ // Empty records are ignored for parameter
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/83136
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https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/83136
>From cdc9ee6c322af0ceed162f3f714bcd0a22e020c3 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Tue, 27 Feb 2024 22:16:38 +0800
Subject: [PATCH 1/8] [X86] Add Support for X86 TLSDESC Relocations
---
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/83136
>From cdc9ee6c322af0ceed162f3f714bcd0a22e020c3 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Tue, 27 Feb 2024 22:16:38 +0800
Subject: [PATCH 1/8] [X86] Add Support for X86 TLSDESC Relocations
---
@@ -0,0 +1,247 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc < %s -mtriple=i686 --relocation-model=pic -enable-tlsdesc |
FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-pc-linux-gnux32
https://github.com/phoebewang approved this pull request.
Looks great, thanks!
https://github.com/llvm/llvm-project/pull/83447
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phoebewang wrote:
Gentle ping~
https://github.com/llvm/llvm-project/pull/83136
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@@ -1405,11 +1413,12 @@ static __inline__ __m128d __DEFAULT_FN_ATTRS
_mm_cvtss_sd(__m128d __a,
/// Converts the two double-precision floating-point elements of a
///128-bit vector of [2 x double] into two signed 32-bit integer values,
-///returned in the lower 64
@@ -1405,11 +1413,12 @@ static __inline__ __m128d __DEFAULT_FN_ATTRS
_mm_cvtss_sd(__m128d __a,
/// Converts the two double-precision floating-point elements of a
///128-bit vector of [2 x double] into two signed 32-bit integer values,
-///returned in the lower 64
https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/84136
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@@ -18543,7 +18552,19 @@ GetTLSADDR(SelectionDAG , SDValue Chain,
GlobalAddressSDNode *GA,
MFI.setHasCalls(true);
SDValue Glue = Chain.getValue(1);
- return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Glue);
+ SDValue Ret = DAG.getCopyFromReg(Chain, dl, ReturnReg,
@@ -18522,13 +18522,21 @@ GetTLSADDR(SelectionDAG , SDValue Chain,
GlobalAddressSDNode *GA,
MachineFrameInfo = DAG.getMachineFunction().getFrameInfo();
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
SDLoc dl(GA);
- SDValue TGA =
@@ -0,0 +1,165 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc < %s -mtriple=i686-unknown-unknown --relocation-model=pic
-enable-tlsdesc | FileCheck %s --check-prefix=X86
+; RUN: llc < %s
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/83136
>From cdc9ee6c322af0ceed162f3f714bcd0a22e020c3 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Tue, 27 Feb 2024 22:16:38 +0800
Subject: [PATCH 1/7] [X86] Add Support for X86 TLSDESC Relocations
---
phoebewang wrote:
> I assume that's what you're doing in the place I asked for a comment is
> trying to avoid redundantly generating TLSDESC accesses for
> _TLS_MODULE_BASE_. I see that we don't generate multiple accesses for
> _TLS_MODULE_BASE_ in the test cases, but I thought that was only
@@ -34,6 +34,60 @@ __m128 test_mm_andnot_ps(__m128 A, __m128 B) {
return _mm_andnot_ps(A, B);
}
+__m128 test_mm_cmp_ps_eq_oq(__m128 a, __m128 b) {
+ // CHECK-LABEL: test_mm_cmp_ps_eq_oq
+ // CHECK: fcmp oeq <4 x float> %{{.*}}, %{{.*}}
+ return _mm_cmp_ps(a, b,
@@ -18515,20 +18515,20 @@ X86TargetLowering::LowerGlobalAddress(SDValue Op,
SelectionDAG ) const {
return LowerGlobalOrExternal(Op, DAG, /*ForCall=*/false);
}
-static SDValue
-GetTLSADDR(SelectionDAG , SDValue Chain, GlobalAddressSDNode *GA,
- SDValue *InGlue,
@@ -0,0 +1,165 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc < %s -mtriple=i686-unknown-unknown --relocation-model=pic
-enable-tlsdesc | FileCheck %s --check-prefix=X86
+; RUN: llc < %s
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/83136
>From cdc9ee6c322af0ceed162f3f714bcd0a22e020c3 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Tue, 27 Feb 2024 22:16:38 +0800
Subject: [PATCH 1/6] [X86] Add Support for X86 TLSDESC Relocations
---
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/83136
>From cdc9ee6c322af0ceed162f3f714bcd0a22e020c3 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Tue, 27 Feb 2024 22:16:38 +0800
Subject: [PATCH 1/6] [X86] Add Support for X86 TLSDESC Relocations
---
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/83136
>From cdc9ee6c322af0ceed162f3f714bcd0a22e020c3 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Tue, 27 Feb 2024 22:16:38 +0800
Subject: [PATCH 1/5] [X86] Add Support for X86 TLSDESC Relocations
---
https://github.com/phoebewang deleted
https://github.com/llvm/llvm-project/pull/83136
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@@ -0,0 +1,165 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc < %s -mtriple=i686-unknown-unknown --relocation-model=pic
-enable-tlsdesc | FileCheck %s --check-prefix=X86
+; RUN: llc < %s
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/83136
>From cdc9ee6c322af0ceed162f3f714bcd0a22e020c3 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Tue, 27 Feb 2024 22:16:38 +0800
Subject: [PATCH 1/4] [X86] Add Support for X86 TLSDESC Relocations
---
phoebewang wrote:
Ping~
https://github.com/llvm/llvm-project/pull/83136
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phoebewang wrote:
This is a turbulent change to both upstream and downstream tests without any
profit as far as I can tell.
I did a similar change for 64-bit a few years ago:
https://reviews.llvm.org/D129647
In comparison, this patch is not to solve a specific problem. It should not
show
@@ -2211,7 +2213,12 @@ _mm256_cvtpd_ps(__m256d __a)
return (__m128)__builtin_ia32_cvtpd2ps256((__v4df) __a);
}
-/// Converts a vector of [8 x float] into a vector of [8 x i32].
+/// Converts a vector of [8 x float] into a vector of [8 x i32]. Rounds inexact
+///results
@@ -2180,7 +2180,8 @@ _mm256_cvtepi32_pd(__m128i __a)
return (__m256d)__builtin_convertvector((__v4si)__a, __v4df);
}
-/// Converts a vector of [8 x i32] into a vector of [8 x float].
+/// Converts a vector of [8 x i32] into a vector of [8 x float]. Rounds inexact
+///
@@ -0,0 +1,165 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc < %s -mtriple=i686-unknown-unknown --relocation-model=pic
-enable-tlsdesc | FileCheck %s --check-prefix=X86
+; RUN: llc < %s
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/83136
>From cdc9ee6c322af0ceed162f3f714bcd0a22e020c3 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Tue, 27 Feb 2024 22:16:38 +0800
Subject: [PATCH 1/3] [X86] Add Support for X86 TLSDESC Relocations
---
https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/83316
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@@ -0,0 +1,165 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc < %s -mtriple=i686-unknown-unknown --relocation-model=pic
-enable-tlsdesc | FileCheck %s --check-prefix=X86
+; RUN: llc < %s
@@ -0,0 +1,165 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc < %s -mtriple=i686-unknown-unknown --relocation-model=pic
-enable-tlsdesc | FileCheck %s --check-prefix=X86
phoebewang wrote:
@@ -18515,17 +18515,17 @@ X86TargetLowering::LowerGlobalAddress(SDValue Op,
SelectionDAG ) const {
return LowerGlobalOrExternal(Op, DAG, /*ForCall=*/false);
}
-static SDValue
-GetTLSADDR(SelectionDAG , SDValue Chain, GlobalAddressSDNode *GA,
- SDValue *InGlue,
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/83136
>From cdc9ee6c322af0ceed162f3f714bcd0a22e020c3 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Tue, 27 Feb 2024 22:16:38 +0800
Subject: [PATCH 1/2] [X86] Add Support for X86 TLSDESC Relocations
---
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/83136
>From cdc9ee6c322af0ceed162f3f714bcd0a22e020c3 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Tue, 27 Feb 2024 22:16:38 +0800
Subject: [PATCH] [X86] Add Support for X86 TLSDESC Relocations
---
https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/83136
None
>From 421a5e4c0a6d7beda71118a36650e72c3d6f2377 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Tue, 27 Feb 2024 22:16:38 +0800
Subject: [PATCH] [X86] Add Support for X86 TLSDESC Relocations
---
https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/82422
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@@ -2099,9 +2099,11 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS
_mm_add_epi64(__m128i __a,
}
/// Adds, with saturation, the corresponding elements of two 128-bit
-///signed [16 x i8] vectors, saving each sum in the corresponding element
of
-///a 128-bit result
phoebewang wrote:
You may also need to transfer "apxf" feature into subfeatures here
https://github.com/llvm/llvm-project/blob/main/clang/lib/Basic/Targets/X86.cpp#L106
https://github.com/llvm/llvm-project/pull/80636
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@@ -1845,6 +1845,12 @@ bool sys::getHostCPUFeatures(StringMap ) {
Features["prefetchi"] = HasLeaf7Subleaf1 && ((EDX >> 14) & 1);
Features["usermsr"] = HasLeaf7Subleaf1 && ((EDX >> 15) & 1);
Features["avx10.1-256"] = HasLeaf7Subleaf1 && ((EDX >> 19) & 1);
+
@@ -2099,9 +2099,11 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS
_mm_add_epi64(__m128i __a,
}
/// Adds, with saturation, the corresponding elements of two 128-bit
-///signed [16 x i8] vectors, saving each sum in the corresponding element
of
-///a 128-bit result
https://github.com/phoebewang edited
https://github.com/llvm/llvm-project/pull/82422
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@@ -2099,9 +2099,11 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS
_mm_add_epi64(__m128i __a,
}
/// Adds, with saturation, the corresponding elements of two 128-bit
-///signed [16 x i8] vectors, saving each sum in the corresponding element
of
-///a 128-bit result
@@ -1845,6 +1845,7 @@ bool sys::getHostCPUFeatures(StringMap ) {
Features["prefetchi"] = HasLeaf7Subleaf1 && ((EDX >> 14) & 1);
Features["usermsr"] = HasLeaf7Subleaf1 && ((EDX >> 15) & 1);
Features["avx10.1-256"] = HasLeaf7Subleaf1 && ((EDX >> 19) & 1);
+
https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/80815
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@@ -1845,6 +1845,7 @@ bool sys::getHostCPUFeatures(StringMap ) {
Features["prefetchi"] = HasLeaf7Subleaf1 && ((EDX >> 14) & 1);
Features["usermsr"] = HasLeaf7Subleaf1 && ((EDX >> 15) & 1);
Features["avx10.1-256"] = HasLeaf7Subleaf1 && ((EDX >> 19) & 1);
+
@@ -211,7 +214,11 @@
/* Features in %edx for leaf 7 sub-leaf 1 */
#define bit_AVXVNNIINT8 0x0010
#define bit_AVXNECONVERT 0x0020
+#define bit_AMXCOMPLEX0x0100
+#define bit_AVXVNNIINT16 0x0400
#define bit_PREFETCHI 0x4000
+#define bit_USERMSR
@@ -211,7 +214,11 @@
/* Features in %edx for leaf 7 sub-leaf 1 */
#define bit_AVXVNNIINT8 0x0010
#define bit_AVXNECONVERT 0x0020
+#define bit_AMXCOMPLEX0x0100
+#define bit_AVXVNNIINT16 0x0400
#define bit_PREFETCHI 0x4000
+#define bit_USERMSR
https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/79086
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@@ -217,8 +217,7 @@ enum ProcessorFeatures {
FEATURE_SM3,
FEATURE_SHA512,
FEATURE_SM4,
- //FIXME: gcc used string "apxf" instead of "egpr"
- FEATURE_EGPR,
+ // FEATURE_APXF,
FEATURE_USERMSR,
phoebewang wrote:
You need to change the number then.
@@ -217,10 +217,11 @@ enum ProcessorFeatures {
FEATURE_SM3,
FEATURE_SHA512,
FEATURE_SM4,
- // FEATURE_APX_F,
- FEATURE_USERMSR = 112,
- // FEATURE_AVX10_1_256,
- // FEATURE_AVX10_1_512,
+ //FIXME: gcc used string "apxf" instead of "egpr"
phoebewang
@@ -139,20 +139,88 @@ enum ProcessorFeatures {
FEATURE_AVX512BITALG,
FEATURE_AVX512BF16,
FEATURE_AVX512VP2INTERSECT,
-
- FEATURE_CMPXCHG16B = 46,
- FEATURE_F16C = 49,
+ // FIXME: Below Features has some missings comparing to gcc, it's because gcc
+ // has some not
@@ -139,20 +139,79 @@ enum ProcessorFeatures {
FEATURE_AVX512BITALG,
FEATURE_AVX512BF16,
FEATURE_AVX512VP2INTERSECT,
+ // Below Features has many missings comparing to gcc, it's because gcc has
+ // some LLVM doesn't include, e.g. FEATURE_ABM, FEATURE_HLE, ...
+
@@ -1,4 +1,12 @@
// RUN: %clang_cc1 -triple x86_64-apple-darwin9 -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple i586-intel-elfiamcu -fsyntax-only -verify %s
+
+#ifdef __iamcu
+// expected-no-diagnostics
+struct dummy { int x __attribute__((aligned)); };
+int
https://github.com/phoebewang approved this pull request.
LGTM with one nit.
https://github.com/llvm/llvm-project/pull/80401
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https://github.com/llvm/llvm-project/pull/80401
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@@ -139,20 +139,77 @@ enum ProcessorFeatures {
FEATURE_AVX512BITALG,
FEATURE_AVX512BF16,
FEATURE_AVX512VP2INTERSECT,
+ FEATURE_3DNOW,
+ FEATURE_ADX = 40,
+ FEATURE_CLDEMOTE = 42,
phoebewang wrote:
ABM is a AMD specific feature
@@ -139,20 +139,79 @@ enum ProcessorFeatures {
FEATURE_AVX512BITALG,
FEATURE_AVX512BF16,
FEATURE_AVX512VP2INTERSECT,
+ // Below Features has many missings comparing to gcc, it's because gcc has
+ // some LLVM doesn't include, e.g. FEATURE_ABM, FEATURE_HLE, ...
+
@@ -139,20 +139,77 @@ enum ProcessorFeatures {
FEATURE_AVX512BITALG,
FEATURE_AVX512BF16,
FEATURE_AVX512VP2INTERSECT,
+ FEATURE_3DNOW,
+ FEATURE_ADX = 40,
+ FEATURE_CLDEMOTE = 42,
phoebewang wrote:
Why do we skip some of features?
@@ -32815,10 +32815,10 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
// No other ValueType for FP_EXTEND should reach this point.
assert(N->getValueType(0) == MVT::v2f32 &&
"Do not know how to legalize this Node");
-if (!Subtarget.hasFP16() ||
https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/78560
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@@ -173,85 +173,84 @@ X86_FEATURE_COMPAT(AVX512VNNI, "avx512vnni",
34)
X86_FEATURE_COMPAT(AVX512BITALG,"avx512bitalg", 35)
X86_FEATURE_COMPAT(AVX512BF16, "avx512bf16",36)
X86_FEATURE_COMPAT(AVX512VP2INTERSECT,
@@ -173,85 +173,84 @@ X86_FEATURE_COMPAT(AVX512VNNI, "avx512vnni",
34)
X86_FEATURE_COMPAT(AVX512BITALG,"avx512bitalg", 35)
X86_FEATURE_COMPAT(AVX512BF16, "avx512bf16",36)
X86_FEATURE_COMPAT(AVX512VP2INTERSECT,
https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/79048
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https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/78901
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@@ -803,10 +803,10 @@
// RUN: %clang -target x86_64-unknown-unknown -march=x86-64 -mapx-features=ndd
-x c -E -dM -o - %s | FileCheck --check-prefix=NDD %s
// RUN: %clang -target x86_64-unknown-unknown -march=x86-64
-mapx-features=ccmp -x c -E -dM -o - %s | FileCheck
@@ -803,10 +803,10 @@
// RUN: %clang -target x86_64-unknown-unknown -march=x86-64 -mapx-features=ndd
-x c -E -dM -o - %s | FileCheck --check-prefix=NDD %s
// RUN: %clang -target x86_64-unknown-unknown -march=x86-64
-mapx-features=ccmp -x c -E -dM -o - %s | FileCheck
https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/78613
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@@ -3190,10 +3190,10 @@ def fno_experimental_isel : Flag<["-"],
"fno-experimental-isel">, Group,
-
Values<"Accelerate,libmvec,MASSV,SVML,SLEEF,Darwin_libsystem_m,ArmPL,none">,
+
Values<"Accelerate,libmvec,MASSV,SVML,SLEEF,Darwin_libsystem_m,ArmPL,AMDLIBM,none">,
@@ -3190,10 +3190,10 @@ def fno_experimental_isel : Flag<["-"],
"fno-experimental-isel">, Group,
-
Values<"Accelerate,libmvec,MASSV,SVML,SLEEF,Darwin_libsystem_m,ArmPL,none">,
+
Values<"Accelerate,libmvec,MASSV,SVML,SLEEF,Darwin_libsystem_m,ArmPL,AMDLIBM,none">,
@@ -129,7 +129,8 @@ class TargetLibraryInfoImpl {
MASSV,// IBM MASS vector library.
SVML, // Intel short vector math library.
SLEEFGNUABI, // SLEEF - SIMD Library for Evaluating Elementary Functions.
-ArmPL// Arm Performance
@@ -1279,6 +1281,213 @@ void
TargetLibraryInfoImpl::addVectorizableFunctionsFromVecLib(
}
break;
}
+ case AMDLIBM: {
+#define FIXED(NL) ElementCount::getFixed(NL)
+const VecDesc VecFuncs[] = {
phoebewang wrote:
Move them to `VecFuncs.def`?
@@ -411,13 +497,45 @@ __rdpmc(int __A) {
/// \param __A
///Address of where to store the 32-bit \c IA32_TSC_AUX value.
/// \returns The 64-bit value of the time stamp counter.
+/// \see _rdtsc
static __inline__ unsigned long long __DEFAULT_FN_ATTRS
__rdtscp(unsigned int
https://github.com/phoebewang commented:
> Is _bswap (one underscore) a mistake? The [12.0 release
> notes](https://releases.llvm.org/12.0.0/tools/clang/docs/ReleaseNotes.html#x86-support-in-clang)
> say it has two underscores.
I think single underscore is correct, it conform the difination
https://github.com/phoebewang edited
https://github.com/llvm/llvm-project/pull/78613
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phoebewang wrote:
> I've revised it. Can you check it again? @phoebewang
I'm not sure the usage of the `isEmptyRecord`. Tagging @asb who modified the
interface recently.
https://github.com/llvm/llvm-project/pull/77907
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phoebewang wrote:
Thanks @KanRobert !
https://github.com/llvm/llvm-project/pull/77733
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https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/77733
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https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/77686
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@@ -173,25 +183,59 @@ __popcntq(unsigned long long __A)
#endif /* __x86_64__ */
#ifdef __x86_64__
+/// Returns the program status and control \c RFLAGS register with the \c VM
+///and \c RF flags cleared.
+///
+/// \headerfile
+///
+/// This intrinsic corresponds to the
phoebewang wrote:
> > > Why not return `i32` for 64-bit mask in 32-bit mode?
> >
> >
> > You mean in two `i32` registers? The problem is the inline asm constraint
> > has 1:1 map with physical register except corner cases. And represent a `k`
> > constraint into two GPR registers is
phoebewang wrote:
> Why not return `i32` for 64-bit mask in 32-bit mode?
You mean in two `i32` registers? The problem is the inline asm constraint has
1:1 map with physical register except corner cases. And represent a `k`
constraint into two GPR registers is inefficient.
@@ -130,3 +130,7 @@ void pr40890(void) {
__asm__ __volatile__("\n#define BEEF abcd%0\n" : :
"n"((int*)0xdeadbeef));
#endif
}
+
+void test_W(int i) {
+ asm("" : : "Wd"(test_W)); // expected-error{{invalid input constraint 'Wd'
in asm}}
phoebewang
@@ -130,3 +130,7 @@ void pr40890(void) {
__asm__ __volatile__("\n#define BEEF abcd%0\n" : :
"n"((int*)0xdeadbeef));
#endif
}
+
+void test_W(int i) {
+ asm("" : : "Wd"(test_W)); // expected-error{{invalid input constraint 'Wd'
in asm}}
phoebewang
@@ -1418,6 +1418,14 @@ bool X86TargetInfo::validateAsmConstraint(
case 'O':
Info.setRequiresImmediate(0, 127);
return true;
+ case 'W':
+switch (*++Name) {
+default:
+ return false;
+case 's':
+ Info.setAllowsRegister();
https://github.com/phoebewang edited
https://github.com/llvm/llvm-project/pull/77886
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