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@@ -86,5 +98,17 @@ char pext64_0[_pext_u64(0x0123456789ABCDEFULL,
0xULL) == 0x0
char pext64_1[_pext_u64(0x0123456789ABCDEFULL, 0x00F0ULL) ==
0x000EULL ? 1 : -1];
char pext64_2[_pext_u64(0x0123456789ABCDEFULL, 0xF0F0F0F0ULL) =
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LGTM.
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LGTM.
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https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/109598
The `-m[no-]evex512` are nontrivial options which are used to control vector
size of other AVX512 features. Hence we expose both to flang for Fortran users.
>From d9aa2912206bb435bc830a42bc5ddd8b604c7d98 Mon
@@ -144,6 +144,7 @@ add_clang_library(clangCodeGen
VarBypassDetector.cpp
DEPENDS
+ vt_gen
phoebewang wrote:
Why it depends?
https://github.com/llvm/llvm-project/pull/109342
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LGTM.
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@@ -23,7 +23,7 @@
static __inline__ __m512i __DEFAULT_FN_ATTRS
_mm512_popcnt_epi16(__m512i __A)
{
- return (__m512i) __builtin_ia32_vpopcntw_512((__v32hi) __A);
+ return (__m512i)__builtin_elementwise_popcount((__v32hi)__A);
phoebewang wrote:
hi or hu? The s
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/108537
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phoebewang wrote:
@mahesh-attarde please solve the conflict.
https://github.com/llvm/llvm-project/pull/108537
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@@ -2139,9 +2139,9 @@ define <8 x i16> @pr59628_xmm(i16 %arg) {
; X86-LABEL: pr59628_xmm:
; X86: # %bb.0:
; X86-NEXT:movzwl {{[0-9]+}}(%esp), %eax
-; X86-NEXT:vxorps %xmm0, %xmm0, %xmm0
+; X86-NEXT:vpxor %xmm0, %xmm0, %xmm0
; X86-NEXT:vpbroadcastw %eax, %
@@ -38197,7 +38197,8 @@ static bool matchUnaryShuffle(MVT MaskVT, ArrayRef
Mask,
// Match against a VZEXT_MOVL instruction, SSE1 only supports 32-bits
(MOVSS).
if (((MaskEltSize == 32) || (MaskEltSize == 64 && Subtarget.hasSSE2()) ||
- (MaskEltSize == 16 && Subtarg
@@ -0,0 +1,17 @@
+// RUN: llvm-mc -triple i386 --show-encoding %s | FileCheck %s
+
+// CHECK: vmovd %xmm2, %xmm1
+// CHECK: encoding: [0x62,0xf1,0x7e,0x08,0x7e,0xca]
+ vmovd %xmm2, %xmm1
phoebewang wrote:
Missing memory tests.
https://github.com/llv
@@ -1537,3 +1537,67 @@ defm VFNMADD132NEPBF16 : avx10_fma3p_132_bf16<0x9C,
"vfnmadd132nepbf16", X86any_
defm VFNMSUB132NEPBF16 : avx10_fma3p_132_bf16<0x9E, "vfnmsub132nepbf16",
X86any_Fnmsub,
X86Fnmsub, SchedWriteFMA>;
}
+
+//
@@ -0,0 +1,34 @@
+/*=== avx10_2copyintrin.h - AVX10.2 Copy intrinsics ---===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache
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LGTM with one nit.
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@@ -0,0 +1,297 @@
+/*===- avx10_2_512satcvtdsintrin.h - AVX10_2_512SATCVTDS intrinsics ===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apac
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@@ -0,0 +1,478 @@
+/*===--- avx10_2satcvtdsintrin.h - AVX512SATCVTDS intrinsics
===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Ap
@@ -0,0 +1,443 @@
+/*===--- avx10_2satcvtdsintrin.h - AVX512SATCVTDS intrinsics
===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Ap
@@ -5520,6 +5520,106 @@ let TargetPrefix = "x86" in {
[IntrNoMem, ImmArg>]>;
}
+// conversion with saturation
+let TargetPrefix = "x86" in {
+ def int_x86_avx512_vcvttss2sis :
ClangBuiltin<"__builtin_ia32_vcvttss2sis32">,
phoebewa
@@ -0,0 +1,526 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 3
+; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown
--show-mc-encoding -mattr=+avx10.2-512 | FileCheck %s --check-prefixes=CHECK,X64
+; RUN:
@@ -0,0 +1,526 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 3
+; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown
--show-mc-encoding -mattr=+avx10.2-512 | FileCheck %s --check-prefixes=CHECK,X64
+; RUN:
@@ -625,6 +625,317 @@ defm VCVTTPS2IUBS : avx10_sat_cvt_base<0x6a,
"vcvttps2iubs", SchedWriteVecIMul,
X86vcvttp2iubsSAE>,
AVX512PDIi8Base, T_MAP5, EVEX_CD8<32, CD8VF>;
+//---
@@ -625,6 +625,317 @@ defm VCVTTPS2IUBS : avx10_sat_cvt_base<0x6a,
"vcvttps2iubs", SchedWriteVecIMul,
X86vcvttp2iubsSAE>,
AVX512PDIi8Base, T_MAP5, EVEX_CD8<32, CD8VF>;
+//---
@@ -625,6 +625,317 @@ defm VCVTTPS2IUBS : avx10_sat_cvt_base<0x6a,
"vcvttps2iubs", SchedWriteVecIMul,
X86vcvttp2iubsSAE>,
AVX512PDIi8Base, T_MAP5, EVEX_CD8<32, CD8VF>;
+//---
@@ -625,6 +625,317 @@ defm VCVTTPS2IUBS : avx10_sat_cvt_base<0x6a,
"vcvttps2iubs", SchedWriteVecIMul,
X86vcvttp2iubsSAE>,
AVX512PDIi8Base, T_MAP5, EVEX_CD8<32, CD8VF>;
+//---
@@ -625,6 +625,317 @@ defm VCVTTPS2IUBS : avx10_sat_cvt_base<0x6a,
"vcvttps2iubs", SchedWriteVecIMul,
X86vcvttp2iubsSAE>,
AVX512PDIi8Base, T_MAP5, EVEX_CD8<32, CD8VF>;
+//---
@@ -625,6 +625,317 @@ defm VCVTTPS2IUBS : avx10_sat_cvt_base<0x6a,
"vcvttps2iubs", SchedWriteVecIMul,
X86vcvttp2iubsSAE>,
AVX512PDIi8Base, T_MAP5, EVEX_CD8<32, CD8VF>;
+//---
@@ -0,0 +1,443 @@
+/*===--- avx10_2satcvtdsintrin.h - AVX512SATCVTDS intrinsics
===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Ap
@@ -0,0 +1,443 @@
+/*===--- avx10_2satcvtdsintrin.h - AVX512SATCVTDS intrinsics
===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Ap
@@ -0,0 +1,443 @@
+/*===--- avx10_2satcvtdsintrin.h - AVX512SATCVTDS intrinsics
===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Ap
@@ -0,0 +1,220 @@
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=i386-unknown-unknown -target-feature +avx10.2-256 -emit-llvm -o - |
FileCheck %s
phoebewang wrote:
Remoe `-unknown-unknown` and add `-triple=x86_64`
https://github.co
@@ -0,0 +1,183 @@
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=i386-unknown-unknown -target-feature +avx10.2-512 -emit-llvm -o - |
FileCheck %s
phoebewang wrote:
Remoe `-unknown-unknown` and add `-triple=x86_64`
https://github.co
@@ -0,0 +1,183 @@
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=i386-unknown-unknown -target-feature +avx10.2-512 -emit-llvm -o - |
FileCheck %s
+
+#include
+#include
+
+int test_mm_cvttssd_i32(__m128d __A) {
+ // CHECK-LABEL: @test_mm_cvttssd_i3
@@ -0,0 +1,447 @@
+/*===--- avx10_2satcvtdsintrin.h - AVX512SATCVTDS intrinsics
===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Ap
@@ -2122,6 +2122,36 @@ TARGET_BUILTIN(__builtin_ia32_vpdpwuud256,
"V8iV8iV8iV8i", "nV:256:", "avxvnniin
TARGET_BUILTIN(__builtin_ia32_vpdpwuuds128, "V4iV4iV4iV4i", "nV:128:",
"avxvnniint16|avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vpdpwuuds256, "V8iV8iV8iV8i", "nV:256:",
"a
@@ -153,7 +163,8 @@ const X86InstrFMA3Group *llvm::getFMA3Group(unsigned
Opcode, uint64_t TSFlags) {
((TSFlags & X86II::EncodingMask) == X86II::EVEX &&
((TSFlags & X86II::OpMapMask) == X86II::T8 ||
(TSF
https://github.com/phoebewang edited
https://github.com/llvm/llvm-project/pull/101603
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LGTM.
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phoebewang wrote:
Should we add folding in X86InstrFMA3Info.cpp?
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@@ -211,6 +211,12 @@ def X86CmpMaskCC :
SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
SDTCisVec<1>, SDTCisSameAs<2, 1>,
SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>]>;
+
+def X86CmpMaskCC_Int :
+ SDTypeProfile<1
@@ -313,7 +313,7 @@ def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
def v32f16_info : X86VectorVTInfo<32, f16, VR512, "ph">;
-def v32bf16_info: X86VectorVTInf
@@ -147,11 +147,13 @@ set(x86_files
amxcomplexintrin.h
amxfp16intrin.h
amxintrin.h
+ avx10_2_512bf16intrin.h
avx10_2_512convertintrin.h
avx10_2_512minmaxintrin.h
avx10_2_512niintrin.h
avx10_2_512satcvtintrin.h
avx10_2convertintrin.h
+ avx10_2bf16intrin.h
@@ -910,3 +910,313 @@ multiclass avx10_convert_2op_nomb,
AVX512XDIi8Base, T_MAP5, EVEX, EVEX_CD8<16, CD8VH>;
+
+//-
+// AVX10 BF16 instructions
+//-
+
+// VADDNEPBF16
@@ -910,3 +910,313 @@ multiclass avx10_convert_2op_nomb,
AVX512XDIi8Base, T_MAP5, EVEX, EVEX_CD8<16, CD8VH>;
+
+//-
+// AVX10 BF16 instructions
+//-
+
+// VADDNEPBF16
@@ -910,3 +910,313 @@ multiclass avx10_convert_2op_nomb,
AVX512XDIi8Base, T_MAP5, EVEX, EVEX_CD8<16, CD8VH>;
+
+//-
+// AVX10 BF16 instructions
+//-
+
+// VADDNEPBF16
@@ -7219,3 +7219,413 @@ def int_x86_avx10_mask_vcvtneph2hf8s512 :
ClangBuiltin<"__builtin_ia32_vcvtneph2
DefaultAttrsIntrinsic<[llvm_v32i8_ty], [llvm_v32f16_ty, llvm_v32i8_ty,
llvm_i32_ty],
[IntrNoMem]>;
}
+
+//===
@@ -910,3 +910,313 @@ multiclass avx10_convert_2op_nomb,
AVX512XDIi8Base, T_MAP5, EVEX, EVEX_CD8<16, CD8VH>;
+
+//-
+// AVX10 BF16 instructions
+//-
+
+// VADDNEPBF16
@@ -14836,6 +14837,9 @@ Value *CodeGenFunction::EmitX86BuiltinExpr(unsigned
BuiltinID,
case X86::BI__builtin_ia32_vfmaddph512_mask:
case X86::BI__builtin_ia32_vfmaddph512_maskz:
case X86::BI__builtin_ia32_vfmaddph512_mask3:
+ case X86::BI__builtin_ia32_vfmaddnepbh128:
+
@@ -0,0 +1,565 @@
+/*===--- avx10_2_512bf16intrin.h - AVX10-BF16 intrinsics -===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache
@@ -0,0 +1,1054 @@
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64 -target-feature +avx10.2-512 -emit-llvm -o -
-Wno-invalid-feature-combination -Wall -Werror | FileCheck %s
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-
@@ -910,3 +910,313 @@ multiclass avx10_convert_2op_nomb,
AVX512XDIi8Base, T_MAP5, EVEX, EVEX_CD8<16, CD8VH>;
+
+//-
+// AVX10 BF16 instructions
+//-
+
+// VADDNEPBF16
@@ -910,3 +910,313 @@ multiclass avx10_convert_2op_nomb,
AVX512XDIi8Base, T_MAP5, EVEX, EVEX_CD8<16, CD8VH>;
+
+//-
+// AVX10 BF16 instructions
+//-
+
+// VADDNEPBF16
@@ -910,3 +910,313 @@ multiclass avx10_convert_2op_nomb,
AVX512XDIi8Base, T_MAP5, EVEX, EVEX_CD8<16, CD8VH>;
+
+//-
+// AVX10 BF16 instructions
+//-
+
+// VADDNEPBF16
@@ -910,3 +910,313 @@ multiclass avx10_convert_2op_nomb,
AVX512XDIi8Base, T_MAP5, EVEX, EVEX_CD8<16, CD8VH>;
+
+//-
+// AVX10 BF16 instructions
+//-
+
+// VADDNEPBF16
@@ -910,3 +910,313 @@ multiclass avx10_convert_2op_nomb,
AVX512XDIi8Base, T_MAP5, EVEX, EVEX_CD8<16, CD8VH>;
+
+//-
+// AVX10 BF16 instructions
+//-
+
+// VADDNEPBF16
@@ -45,6 +45,14 @@ bool SemaX86::CheckBuiltinRoundingOrSAE(unsigned BuiltinID,
CallExpr *TheCall) {
case X86::BI__builtin_ia32_vcvttsh2si64:
phoebewang wrote:
We don't have a VCVTTSH2SIS instruction. The general convention is to use the
instruction name dire
https://github.com/phoebewang approved this pull request.
LGTM, thanks!
https://github.com/llvm/llvm-project/pull/105852
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@@ -0,0 +1,387 @@
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown -fsyntax-only \
phoebewang wrote:
Move it to clang/test/CodeGen/X86?
https://github.com/llvm/llvm-project/pull/105852
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cf
@@ -0,0 +1,105 @@
+// RUN: %clang_cc1 -triple i386-unknown-unknown -target-feature +mmx \
+// RUN: -target-feature +sse2 -O0 -emit-llvm %s -o - | FileCheck %s
+
+// Test that mmx/sse2 shift intrinsics map to the expected builtins.
+
+// Don't include mm_malloc.h, it's system spec
https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/101600
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https://github.com/phoebewang closed
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https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/104781
E.g.: https://godbolt.org/z/G8zK5svjK
Based on Evgenii's work.
>From 9a0c15c9b0bb3d1df3902dcfe62d659803cba516 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Mon, 19 Aug 2024 22:09:13 +0800
Subject: [PA
@@ -847,6 +847,91 @@ def X86vcvttp2iubs : SDNode<"X86ISD::CVTTP2IUBS",
SDTFloatToInt>;
def X86vcvttp2ibsSAE : SDNode<"X86ISD::CVTTP2IBS_SAE", SDTFloatToInt>;
def X86vcvttp2iubsSAE : SDNode<"X86ISD::CVTTP2IUBS_SAE", SDTFloatToInt>;
+def SDTAVX10CONVERT_I82F16 : SDTypeProfile<
@@ -617,7 +617,7 @@ constexpr FeatureBitset ImpliedFeaturesAVX10_1 =
FeatureAVX512CD | FeatureAVX512VBMI | FeatureAVX512IFMA |
FeatureAVX512VNNI | FeatureAVX512BF16 | FeatureAVX512VPOPCNTDQ |
FeatureAVX512VBMI2 | FeatureAVX512BITALG | FeatureVAES | FeatureVPCLMULQDQ
@@ -624,3 +624,328 @@ defm VCVTTPS2IUBS : avx10_sat_cvt_base<0x6a,
"vcvttps2iubs", SchedWriteVecIMul,
avx512vl_i32_info, avx512vl_f32_info,
X86vcvttp2iubsSAE>,
AVX512PDIi8Base, T_MA
@@ -847,6 +847,91 @@ def X86vcvttp2iubs : SDNode<"X86ISD::CVTTP2IUBS",
SDTFloatToInt>;
def X86vcvttp2ibsSAE : SDNode<"X86ISD::CVTTP2IBS_SAE", SDTFloatToInt>;
def X86vcvttp2iubsSAE : SDNode<"X86ISD::CVTTP2IUBS_SAE", SDTFloatToInt>;
+def SDTAVX10CONVERT_I82F16 : SDTypeProfile<
@@ -847,6 +847,91 @@ def X86vcvttp2iubs : SDNode<"X86ISD::CVTTP2IUBS",
SDTFloatToInt>;
def X86vcvttp2ibsSAE : SDNode<"X86ISD::CVTTP2IBS_SAE", SDTFloatToInt>;
def X86vcvttp2iubsSAE : SDNode<"X86ISD::CVTTP2IUBS_SAE", SDTFloatToInt>;
+def SDTAVX10CONVERT_I82F16 : SDTypeProfile<
@@ -7089,3 +7089,133 @@ def int_x86_avx10_mask_vcvttps2iubs512 :
ClangBuiltin<"__builtin_ia32_vcvttps2iu
DefaultAttrsIntrinsic<[llvm_v16i32_ty], [llvm_v16f32_ty,
llvm_v16i32_ty, llvm_i16_ty, llvm_i32_ty],
[IntrNoMem, ImmArg>]>;
}
+
+//===
@@ -847,6 +847,91 @@ def X86vcvttp2iubs : SDNode<"X86ISD::CVTTP2IUBS",
SDTFloatToInt>;
def X86vcvttp2ibsSAE : SDNode<"X86ISD::CVTTP2IBS_SAE", SDTFloatToInt>;
def X86vcvttp2iubsSAE : SDNode<"X86ISD::CVTTP2IUBS_SAE", SDTFloatToInt>;
+def SDTAVX10CONVERT_I82F16 : SDTypeProfile<
@@ -847,6 +847,91 @@ def X86vcvttp2iubs : SDNode<"X86ISD::CVTTP2IUBS",
SDTFloatToInt>;
def X86vcvttp2ibsSAE : SDNode<"X86ISD::CVTTP2IBS_SAE", SDTFloatToInt>;
def X86vcvttp2iubsSAE : SDNode<"X86ISD::CVTTP2IUBS_SAE", SDTFloatToInt>;
+def SDTAVX10CONVERT_I82F16 : SDTypeProfile<
@@ -1185,6 +1189,9 @@ Currently, only the following parameter attributes are
defined:
value should be sign-extended to the extent required by the target's
ABI (which is usually 32-bits) by the caller (for a parameter) or
the callee (for a return value).
+``noext``
@@ -1185,6 +1189,9 @@ Currently, only the following parameter attributes are
defined:
value should be sign-extended to the extent required by the target's
ABI (which is usually 32-bits) by the caller (for a parameter) or
the callee (for a return value).
+``noext``
@@ -0,0 +1,286 @@
+/*===- avx10_2_512convertintrin.h - AVX10_2_512CONVERT -===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apac
@@ -2217,6 +2217,50 @@ TARGET_BUILTIN(__builtin_ia32_vcvttps2ibs512_mask,
"V16UiV16fV16UiUsIi", "nV:512
TARGET_BUILTIN(__builtin_ia32_vcvttps2iubs128_mask, "V4UiV4fV4UiUc",
"nV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvttps2iubs256_mask, "V8UiV8fV8UiUcIi",
"nV:25
@@ -624,3 +624,440 @@ defm VCVTTPS2IUBS : avx10_sat_cvt_base<0x6a,
"vcvttps2iubs", SchedWriteVecIMul,
avx512vl_i32_info, avx512vl_f32_info,
X86vcvttp2iubsSAE>,
AVX512PDIi8Base, T_MA
@@ -0,0 +1,286 @@
+/*===- avx10_2_512convertintrin.h - AVX10_2_512CONVERT -===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apac
@@ -624,3 +624,440 @@ defm VCVTTPS2IUBS : avx10_sat_cvt_base<0x6a,
"vcvttps2iubs", SchedWriteVecIMul,
avx512vl_i32_info, avx512vl_f32_info,
X86vcvttp2iubsSAE>,
AVX512PDIi8Base, T_MA
@@ -0,0 +1,286 @@
+/*===- avx10_2_512convertintrin.h - AVX10_2_512CONVERT -===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apac
@@ -0,0 +1,286 @@
+/*===- avx10_2_512convertintrin.h - AVX10_2_512CONVERT -===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apac
@@ -624,3 +624,440 @@ defm VCVTTPS2IUBS : avx10_sat_cvt_base<0x6a,
"vcvttps2iubs", SchedWriteVecIMul,
avx512vl_i32_info, avx512vl_f32_info,
X86vcvttp2iubsSAE>,
AVX512PDIi8Base, T_MA
https://github.com/phoebewang edited
https://github.com/llvm/llvm-project/pull/101600
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https://github.com/phoebewang commented:
Just found I didn't publish the comments..
https://github.com/llvm/llvm-project/pull/101600
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@@ -0,0 +1,115 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-linux -mattr=+avx10.2-256 | FileCheck %s
--check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-linux -mattr=+avx10.2-256 | FileCheck %s
--check-prefix=X6
@@ -0,0 +1,453 @@
+/*===--- avx10_2satcvtdsintrin.h - AVX512SATCVTDS intrinsics
===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Ap
@@ -324,7 +324,14 @@ X86TargetLowering::X86TargetLowering(const
X86TargetMachine &TM,
}
}
- if (Subtarget.hasSSE2()) {
+ if (Subtarget.hasAVX10_2() || Subtarget.hasAVX10_2_512()) {
phoebewang wrote:
Check `Subtarget.hasAVX10_2()` is enough.
https://
@@ -0,0 +1,302 @@
+/*===- avx10_2_512satcvtdsintrin.h - AVX10_2_512SATCVTDS intrinsics ===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apac
@@ -0,0 +1,453 @@
+/*===--- avx10_2satcvtdsintrin.h - AVX512SATCVTDS intrinsics
===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Ap
@@ -150,9 +150,11 @@ set(x86_files
avx10_2_512minmaxintrin.h
avx10_2_512niintrin.h
avx10_2_512satcvtintrin.h
+ avx10_2_512satcvtdsintrin.h
avx10_2minmaxintrin.h
avx10_2niintrin.h
avx10_2satcvtintrin.h
+ avx10_2satcvtdsintrin.h
phoebewang wrote:
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