[gcc r15-3830] RISC-V: testsuite: Fix SELECT_VL SLP fallout.

https://gcc.gnu.org/g:4bd3ccae58d40fad6bd99ed08ef4e1e4d70fefd0 commit r15-3830-g4bd3ccae58d40fad6bd99ed08ef4e1e4d70fefd0 Author: Robin Dapp Date: Thu Sep 19 05:08:47 2024 -0700 RISC-V: testsuite: Fix SELECT_VL SLP fallout. This fixes asm-scan fallout from r15-3712-g5e3a4a01785e2d

[gcc r15-3829] RISC-V: Add more vector-vector extract cases.

https://gcc.gnu.org/g:be50c763a07893416419b82538f259f43e0773d4 commit r15-3829-gbe50c763a07893416419b82538f259f43e0773d4 Author: Robin Dapp Date: Tue Sep 3 17:53:34 2024 +0200 RISC-V: Add more vector-vector extract cases. This adds a V16SI -> V4SI and related i.e. "quartering" vec

[gcc r15-3828] RISC-V: Fix effective target check.

https://gcc.gnu.org/g:e45537f56250f19cdf2ec09a744c6b11170c1001 commit r15-3828-ge45537f56250f19cdf2ec09a744c6b11170c1001 Author: Robin Dapp Date: Fri Aug 30 14:35:08 2024 +0200 RISC-V: Fix effective target check. The return value is inverted in check_effective_target_rvv_zvl256b_o

[gcc r15-3282] RISC-V: Fix subreg of VLS modes larger than a vector [PR116086].

https://gcc.gnu.org/g:4ff4875a79ccb302dc2401c32fe0af2187b61b99 commit r15-3282-g4ff4875a79ccb302dc2401c32fe0af2187b61b99 Author: Robin Dapp Date: Tue Aug 27 10:25:34 2024 +0200 RISC-V: Fix subreg of VLS modes larger than a vector [PR116086]. When the source mode is potentially lar

[gcc r15-3120] optabs-query: Use opt_machine_mode for smallest_int_mode_for_size [PR115495].

https://gcc.gnu.org/g:96fe95bac67c7303dc811c04f5e99cc959a7182a commit r15-3120-g96fe95bac67c7303dc811c04f5e99cc959a7182a Author: Robin Dapp Date: Tue Aug 20 14:02:09 2024 +0200 optabs-query: Use opt_machine_mode for smallest_int_mode_for_size [PR115495]. In get_best_extraction_in

[gcc r15-3119] RISC-V: Expand vec abs without masking.

https://gcc.gnu.org/g:c22d57cdc52d990eb7d353fa82c67882bc824d40 commit r15-3119-gc22d57cdc52d990eb7d353fa82c67882bc824d40 Author: Robin Dapp Date: Fri Aug 9 15:05:39 2024 +0200 RISC-V: Expand vec abs without masking. Standard abs synthesis during expand is max (a, -a). This ex

[gcc r15-2649] RISC-V: Correct mode_idx attribute for viwalu wx variants [PR116149].

https://gcc.gnu.org/g:f15cd1802129454029f7fcc8ee3ddd56a86cdad8 commit r15-2649-gf15cd1802129454029f7fcc8ee3ddd56a86cdad8 Author: Robin Dapp Date: Wed Jul 31 16:54:03 2024 +0200 RISC-V: Correct mode_idx attribute for viwalu wx variants [PR116149]. In PR116149 we choose a wrong vect

[gcc r15-2337] RISC-V: Work around bare apostrophe in error string.

https://gcc.gnu.org/g:3f2bf415b447a0f6bc424c688b06e1f5946688a0 commit r15-2337-g3f2bf415b447a0f6bc424c688b06e1f5946688a0 Author: Robin Dapp Date: Fri Jul 26 12:58:38 2024 +0200 RISC-V: Work around bare apostrophe in error string. An unquoted apostrophe slipped through when testing

[gcc r15-2301] RISC-V: Error early with V and no M extension.

https://gcc.gnu.org/g:e589ffb6d78881572ddea21df0d9b6c2641d574d commit r15-2301-ge589ffb6d78881572ddea21df0d9b6c2641d574d Author: Robin Dapp Date: Wed Jul 24 09:08:00 2024 +0200 RISC-V: Error early with V and no M extension. For calculating the value of a poly_int at runtime we use

[gcc r15-2300] RISC-V: Allow LICM hoist POLY_INT configuration code sequence

https://gcc.gnu.org/g:4cbbce045681c234387d8d56376ea179dc869229 commit r15-2300-g4cbbce045681c234387d8d56376ea179dc869229 Author: Juzhe-Zhong Date: Thu Feb 1 23:45:50 2024 +0800 RISC-V: Allow LICM hoist POLY_INT configuration code sequence Realize in recent benchmark evaluation (co

[gcc r15-1861] RISC-V: Use tu policy for first-element vec_set [PR115725].

https://gcc.gnu.org/g:acc3b703c05debc6276451f9daae5d0ffc797eac commit r15-1861-gacc3b703c05debc6276451f9daae5d0ffc797eac Author: Robin Dapp Date: Mon Jul 1 13:37:17 2024 +0200 RISC-V: Use tu policy for first-element vec_set [PR115725]. This patch changes the tail policy for vmv.s.

[gcc r15-1187] vect: Merge loop mask and cond_op mask in fold-left reduction [PR115382].

https://gcc.gnu.org/g:2b438a0d2aa80f051a09b245a58f643540d4004b commit r15-1187-g2b438a0d2aa80f051a09b245a58f643540d4004b Author: Robin Dapp Date: Fri Jun 7 14:36:41 2024 +0200 vect: Merge loop mask and cond_op mask in fold-left reduction [PR115382]. Currently we discard the cond-o

[gcc r15-1061] RISC-V: Regenerate opt urls.

https://gcc.gnu.org/g:037fc4d1012dc9d533862ef7e2c946249877dd71 commit r15-1061-g037fc4d1012dc9d533862ef7e2c946249877dd71 Author: Robin Dapp Date: Thu Jun 6 09:32:28 2024 +0200 RISC-V: Regenerate opt urls. I wasn't aware that I needed to regenerate the opt urls when adding an o

[gcc r15-1043] check_GNU_style: Use raw strings.

https://gcc.gnu.org/g:03e1a7270314800eb33632f778401570e65345bd commit r15-1043-g03e1a7270314800eb33632f778401570e65345bd Author: Robin Dapp Date: Mon May 13 22:05:57 2024 +0200 check_GNU_style: Use raw strings. This silences some warnings when using check_GNU_style. contr

[gcc r15-1042] RISC-V: Introduce -mvector-strict-align.

https://gcc.gnu.org/g:68b0742a49de7122d5023f0bf46460ff2fb3e3dd commit r15-1042-g68b0742a49de7122d5023f0bf46460ff2fb3e3dd Author: Robin Dapp Date: Tue May 28 21:19:26 2024 +0200 RISC-V: Introduce -mvector-strict-align. this patch disables movmisalign by default and introduces t

[gcc r15-957] RISC-V: Remove dead perm series code and document.

https://gcc.gnu.org/g:30cfdd6ff56972d9d1b9dbdd43a8333c85618775 commit r15-957-g30cfdd6ff56972d9d1b9dbdd43a8333c85618775 Author: Robin Dapp Date: Fri May 17 12:48:52 2024 +0200 RISC-V: Remove dead perm series code and document. With the introduction of shuffle_series_patterns the e

[gcc r15-956] RISC-V: Add vector popcount, clz, ctz.

https://gcc.gnu.org/g:6fa4b0135439d64c0ea1816594d7dc830e836376 commit r15-956-g6fa4b0135439d64c0ea1816594d7dc830e836376 Author: Robin Dapp Date: Wed May 15 17:41:07 2024 +0200 RISC-V: Add vector popcount, clz, ctz. This patch adds the zvbb vcpop, vclz and vctz to the autovec machi

[gcc r15-955] RISC-V: Add vandn combine helper.

https://gcc.gnu.org/g:f48448276f29a3823827292c72b7fc8e9cd39e1e commit r15-955-gf48448276f29a3823827292c72b7fc8e9cd39e1e Author: Robin Dapp Date: Wed May 15 15:01:35 2024 +0200 RISC-V: Add vandn combine helper. This patch adds a combine pattern for vandn as well as tests for it.

[gcc r15-954] RISC-V: Use widening shift for scatter/gather if applicable.

https://gcc.gnu.org/g:309ee005aa871286c8daccbce7586f82be347440 commit r15-954-g309ee005aa871286c8daccbce7586f82be347440 Author: Robin Dapp Date: Fri May 10 13:37:03 2024 +0200 RISC-V: Use widening shift for scatter/gather if applicable. With the zvbb extension we can emit a wideni

[gcc r15-953] RISC-V: Add vwsll combine helpers.

https://gcc.gnu.org/g:af4bf422a699de0e7af5a26e02997d313e7301a6 commit r15-953-gaf4bf422a699de0e7af5a26e02997d313e7301a6 Author: Robin Dapp Date: Mon May 13 22:09:35 2024 +0200 RISC-V: Add vwsll combine helpers. This patch enables the usage of vwsll in autovec context by adding the

[gcc r15-952] RISC-V: Split vwadd.wx and vwsub.wx and add helpers.

https://gcc.gnu.org/g:9781885a624f3e29634d95c14cd10940cefb1a5a commit r15-952-g9781885a624f3e29634d95c14cd10940cefb1a5a Author: Robin Dapp Date: Thu May 16 12:43:43 2024 +0200 RISC-V: Split vwadd.wx and vwsub.wx and add helpers. vwadd.wx and vwsub.wx have the same problem vfwadd.w

[gcc r15-951] RISC-V: Do not allow v0 as dest when merging [PR115068].

https://gcc.gnu.org/g:a2fd0812a54cf51520f15e900df4cfb5874b75ed commit r15-951-ga2fd0812a54cf51520f15e900df4cfb5874b75ed Author: Robin Dapp Date: Mon May 13 13:49:57 2024 +0200 RISC-V: Do not allow v0 as dest when merging [PR115068]. This patch splits the vfw...wf pattern so we do

[gcc r15-639] RISC-V: Add initial cost handling for segment loads/stores.

https://gcc.gnu.org/g:e0b9c8ad7098fb08a25a61fe17d4274dd73e5145 commit r15-639-ge0b9c8ad7098fb08a25a61fe17d4274dd73e5145 Author: Robin Dapp Date: Mon Feb 26 13:09:15 2024 +0100 RISC-V: Add initial cost handling for segment loads/stores. This patch makes segment loads and stores mor

[gcc r15-638] internal-fn: Do not force vcond_mask operands to reg.

https://gcc.gnu.org/g:7ca35f2e430081d6ec91e910002f92d9713350fa commit r15-638-g7ca35f2e430081d6ec91e910002f92d9713350fa Author: Robin Dapp Date: Fri May 10 12:44:44 2024 +0200 internal-fn: Do not force vcond_mask operands to reg. In order to directly use constants this patch remov

[gcc r14-9972] RISC-V: Add VLS to mask vec_extract [PR114668].

https://gcc.gnu.org/g:02cc8f3e68f9af96d484d9946ceaa9e3eed38151 commit r14-9972-g02cc8f3e68f9af96d484d9946ceaa9e3eed38151 Author: Robin Dapp Date: Mon Apr 15 12:44:56 2024 +0200 RISC-V: Add VLS to mask vec_extract [PR114668]. This adds the missing VLS modes to the mask extract expa

[gcc r14-9366] vect: Do not peel epilogue for partial vectors.

https://gcc.gnu.org/g:226043a4d8fb23c7fe7bf16e485b3cfaa094db21 commit r14-9366-g226043a4d8fb23c7fe7bf16e485b3cfaa094db21 Author: Robin Dapp Date: Wed Mar 6 16:54:35 2024 +0100 vect: Do not peel epilogue for partial vectors. r14-7036-gcbf569486b2dec added an epilogue vectorization

[gcc r14-9345] RISC-V: Use vmv1r.v instead of vmv.v.v for fma output reloads [PR114200].

https://gcc.gnu.org/g:59554a50be8ebbd52e8a6348a92110af182e1874 commit r14-9345-g59554a50be8ebbd52e8a6348a92110af182e1874 Author: Robin Dapp Date: Wed Mar 6 12:15:40 2024 +0100 RISC-V: Use vmv1r.v instead of vmv.v.v for fma output reloads [PR114200]. Three-operand instructions like

[gcc r14-9344] RISC-V: Adjust vec unit-stride load/store costs.

https://gcc.gnu.org/g:9ae83078fe45d093bbaa02b8348f2407fe0c62d6 commit r14-9344-g9ae83078fe45d093bbaa02b8348f2407fe0c62d6 Author: Robin Dapp Date: Mon Jan 15 17:34:58 2024 +0100 RISC-V: Adjust vec unit-stride load/store costs. Scalar loads provide offset addressing while unit-strid