[llvm-branch-commits] [llvm] DebugInfo: Avoid some MMI::hasDebugInfo checks (PR #100333)

https://github.com/s-barannikov approved this pull request. https://github.com/llvm/llvm-project/pull/100333 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] DebugInfo: Avoid some MMI::hasDebugInfo checks (PR #100333)

@@ -1148,14 +1148,15 @@ sortGlobalExprs(SmallVectorImpl ) { void DwarfDebug::beginModule(Module *M) { DebugHandlerBase::beginModule(M); - if (!Asm || !MMI->hasDebugInfo()) + if (!Asm) return; unsigned NumDebugCUs = std::distance(M->debug_compile_units_begin(),

[llvm-branch-commits] [llvm] CodeGen: Move current call site out of MachineModuleInfo (PR #100369)

@@ -188,6 +188,14 @@ class FunctionLoweringInfo { /// SelectionDAGISel::PrepareEHLandingPad(). unsigned ExceptionPointerVirtReg, ExceptionSelectorVirtReg; + /// The current call site index being processed, if any. 0 if none. + unsigned CurCallSite = 0; + // TODO:

[llvm-branch-commits] [llvm] CodeGen: Remove MachineModuleInfo reference from MachineFunction (PR #100357)

@@ -8619,21 +8619,21 @@ SDValue SelectionDAGBuilder::lowerStartEH(SDValue Chain, const BasicBlock *EHPadBB, MCSymbol *) { MachineFunction = DAG.getMachineFunction(); - MachineModuleInfo =

[llvm-branch-commits] [llvm] CodeGen: Remove MachineModuleInfo reference from MachineFunction (PR #100357)

https://github.com/s-barannikov approved this pull request. https://github.com/llvm/llvm-project/pull/100357 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AsmPrinter: Avoid use of MachineFunction::getMMI (PR #99751)

https://github.com/s-barannikov approved this pull request. https://github.com/llvm/llvm-project/pull/99751 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [SPARC][IAS] Reject unknown/unavailable mnemonics early in ParseInstruction (PR #96021)

https://github.com/s-barannikov edited https://github.com/llvm/llvm-project/pull/96021 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [SPARC][IAS] Reject unknown/unavailable mnemonics early in ParseInstruction (PR #96021)

https://github.com/s-barannikov approved this pull request. The downside of this approach is that you lose the ability to report the missing features (unless you implement it yourself, which would be a code duplication), that would allow to produce instead better diagnostics like "instruction

[llvm-branch-commits] [llvm] [SPARC][IAS] Rework ASI/Prefetch tag matching in prep for `ParseForAllFeatures` (PR #96020)

https://github.com/s-barannikov approved this pull request. https://github.com/llvm/llvm-project/pull/96020 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [SPARC][IAS] Rework ASI tag matching in prep for `ParseForAllFeatures` (PR #96020)

@@ -1360,6 +1372,16 @@ ParseStatus SparcAsmParser::parseBranchModifiers(OperandVector ) { return ParseStatus::Success; } +ParseStatus SparcAsmParser::parseExpression(OperandVector , s-barannikov wrote: Can you use this method in `parsePrefetchTag` too?

[llvm-branch-commits] [SPARC][IAS] Rework ASI tag matching in prep for `ParseForAllFeatures` (PR #96020)

@@ -107,10 +107,15 @@ class SparcAsmParser : public MCTargetAsmParser { ParseStatus parseBranchModifiers(OperandVector ); + ParseStatus parseExpression(OperandVector , int64_t ); + // Helper function for dealing with %lo / %hi in PIC mode. const SparcMCExpr

[llvm-branch-commits] [SPARC][IAS] Rework ASI tag matching in prep for `ParseForAllFeatures` (PR #96020)

@@ -1085,13 +1085,24 @@ ParseStatus SparcAsmParser::parseASITag(OperandVector ) { SMLoc E = Parser.getTok().getEndLoc(); int64_t ASIVal = 0; - if (is64Bit() && (getLexer().getKind() == AsmToken::Hash)) { + switch (getLexer().getKind()) { + case AsmToken::LParen: +

[llvm-branch-commits] [SPARC][IAS] Enable `ParseForAllFeatures` in `MatchOperandParserImpl` (PR #96021)

@@ -11,7 +11,7 @@ ! V9: unknown membar tag membar #BadTag -! V8: instruction requires a CPU feature not currently enabled +! V8: unexpected token ! V9: invalid membar mask number membar -127 s-barannikov

[llvm-branch-commits] [SPARC][IAS] Rework ASI tag matching in prep for `ParseForAllFeatures` (PR #96020)

@@ -1085,13 +1085,24 @@ ParseStatus SparcAsmParser::parseASITag(OperandVector ) { SMLoc E = Parser.getTok().getEndLoc(); int64_t ASIVal = 0; - if (is64Bit() && (getLexer().getKind() == AsmToken::Hash)) { + switch (getLexer().getKind()) { + case AsmToken::LParen: +

[llvm-branch-commits] [SPARC][IAS] Enable `ParseForAllFeatures` in `MatchOperandParserImpl` (PR #96021)

https://github.com/s-barannikov edited https://github.com/llvm/llvm-project/pull/96021 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [SPARC][IAS] Enable `ParseForAllFeatures` in `MatchOperandParserImpl` (PR #96021)

https://github.com/s-barannikov edited https://github.com/llvm/llvm-project/pull/96021 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [SPARC][IAS] Enable `ParseForAllFeatures` in `MatchOperandParserImpl` (PR #96021)

https://github.com/s-barannikov edited https://github.com/llvm/llvm-project/pull/96021 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [SPARC][IAS] Enable `ParseForAllFeatures` in `MatchOperandParserImpl` (PR #96021)

@@ -11,7 +11,7 @@ ! V9: unknown membar tag membar #BadTag -! V8: instruction requires a CPU feature not currently enabled +! V8: unexpected token ! V9: invalid membar mask number membar -127 s-barannikov

[llvm-branch-commits] [SPARC][IAS] Add movr(n)e alias for movr(n)z (PR #94252)

https://github.com/s-barannikov approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/94252 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org

[llvm-branch-commits] [SPARC][IAS] Add support for `prefetcha` instruction (PR #94250)

https://github.com/s-barannikov approved this pull request. https://github.com/llvm/llvm-project/pull/94250 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [SPARC][IAS] Add named prefetch tag constants (PR #94249)

https://github.com/s-barannikov approved this pull request. https://github.com/llvm/llvm-project/pull/94249 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [SPARC][IAS] Add named prefetch tag constants (PR #94249)

@@ -537,16 +537,26 @@ ! V9: stxa %g0, [%g2+%i5] #ASI_SNF ! encoding: [0xc0,0xf0,0x90,0x7d] stxa %g0, [%g2 + %i5] #ASI_SNF -! V8: error: instruction requires a CPU feature not currently enabled +! V8: error: invalid operand for

[llvm-branch-commits] [SPARC][IAS] Add support for `prefetcha` instruction (PR #94250)

@@ -557,6 +557,36 @@ ! V9: prefetch [%i1+%i2], #one_read ! encoding: [0xc3,0x6e,0x40,0x1a] prefetch [ %i1 + %i2 ], #one_read +! V8: error: malformed ASI tag, must be a constant integer expression s-barannikov wrote: I hoped a

[llvm-branch-commits] [SPARC][IAS] Add support for `prefetcha` instruction (PR #94250)

@@ -557,6 +557,36 @@ ! V9: prefetch [%i1+%i2], #one_read ! encoding: [0xc3,0x6e,0x40,0x1a] prefetch [ %i1 + %i2 ], #one_read +! V8: error: malformed ASI tag, must be a constant integer expression s-barannikov wrote: With the

[llvm-branch-commits] [SPARC][IAS] Add support for `prefetcha` instruction (PR #94250)

@@ -557,6 +557,36 @@ ! V9: prefetch [%i1+%i2], #one_read ! encoding: [0xc3,0x6e,0x40,0x1a] prefetch [ %i1 + %i2 ], #one_read +! V8: error: malformed ASI tag, must be a constant integer expression s-barannikov wrote: It is

[llvm-branch-commits] [SPARC][IAS] Add named prefetch tag constants (PR #94249)

@@ -1088,6 +1115,34 @@ ParseStatus SparcAsmParser::parseASITag(OperandVector ) { return ParseStatus::Success; } +ParseStatus SparcAsmParser::parsePrefetchTag(OperandVector ) { + SMLoc S = Parser.getTok().getLoc(); + SMLoc E = Parser.getTok().getEndLoc(); + int64_t

[llvm-branch-commits] [SPARC][IAS] Handle the case of non-4-byte aligned writeNopData (PR #94251)

https://github.com/s-barannikov approved this pull request. https://github.com/llvm/llvm-project/pull/94251 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [SPARC][IAS] Add support for `prefetcha` instruction (PR #94250)

@@ -557,6 +557,36 @@ ! V9: prefetch [%i1+%i2], #one_read ! encoding: [0xc3,0x6e,0x40,0x1a] prefetch [ %i1 + %i2 ], #one_read +! V8: error: malformed ASI tag, must be a constant integer expression s-barannikov wrote: The error

[llvm-branch-commits] [SPARC][IAS] Add named prefetch tag constants (PR #94249)

@@ -1088,6 +1115,34 @@ ParseStatus SparcAsmParser::parseASITag(OperandVector ) { return ParseStatus::Success; } +ParseStatus SparcAsmParser::parsePrefetchTag(OperandVector ) { + SMLoc S = Parser.getTok().getLoc(); + SMLoc E = Parser.getTok().getEndLoc(); + int64_t

[llvm-branch-commits] [SPARC][IAS] Add named prefetch tag constants (PR #94249)

@@ -537,16 +537,26 @@ ! V9: stxa %g0, [%g2+%i5] #ASI_SNF ! encoding: [0xc0,0xf0,0x90,0x7d] stxa %g0, [%g2 + %i5] #ASI_SNF -! V8: error: instruction requires a CPU feature not currently enabled +! V8: error: invalid operand for

[llvm-branch-commits] [SPARC][IAS] Add named prefetch tag constants (PR #94249)

https://github.com/s-barannikov commented: Please add testcases for the remaining tags https://github.com/llvm/llvm-project/pull/94249 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org

[llvm-branch-commits] [SPARC][IAS] Add named prefetch tag constants (PR #94249)

https://github.com/s-barannikov edited https://github.com/llvm/llvm-project/pull/94249 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [SPARC][IAS] Add aliases for %asr20-21 as defined in JPS1 (PR #94247)

https://github.com/s-barannikov approved this pull request. https://github.com/llvm/llvm-project/pull/94247 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [SPARC][IAS] Add support for %uhi and %ulo extensions (PR #94246)

https://github.com/s-barannikov approved this pull request. https://github.com/llvm/llvm-project/pull/94246 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [SPARC] Prefer RDPC over CALL to implement GETPCX for 64-bit target (PR #77196)

s-barannikov wrote: Yes, sure https://github.com/llvm/llvm-project/pull/77196 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [SPARC] Prefer RDPC over CALL to implement GETPCX for 64-bit target (PR #77196)

https://github.com/s-barannikov approved this pull request. https://github.com/llvm/llvm-project/pull/77196 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [SPARC] Prefer RDPC over CALL to implement GETPCX for 64-bit target (PR #77196)

@@ -0,0 +1,51 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -relocation-model=pic -mtriple=sparc | FileCheck --check-prefix=SPARC %s +; RUN: llc < %s -relocation-model=pic -mtriple=sparcv9 | FileCheck --check-prefix=SPARC64

[llvm-branch-commits] [clang] [llvm] [SPARC] Prefer RDPC over CALL to implement GETPCX for 64-bit target (PR #77196)

@@ -234,8 +244,15 @@ void SparcAsmPrinter::LowerGETPCXAndEmitMCInsts(const MachineInstr *MI, // add , %o7, OutStreamer->emitLabel(StartLabel); - MCOperand Callee = createPCXCallOP(EndLabel, OutContext); - EmitCall(*OutStreamer, Callee, STI); + if

[llvm-branch-commits] [clang] [llvm] [SPARC] Prefer RDPC over CALL to implement GETPCX for 64-bit target (PR #77196)

https://github.com/s-barannikov edited https://github.com/llvm/llvm-project/pull/77196 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [SPARC] Prefer RDPC over CALL to implement GETPCX for 64-bit target (PR #77196)

@@ -0,0 +1,59 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -relocation-model=pic -mtriple=sparc | FileCheck --check-prefix=SPARC %s +; RUN: llc < %s -relocation-model=pic -mtriple=sparcv9 | FileCheck --check-prefix=SPARC64

[llvm-branch-commits] [llvm] [clang] [SPARC] Prefer RDPC over CALL to implement GETPCX for 64-bit target (PR #77196)

@@ -118,9 +126,11 @@ def : Proc<"ma2480", [FeatureLeon, LeonCASA]>; def : Proc<"ma2485", [FeatureLeon, LeonCASA]>; def : Proc<"ma2x8x", [FeatureLeon, LeonCASA]>; def : Proc<"v9", [FeatureV9]>; -def : Proc<"ultrasparc", [FeatureV9,

[llvm-branch-commits] [clang] [llvm] [SPARC] Prefer RDPC over CALL to implement GETPCX for 64-bit target (PR #77196)

@@ -234,8 +244,15 @@ void SparcAsmPrinter::LowerGETPCXAndEmitMCInsts(const MachineInstr *MI, // add , %o7, OutStreamer->emitLabel(StartLabel); - MCOperand Callee = createPCXCallOP(EndLabel, OutContext); - EmitCall(*OutStreamer, Callee, STI); + if

[llvm-branch-commits] [llvm] [clang] [SPARC] Prefer RDPC over CALL to implement GETPCX for 64-bit target (PR #77196)

@@ -118,9 +126,11 @@ def : Proc<"ma2480", [FeatureLeon, LeonCASA]>; def : Proc<"ma2485", [FeatureLeon, LeonCASA]>; def : Proc<"ma2x8x", [FeatureLeon, LeonCASA]>; def : Proc<"v9", [FeatureV9]>; -def : Proc<"ultrasparc", [FeatureV9,

[llvm-branch-commits] [llvm] [clang] [SPARC] Prefer RDPC over CALL to implement GETPCX for 64-bit target (PR #77196)

@@ -0,0 +1,18 @@ +; RUN: llc < %s -relocation-model=pic -mtriple=sparc | FileCheck --check-prefix=CALL %s +; RUN: llc < %s -relocation-model=pic -mtriple=sparcv9 -mcpu=ultrasparc | FileCheck --check-prefix=CALL %s +; RUN: llc < %s -relocation-model=pic -mtriple=sparcv9 |

[llvm-branch-commits] [clang] [llvm] [SPARC] Prefer RDPC over CALL to implement GETPCX for 64-bit target (PR #77196)

@@ -234,8 +244,15 @@ void SparcAsmPrinter::LowerGETPCXAndEmitMCInsts(const MachineInstr *MI, // add , %o7, s-barannikov wrote: Please update the comment to include the rdpc case. https://github.com/llvm/llvm-project/pull/77196