Re-introduce the comment for the tx-fifo-resize setting for the DWC3
controller. This allows for vendors to control if they require the TX FIFO
resizing logic on their HW, as the default FIFO size configurations may
already be sufficient.
Signed-off-by: Wesley Cheng
Reviewed-by: Rob Herring
Enable the flexible TX FIFO resize logic on SM8150. Using a larger TX FIFO
SZ can help account for situations when system latency is greater than the
USB bus transmission latency.
Signed-off-by: Wesley Cheng
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 1 +
1 file changed, 1 insertion(+)
diff
---
Wesley Cheng (3):
usb: dwc3: Resize TX FIFOs to meet EP bursting requirements
arm64: boot: dts: qcom: sm8150: Enable dynamic TX FIFO resize logic
dt-bindings: usb: dwc3: Add entry for tx-fifo-resize
Documentation/devicetree/bindings/usb/dwc3.txt | 2
On 5/14/2020 8:10 PM, Rob Herring wrote:
> On Thu, May 07, 2020 at 02:59:28PM -0700, Wesley Cheng wrote:
>> Re-introduce the comment for the tx-fifo-resize setting for the DWC3
>> controller.
>
> Why?
>
Hi Rob,
Initially, the reasoning behind bringing back the DTSI p
On 5/8/2020 5:45 AM, Felipe Balbi wrote:
>
> Hi,
>
> Wesley Cheng writes:
>> Some devices have USB compositions which may require multiple endpoints
>> that support EP bursting. HW defined TX FIFO sizes may not always be
>> sufficient for these compositions.
| | 293.61
---
Wesley Cheng (3):
usb: dwc3: Resize TX FIFOs to meet EP bursting requirements
arm64: boot: dts: qcom: sm8150: Enable dynamic TX FIFO resize logic
dt-bindings: usb: dwc3: Add entry for tx-fifo-resize
Documentation/devicetree
Enable the flexible TX FIFO resize logic on SM8150. Using a larger TX FIFO
SZ can help account for situations when system latency is greater than the
USB bus transmission latency.
Signed-off-by: Wesley Cheng
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 1 +
1 file changed, 1 insertion(+)
diff
bandwidth. With some higher bMaxBurst configurations, using
a larger TX FIFO size results in better TX throughput.
Signed-off-by: Wesley Cheng
---
drivers/usb/dwc3/core.c | 2 +
drivers/usb/dwc3/core.h | 6 +++
drivers/usb/dwc3/ep0.c| 40 +++-
drivers/usb/dwc3/gadget.c
Re-introduce the comment for the tx-fifo-resize setting for the DWC3
controller.
Signed-off-by: Wesley Cheng
---
Documentation/devicetree/bindings/usb/dwc3.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt
b/Documentation
Fix errors reported by dt_binding_check, due to missing required
regulators in the example node.
Fixes: f06b9fc9a814 ("dt-bindings: phy: Add binding for qcom,usb-snps-femto-v2")
Signed-off-by: Wesley Cheng
Reported-by: Rob Herring
---
Documentation/devicetree/bindings/phy/qcom,usb-
This adds the SNPS FemtoPHY V2 driver used in QCOM SOCs. There
are potentially multiple instances of this UTMI PHY on the
SOC, all which can utilize this driver. The V2 driver will
have a different register map compared to V1.
Signed-off-by: Wesley Cheng
Reviewed-by: Philipp Zabel
Reviewed
The UFS QMP v4 PHY has a largely different register set versus USB and
PCIe. Rename the register offsets to denote that the value is specific for
the UFS PCS register.
Signed-off-by: Wesley Cheng
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 20 +--
drivers/phy/qualcomm/phy-qcom
The register map for SM8150 QMP USB SSPHY has moved
QPHY_POWER_DOWN_CONTROL to a different offset. Allow for
an offset in the register table to override default value
if it is a DP capable PHY.
Signed-off-by: Wesley Cheng
Reviewed-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 23
From: Jack Pham
Add support for SM8150 QMP USB3 PHY with the necessary
initialization sequences as well as additional QMP V4
register definitions.
Signed-off-by: Jack Pham
Signed-off-by: Wesley Cheng
Reviewed-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 153
This binding shows the descriptions and properties for the
Synopsis Femto USB PHY V2 used on QCOM platforms.
Signed-off-by: Wesley Cheng
Reviewed-by: Rob Herring
Reviewed-by: Stephen Boyd
---
.../bindings/phy/qcom,usb-snps-femto-v2.yaml | 80 ++
1 file changed, 80
of referencing index for
reset handle
Changes in v2:
- Fixed YAML errors caught by dt_binding_check
Jack Pham (1):
phy: qcom-qmp: Add SM8150 QMP USB3 PHY support
Wesley Cheng (4):
dt-bindings: phy: Add binding for qcom,usb-snps-femto-v2
phy: qcom-snps: Add SNPS USB PHY driver for QCOM based
On 5/5/2020 6:34 AM, Rob Herring wrote:
> On Mon, 4 May 2020 16:54:23 -0700, Wesley Cheng wrote:
>> This binding shows the descriptions and properties for the
>> Synopsis Femto USB PHY V2 used on QCOM platforms.
>>
>> Signed-off-by: Wesley Cheng
>> Revi
Jack Pham (1):
phy: qcom-qmp: Add SM8150 QMP USB3 PHY support
Wesley Cheng (4):
dt-bindings: phy: Add binding for qcom,usb-snps-femto-v2
phy: qcom-snps: Add SNPS USB PHY driver for QCOM based SOCs
phy: qcom-qmp: Use proper PWRDOWN offset for sm8150 USB
phy: qcom-qmp: Rename UFS
The register map for SM8150 QMP USB SSPHY has moved
QPHY_POWER_DOWN_CONTROL to a different offset. Allow for
an offset in the register table to override default value
if it is a DP capable PHY.
Signed-off-by: Wesley Cheng
Reviewed-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 23
This adds the SNPS FemtoPHY V2 driver used in QCOM SOCs. There
are potentially multiple instances of this UTMI PHY on the
SOC, all which can utilize this driver. The V2 driver will
have a different register map compared to V1.
Signed-off-by: Wesley Cheng
Reviewed-by: Philipp Zabel
Reviewed
The UFS QMP v4 PHY has a largely different register set versus USB and
PCIe. Rename the register offsets to denote that the value is specific for
the UFS PCS register.
Signed-off-by: Wesley Cheng
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 20 +--
drivers/phy/qualcomm/phy-qcom
From: Jack Pham
Add support for SM8150 QMP USB3 PHY with the necessary
initialization sequences as well as additional QMP V4
register definitions.
Signed-off-by: Jack Pham
Signed-off-by: Wesley Cheng
Reviewed-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 153
This binding shows the descriptions and properties for the
Synopsis Femto USB PHY V2 used on QCOM platforms.
Signed-off-by: Wesley Cheng
Reviewed-by: Rob Herring
Reviewed-by: Stephen Boyd
---
.../bindings/phy/qcom,usb-snps-femto-v2.yaml | 77 ++
1 file changed, 77
On 5/4/2020 12:15 AM, Vinod Koul wrote:
> Hi Wesley,
>
> On 09-04-20, 15:52, Wesley Cheng wrote:
>> This series adds support for the Synopsis 7nm HSPHY USB driver being
>> used in QCOM chipsets. The HSPHY register map differs compared to
>> other PHY revisions.
/2020 3:52 PM, Wesley Cheng wrote:
> This series adds support for the Synopsis 7nm HSPHY USB driver being
> used in QCOM chipsets. The HSPHY register map differs compared to
> other PHY revisions. In addition, modifications and updates are done
> to the QMP driver to add new regis
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