Re: [Mesa-dev] [PATCH 6/8] radv: handle sample locations during automatic layout transitions

On 6/6/19 3:41 AM, Bas Nieuwenhuizen wrote: On Wed, Jun 5, 2019 at 12:04 PM Samuel Pitoiset wrote: On 6/5/19 2:51 AM, Bas Nieuwenhuizen wrote: On Thu, May 30, 2019 at 4:02 PM Samuel Pitoiset wrote: From the Vulkan spec 1.1.109: "Some implementations may need to evaluate

[Piglit] [PATCH] framework/test: allow to set extra args with PIGLIT_VKRUNNER_EXTRA_ARGS

vkrunner recently added a new option (--device-id=) for selecting the physical device. This is quite useful in a multi-GPU scenario. This allows to set some vkrunner options via vkrunner:extra_args in the configuration file or with PIGLIT_VKRUNNER_EXTRA_ARGS. Signed-off-by: Samuel Pitoiset

Re: [Mesa-dev] [PATCH] ac/nir: Remove stale TODO

Reviewed-by: Samuel Pitoiset On 6/5/19 5:09 PM, Connor Abbott wrote: While we're here, copy the comment explaining this from radeonsi. --- src/amd/common/ac_nir_to_llvm.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd

Re: [Mesa-dev] [PATCH 6/8] radv: handle sample locations during automatic layout transitions

On 6/5/19 2:51 AM, Bas Nieuwenhuizen wrote: On Thu, May 30, 2019 at 4:02 PM Samuel Pitoiset wrote: From the Vulkan spec 1.1.109: "Some implementations may need to evaluate depth image values while performing image layout transitions. To accommodate this, inst

Re: [Mesa-dev] [PATCH 1/8] radv: allow to save/restore sample locations during meta operations

On 6/5/19 2:37 AM, Bas Nieuwenhuizen wrote: On Thu, May 30, 2019 at 4:02 PM Samuel Pitoiset wrote: This will be used for the depth decompress pass that might need to emit variable sample locations during layout transitions. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_meta.c

[Mesa-dev] [PATCH] Revert "radv: fix color conversions for normalized uint/sint formats"

For some reasons, this actually introduced rendering issues with Far Cry 3 (and probably Far Cry 4). I'm reverting it for now until I figure out the right fix. See the following link for reference: https://github.com/ValveSoftware/Proton/issues/727#issuecomment-498638025 Cc: 19.0 19.1 This

Re: [Mesa-dev] [PATCH 2/9] ac: rename LLVM <= 7 helpers for readability

Patches 1-2: Reviewed-by: Samuel Pitoiset On 6/4/19 2:02 AM, Marek Olšák wrote: From: Marek Olšák --- src/amd/common/ac_llvm_build.c | 74 +- 1 file changed, 37 insertions(+), 37 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common

[Mesa-dev] [PATCH v2] ac, radv: do not emit vec3 for raw load/store on SI

It's unsupported, only load/store format with vec3 are supported. v2: - allow to use load/store format with vec3 Fixes: 6970a9a6ca9 ("ac,radv: remove the vec3 restriction with LLVM 9+")" Signed-off-by: Samuel Pitoiset --- src/amd/common/ac_llvm_build.c| 12 ++--

Re: [Mesa-dev] [PATCH] ac, radv: fix removing the vec3 restriction on SI

On 6/3/19 9:33 PM, Marek Olšák wrote: SI doesn't support buffer_load_dwordx3 and buffer_store_dwordx3, but it supports buffer_load_format_xyz and buffer_store_format_xyz. OK, I will update. Marek On Mon, Jun 3, 2019 at 9:09 AM Samuel Pitoiset mailto:samuel.pitoi...@gmail.com>>

[Mesa-dev] [PATCH] radv: do not use gfx fast depth clears for layered depth/stencil images

The driver should only fast depth clears with the graphics path when the view covers all image layers, otherwise this might corrupt layers when HTILE is enabled. Cc: 19.0 19.1 mesa-sta...@lists.freedesktop.org Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_meta_clear.c | 1 + 1 file

Re: [Mesa-dev] [PATCH] ac, radv: fix removing the vec3 restriction on SI

On 6/3/19 3:48 PM, Matt Arsenault wrote: On Jun 3, 2019, at 9:13 AM, Samuel Pitoiset wrote: I thought LLVM was able to handle that itself but actually it does not. That means we shouldn't try to emit vec3 on SI because it's unsupported. It should. Can you file a bug with an example

[Mesa-dev] [PATCH] ac, radv: fix removing the vec3 restriction on SI

I thought LLVM was able to handle that itself but actually it does not. That means we shouldn't try to emit vec3 on SI because it's unsupported. Fixes: 6970a9a6ca9 ("ac,radv: remove the vec3 restriction with LLVM 9+")" Signed-off-by: Samuel Pitoiset --- src/amd/common/ac_llvm_

Re: [Mesa-dev] [PATCH] radv: Change memory type order for GPUs without dedicated VRAM

On 6/3/19 9:46 AM, Alex Smith wrote: On Sun, 2 Jun 2019 at 11:59, Bas Nieuwenhuizen mailto:b...@basnieuwenhuizen.nl>> wrote: On Sun, Jun 2, 2019 at 12:32 PM Alex Smith mailto:asm...@feralinteractive.com>> wrote: > > Put the uncached GTT type at a higher index than the

Re: [Mesa-dev] [PATCH] radv: Change memory type order for GPUs without dedicated VRAM

Reviewed-by: Samuel Pitoiset On 6/2/19 12:32 PM, Alex Smith wrote: Put the uncached GTT type at a higher index than the visible VRAM type, rather than having GTT first. When we don't have dedicated VRAM, we don't have a non-visible VRAM type, and the property flags for GTT and visible VRAM

[Mesa-dev] [PATCH 8/8] radv: enable VK_EXT_sample_locations

Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_device.c | 8 src/amd/vulkan/radv_extensions.py | 2 +- 2 files changed, 1 insertion(+), 9 deletions(-) diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 3cf050ed220..16efc6134f1 100644 --- a/src

[Mesa-dev] [PATCH 2/8] radv: allow to set dynamic sample locations to the depth decompress pass

If VK_EXT_sample_locations is used, the driver might need to emit the sample locations specified during layout transitions. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_meta_decompress.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan

[Mesa-dev] [PATCH 7/8] radv: enable HTILE for images that might need variable sample locations

This is now supported. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_image.c | 7 --- 1 file changed, 7 deletions(-) diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index b69dda39ce1..161997ae196 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan

[Mesa-dev] [PATCH 6/8] radv: handle sample locations during automatic layout transitions

matic layout transition has to take place. [...] and VkRenderPassSampleLocationsBeginInfoEXT can be chained from VkRenderPassBeginInfo to provide sample locations for layout transitions performed implicitly by a render pass instance." Signed-off-by: Samuel Pitoiset --- src/

[Mesa-dev] [PATCH 4/8] radv: handle sample locations during explicit depth/stencil transitions

ransitions performed with CmdWaitEvents() or CmdPipelineBarrier(). Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_cmd_buffer.c | 35 +--- 1 file changed, 28 insertions(+), 7 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buff

[Mesa-dev] [PATCH 0/8] radv: add support for sample locations during layout transitions

of this series enables VK_EXT_sample_locations. Please review, thanks! Samuel Pitoiset (8): radv: allow to save/restore sample locations during meta operations radv: allow to set dynamic sample locations to the depth decompress pass radv: allow the depth decompress pass to emit dynamic

[Mesa-dev] [PATCH 5/8] radv: determine the first subpass id for every attachments

Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_pass.c| 18 ++ src/amd/vulkan/radv_private.h | 3 ++- 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_pass.c b/src/amd/vulkan/radv_pass.c index 4d1e38a780e..8fa098eaac8 100644 --- a/src

[Mesa-dev] [PATCH 1/8] radv: allow to save/restore sample locations during meta operations

This will be used for the depth decompress pass that might need to emit variable sample locations during layout transitions. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_meta.c | 20 src/amd/vulkan/radv_meta.h | 2 ++ 2 files changed, 22 insertions(+) diff --git

[Mesa-dev] [PATCH 3/8] radv: allow the depth decompress pass to emit dynamic sample locations

Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_cmd_buffer.c | 3 ++- src/amd/vulkan/radv_meta.h| 6 -- src/amd/vulkan/radv_meta_decompress.c | 29 +++ 3 files changed, 31 insertions(+), 7 deletions(-) diff --git a/src/amd/vulkan

[Mesa-dev] [PATCH] radv: set the subpass before any initial subpass transitions

This might fix initial subpass transitions when multiview is used. Noticed while implementing sample locations during layout transitions. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_cmd_buffer.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/amd/vulkan

[Mesa-dev] [PATCH 1/2] radv: use CmdPushConstants when restoring constants after meta operations

Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_meta.c | 14 -- 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/src/amd/vulkan/radv_meta.c b/src/amd/vulkan/radv_meta.c index ec4fc4a6d4b..721c7039830 100644 --- a/src/amd/vulkan/radv_meta.c +++ b/src/amd/vulkan

[Mesa-dev] [PATCH 2/2] radv: use RADV_CMD_DRITY_DYNAMIC_* when restoring viewport/scissor

Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_meta.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/amd/vulkan/radv_meta.c b/src/amd/vulkan/radv_meta.c index 721c7039830..3bfe49b4dab 100644 --- a/src/amd/vulkan/radv_meta.c +++ b/src/amd/vulkan/radv_meta.c

[Mesa-dev] [PATCH] radv: enable transformFeedbackStreamsLinesTriangles

The driver should already support this without any changes. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index d04dcbed89e..16efc6134f1 100644

Re: [Mesa-dev] [PATCH 1/2] radv: always use view format when performing subpass resolves

AM Samuel Pitoiset wrote: It makes sense to use the image view formats when resolving inside subpasses, while we have to use the image formats for normal resolves. Original patch by Philip Rebohle. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110348 Signed-off-by: Samuel Pitoiset

[Mesa-dev] [PATCH] radv: allocate more space in the CS when emitting events

If the driver waits for CP DMA to be idle and emit an EOP event we need more space. This fixes a crash with Quake Champions. Cc: Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_cmd_buffer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/vulkan

[Mesa-dev] [PATCH] radv: sync before resetting a pool if there is active pending queries

Make sure to sync all previous work if the given command buffer has pending active queries. Otherwise the GPU might write queries data after the reset operation. This fixes a bunch of new dEQP-VK.query_pool.* CTS failures. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_cmd_buffer.c

[Mesa-dev] [PATCH 1/2] radv: always use view format when performing subpass resolves

It makes sense to use the image view formats when resolving inside subpasses, while we have to use the image formats for normal resolves. Original patch by Philip Rebohle. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110348 Signed-off-by: Samuel Pitoiset --- src/amd/vulkan

[Mesa-dev] [PATCH 2/2] radv: use view format when selecting the resolve path for subpasses

Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_meta_resolve.c | 21 + 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/src/amd/vulkan/radv_meta_resolve.c b/src/amd/vulkan/radv_meta_resolve.c index b4551a98637..2b97c42fc69 100644 --- a/src/amd/vulkan

Re: [Mesa-dev] [PATCH 1/7] radv: record if a render pass has depth/stencil resolve attachments

On 5/27/19 6:48 PM, Bas Nieuwenhuizen wrote: On Mon, May 27, 2019 at 5:38 PM Samuel Pitoiset wrote: Only supported with vkCreateRenderPass2(). Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_pass.c| 30 +- src/amd/vulkan/radv_private.h | 3 +++ 2

[Mesa-dev] [PATCH 2/2] radv add radv_get_resolve_pipeline() in the compute path

Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_meta_resolve_cs.c | 56 +-- 1 file changed, 36 insertions(+), 20 deletions(-) diff --git a/src/amd/vulkan/radv_meta_resolve_cs.c b/src/amd/vulkan/radv_meta_resolve_cs.c index 76612672b1c..67df4800023 100644

[Mesa-dev] [PATCH 1/2] radv: cleanup the compute resolve path for subpass

This makes use of radv_meta_resolve_compute_image() by filling a VkImageResolve region instead of duplicating code. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_meta_resolve_cs.c | 85 +-- 1 file changed, 29 insertions(+), 56 deletions(-) diff --git a/src/amd

[Mesa-dev] [PATCH 3/7] radv: implement all depth/stencil resolve modes using compute

This path supports layers but it requires to decompress HTILE before resolving. The driver also needs to fixup HTILE after the resolve. This path is probably slower than the graphics one. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_meta_resolve_cs.c | 491

[Mesa-dev] [PATCH 6/7] radv: clear the depth/stencil resolve attachment if necessary

The driver might need to clear one aspect of the depth/stencil resolve attachment before performing the resolve itself. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_meta_clear.c | 73 1 file changed, 55 insertions(+), 18 deletions(-) diff --git a/src

[Mesa-dev] [PATCH 1/7] radv: record if a render pass has depth/stencil resolve attachments

Only supported with vkCreateRenderPass2(). Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_pass.c| 30 +- src/amd/vulkan/radv_private.h | 3 +++ 2 files changed, 32 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_pass.c b/src/amd/vulkan

[Mesa-dev] [PATCH 5/7] radv: decompress HTILE if the resolve src image is compressed

It's required to decompress HTILE before resolving with the compute path. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_meta_resolve.c | 26 ++ 1 file changed, 26 insertions(+) diff --git a/src/amd/vulkan/radv_meta_resolve.c b/src/amd/vulkan

[Mesa-dev] [PATCH 7/7] radv: add support for VK_KHR_depth_stencil_resolve

Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_device.c | 21 + src/amd/vulkan/radv_extensions.py | 1 + 2 files changed, 22 insertions(+) diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 4203074a4cd..ead6d63f1c5 100644 --- a/src

[Mesa-dev] [PATCH 2/7] radv: implement all depth/stencil resolve modes using graphics

When using graphics, the driver doesn't need to decompress HTILE before resolving. This path currently doesn't support layers so we have to fallback to the compute path. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_meta_resolve_fs.c | 597 +- src/amd/vulkan

[Mesa-dev] [PATCH 4/7] radv: select the depth/stencil resolve method based on some conditions

Only fallback to the compute path for layers. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_meta_resolve.c | 77 +- 1 file changed, 64 insertions(+), 13 deletions(-) diff --git a/src/amd/vulkan/radv_meta_resolve.c b/src/amd/vulkan/radv_meta_resolve.c index

[Mesa-dev] [PATCH 0/7] radv: implement VK_KHR_depth_stencil_resolve

but it requires a decompression pass. All CTS tests pass on Polaris10 and Vega10. Please review, Thanks! Samuel Pitoiset (7): radv: record if a render pass has depth/stencil resolve attachments radv: implement all depth/stencil resolve modes using graphics radv: implement all depth/stencil

[Mesa-dev] [PATCH v2] radv: ignore the loadOp if the first use of an attachment is a resolve

Based on ANV. v2: - remove the if statement - update the comment Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_meta_resolve.c | 12 +++- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/src/amd/vulkan/radv_meta_resolve.c b/src/amd/vulkan/radv_meta_resolve.c

Re: [Mesa-dev] [PATCH] radv: ignore the loadOp if the first use of an attachment is a resolve

On 5/26/19 2:50 PM, Bas Nieuwenhuizen wrote: On Wed, May 22, 2019 at 11:20 AM Samuel Pitoiset wrote: Based on ANV. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_meta_resolve.c | 21 - 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/src/amd

[Mesa-dev] [PATCH] radv: flush pending query reset caches before copying results

From the Vulkan spec 1.1.108: "vkCmdCopyQueryPoolResults is guaranteed to see the effect of previous uses of vkCmdResetQueryPool in the same queue, without any additional synchronization." Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_qu

Re: [Mesa-dev] [PATCH v2] radv: implement VK_EXT_sample_locations

during layout transitions? AFAIK those are needed for e.g. HTILE decompression as it is based on equations somehow. On Thu, May 16, 2019 at 11:51 AM Samuel Pitoiset mailto:samuel.pitoi...@gmail.com>> wrote: > > Basically, this extension allows applicat

[Mesa-dev] [PATCH v3] radv: implement VK_EXT_sample_locations

: - change sampleLocationCoordinateRange[1] to 0.9375 - compute and emit PA_SC_CENTROID_PRIORITY_{0,1} - rebased on top of master - some cleanups Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_cmd_buffer.c | 223 ++ src/amd/vulkan/radv_device.c

[Mesa-dev] [PATCH] radv: always dirty the framebuffer when restoring a subpass

The old code was not wrong because the transitions performed after the resolves should re-emit the framebuffer if needed. This change is mostly a no-op but it improves consistency regarding other meta operations that need to save/restore subpasses. Signed-off-by: Samuel Pitoiset --- src/amd

Re: [Mesa-dev] [PATCH v2] radv: implement VK_EXT_sample_locations

11:51 AM Samuel Pitoiset mailto:samuel.pitoi...@gmail.com>> wrote: > > Basically, this extension allows applications to use custom > sample locations. It doesn't support variable sample locations > during subpass. Note that we don't have to upload the use

[Mesa-dev] [PATCH] radv: tidy up GetQueryPoolResults for occlusion queries

Just move the block that checks the availability bit into the switch like other query types. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_query.c | 12 +--- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c

[Mesa-dev] [PATCH] radv: add radv_clear_htile() helper

This helper will be useful for clearing HTILE after some depth/stencil resolves. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_cmd_buffer.c | 7 +-- src/amd/vulkan/radv_meta.h | 3 +++ src/amd/vulkan/radv_meta_clear.c | 12 3 files changed, 16 insertions(+), 6

[Mesa-dev] [PATCH] radv: ignore the loadOp if the first use of an attachment is a resolve

Based on ANV. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_meta_resolve.c | 21 - 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/src/amd/vulkan/radv_meta_resolve.c b/src/amd/vulkan/radv_meta_resolve.c index ade5d438438..6a8abce1ddb 100644 --- a/src

[Mesa-dev] [PATCH] radv: fix the availability bit for timestamp queries

to zero, and it uses a COND_WRITE to packet to set the bit if the timestamp is ready. This fixes dEQP-VK.pipeline.timestamp.misc_tests.reset_query_before_copy. Signed-off-by: Samuel Pitoiset --- src/amd/common/sid.h| 3 +++ src/amd/vulkan/radv_query.c | 31 +-- 2

[Mesa-dev] [PATCH] radv: do not reset query pool during creation

From the Vulkan spec 1.1.108: "After query pool creation, each query must be reset before it is used." So, the driver doesn't need to do this at creation time. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_query.c | 3 --- 1 file changed, 3 deletions(-) diff --git

[Mesa-dev] [PATCH 3/3] radv: use only one descriptor in the fmask expand pass

This removes one useless SMEM load operations which pointed to the same descriptor anyway. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_meta_fmask_expand.c | 27 +++-- 1 file changed, 3 insertions(+), 24 deletions(-) diff --git a/src/amd/vulkan

[Mesa-dev] [PATCH 2/3] radv: set ACCESS_NON_READABLE on the fmask expand pass output image

The driver will emit GLC=1. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_meta_fmask_expand.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/amd/vulkan/radv_meta_fmask_expand.c b/src/amd/vulkan/radv_meta_fmask_expand.c index 12533935348..44068edc89e 100644 --- a/src/amd

[Mesa-dev] [PATCH 1/3] radv: remove one useless image type in the fmask expand shader

Both input and output images use the same type. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_meta_fmask_expand.c | 9 +++-- 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/src/amd/vulkan/radv_meta_fmask_expand.c b/src/amd/vulkan/radv_meta_fmask_expand.c index

[Mesa-dev] [PATCH v2] radv: implement VK_EXT_sample_locations

: - change sampleLocationCoordinateRange[1] to 0.9375 - compute and emit PA_SC_CENTROID_PRIORITY_{0,1} - rebased on top of master - some cleanups Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_cmd_buffer.c | 223 ++ src/amd/vulkan/radv_device.c

[Mesa-dev] [PATCH 4/4] radv: fix the sample max distance value for 8x

It should be 7, not 8. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/si_cmd_buffer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index 9f6f92a42be..c73c6ecd65c 100644 --- a/src/amd/vulkan/si_cmd_buffer.c

[Mesa-dev] [PATCH 1/4] radv: remove remaining code related to 16 samples

The driver only supports up to 8 samples. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_private.h | 1 - src/amd/vulkan/si_cmd_buffer.c | 50 -- 2 files changed, 51 deletions(-) diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan

[Mesa-dev] [PATCH 3/4] radv: emit correct centroid priority based on the number of samples

Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/si_cmd_buffer.c | 19 --- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index 56d7a9a3682..9f6f92a42be 100644 --- a/src/amd/vulkan/si_cmd_buffer.c

[Mesa-dev] [PATCH 2/4] radv: clean up the sample locations codebase

Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_cmd_buffer.c | 2 +- src/amd/vulkan/radv_pipeline.c | 2 +- src/amd/vulkan/radv_private.h| 4 +- src/amd/vulkan/si_cmd_buffer.c | 166 ++- 4 files changed, 76 insertions(+), 98 deletions(-) diff

[Mesa-dev] [PATCH] radv: decompress FMASK before performing a MSAA decompress using FMASK

This fixes some CTS failures related to VK_EXT_sample_locations. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_cmd_buffer.c | 15 +-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index

Re: [Mesa-dev] [PATCH 2/2] ac: rename SI-CIK-VI to GFX6-GFX7-GFX8

On 5/15/19 9:26 AM, Dave Airlie wrote: From: Marek Olšák It would be nice to have a reasoning why, I assume that is what they are called internally and in the kernel, but it would be good to mention something to justify it in the commit msg. Probably because Navi will be GFX10? :-)

[Mesa-dev] [PATCH 1/2] radv: bump reported version to 1.1.107

VK_AMD_draw_indirect_count has been promoted with the suffix changed to KHR. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_cmd_buffer.c | 49 --- src/amd/vulkan/radv_extensions.py | 2 +- 2 files changed, 1 insertion(+), 50 deletions(-) diff --git a/src

[Mesa-dev] [PATCH 2/2] radv: add support for VK_KHR_uniform_buffer_standard_layout

Nothing to do. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_device.c | 6 ++ src/amd/vulkan/radv_extensions.py | 1 + 2 files changed, 7 insertions(+) diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 6daf9f48182..b197d7f9ec8 100644 --- a/src/amd

[Mesa-dev] [PATCH] radv: fix setting the number of rectangles when it's dyanmic

We need to know the number of rectangles. This fixes new CTS dEQP-VK.draw.discard_rectangles.dynamic_*. Fixes: 5db0bf99944 ("radv: Implement VK_EXT_discard_rectangles.") Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_pipeline.c | 10 ++ 1 file changed, 6 insert

[Mesa-dev] [PATCH backport] radv: apply the indexing workaround for atomic buffer operations on GFX9

("ac/nir: only use the new raw/struct image atomic intrinsics with LLVM 9+") Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen --- src/amd/common/ac_nir_to_llvm.c | 12 +++- src/amd/common/ac_shader_abi.h| 1 + src/amd/vulkan/radv_nir_to_llvm.c | 6 +

Re: [Mesa-dev] [PATCH] radv: apply the indexing workaround for atomic buffer operations on GFX9

Err no, my mistake. I will write a backport. On 5/8/19 10:54 AM, Samuel Pitoiset wrote: You mean 19.1? On 5/7/19 8:29 PM, Dylan Baker wrote: Hi Samuel, This doesn't apply cleanly on 19.0, and I'm not sure how to resolve the diff. Could you provide a packport please? Thanks, Dylan

Re: [Mesa-dev] [PATCH] radv: apply the indexing workaround for atomic buffer operations on GFX9

You mean 19.1? On 5/7/19 8:29 PM, Dylan Baker wrote: Hi Samuel, This doesn't apply cleanly on 19.0, and I'm not sure how to resolve the diff. Could you provide a packport please? Thanks, Dylan Quoting Samuel Pitoiset (2019-05-03 02:45:34) Because the new raw/struct intrinsics are buggy

Re: [Mesa-dev] [PATCH] radv: call constant folding before opt algebraic

LGTM. Thanks for double checking Tim! On 5/8/19 1:27 AM, Timothy Arceri wrote: On 8/5/19 1:51 am, Samuel Pitoiset wrote: What games are affected btw?  PERCENTAGE DELTAS    Shaders SGPRs VGPRs SpillSGPR CodeSize MaxWaves  batman-arkham-city   2581

Re: [Mesa-dev] [PATCH] radv: call constant folding before opt algebraic

What games are affected btw? Can you please double check before pushing because of the flrp changes that landed around? On 5/7/19 7:14 AM, Timothy Arceri wrote: ping! On 2/5/19 1:38 pm, Timothy Arceri wrote: The pattern of calling opt algebraic first seems to have originated in i965. The

Re: [Mesa-dev] Mesa (master): nir/flrp: Lower flrp(±1, b, c) and flrp(a, ±1, c) differently

On 5/7/19 5:30 PM, Ian Romanick wrote: On 5/7/19 8:20 AM, Samuel Pitoiset wrote: This introduces glitches with Talos and Serious Sam 2017 with RADV... Are you able to reproduce the problem with ANV? Probably not very easily. If you can figure out which shader it is, it should be easy

Re: [Mesa-dev] Mesa (master): nir/flrp: Lower flrp(±1, b, c) and flrp(a, ±1, c) differently

This introduces glitches with Talos and Serious Sam 2017 with RADV... Are you able to reproduce the problem with ANV? On 5/7/19 8:01 AM, GitLab Mirror wrote: Module: Mesa Branch: master Commit: 5b908db604b2f47bb8382047533e556db8d5f52b URL:

[Mesa-dev] [PATCH] radv: add a workaround for Monster Hunter World and LLVM 7&8

://reviews.llvm.org/D61313. Cc: "19.0" "19.1" Signed-off-by: Samuel Pitoiset --- src/amd/common/ac_llvm_util.c | 7 --- src/amd/common/ac_llvm_util.h | 1 + src/amd/vulkan/radv_debug.h | 1 + src/amd/vulkan/radv_device.c | 8 src/amd/vulkan/radv_shader.c | 2 ++

Re: [Mesa-dev] [PATCH] radv: call constant folding before opt algebraic

Seems fine to, Reviewed-by: Samuel Pitoiset Bas, any comments? On 5/7/19 7:14 AM, Timothy Arceri wrote: ping! On 2/5/19 1:38 pm, Timothy Arceri wrote: The pattern of calling opt algebraic first seems to have originated in i965. The order in OpenGL drivers generally doesn't matter because

Re: [Mesa-dev] [PATCH 0/3] radeonsi: handle unaligned vertex buffers in hardware

On 5/3/19 12:39 PM, Nicolai Hähnle wrote: On 30.04.19 21:20, Marek Olšák wrote: Why can we not use tbuffer loads? tbuffer_load_format has the exact same limitations as buffer_load_format. They both use the same hardware path, the only difference is that tbuffer_load_format gets the format

[Mesa-dev] [PATCH] radv: apply the indexing workaround for atomic buffer operations on GFX9

nsics with LLVM 9+") Signed-off-by: Samuel Pitoiset --- src/amd/common/ac_nir_to_llvm.c | 12 +++- src/amd/common/ac_shader_abi.h| 1 + src/amd/vulkan/radv_nir_to_llvm.c | 6 ++ 3 files changed, 14 insertions(+), 5 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/

[Mesa-dev] [PATCH] radv: fix radv_get_aspect_format() for D+S formats

This restores the previous behaviour before YCBCR landed. For D+S formats, it returns the depth format. This fixes an assertion with Thrones of Britannia. Fixes: 66507cc6563 ("radv: Add single plane image views & meta operations") Signed-off-by: Samuel Pitoiset --- src/amd/vulka

[Mesa-dev] [PATCH] radv: only need to force emit the TCS regs on Vega10 and Ravenv1

Other GFX9 chips aren't affected. Cc: "19.0" "19.1" Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_nir_to_llvm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index b4a1

Re: [Mesa-dev] [PATCH] radv: do not need to force emit the TCS regs on Vega20

On 5/2/19 5:35 PM, Marek Olšák wrote: This bug is only on Vega10 and Raven1. Yep, I figured after pushing... I will update the workaround. Thanks Marek! Marek On Wed, May 1, 2019 at 10:10 AM Samuel Pitoiset mailto:samuel.pitoi...@gmail.com>> wrote: This chip doesn'

[Mesa-dev] [PATCH v3] ac, radv: remove the vec3 restriction with LLVM 9+

653664 -> 8630316 (-0.27 %) bytes Max Waves: 60811 -> 60737 (-0.12 %) v3: - rebase on top of master - remove the restriction for SSBO stores as well v2: - fix llvm 8 Signed-off-by: Samuel Pitoiset --- I plan to run benchmarks with that change. src/amd/common/ac_llvm_build.c

[Mesa-dev] [PATCH] radv: set WD_SWITCH_ON_EOP=1 when drawing primitives from a stream output buffer

According to RadeonSI, this seems to be required by the hardware to avoid GPU hangs. I think I just forgot to set that bit when I implemented VK_EXT_transform_feedback. This fixes a GPU hang with Space Engineers and DXVK. Cc: "19.0" "19.1" Signed-off-by: Samuel Pitoiset

Re: [Mesa-dev] Mesa (staging/19.0): radv: enable descriptor indexing capabilities

that 028ce527395642b68612d10c6030be5d4706a65e also was, and it looks like I did not CC that to 19.0, partially because of a lot of dependencies. Might make more sense to disable the ext on the 19.0 branch. Yes, that seems better to disable it. Can you send a patch? On Wed, May 1, 2019 at 9:56 PM Samuel

Re: [Mesa-dev] Mesa (staging/19.0): radv: enable descriptor indexing capabilities

wait what? Are we backporting a new feature into a stable branch? Do we really need that? On 5/1/19 6:35 PM, GitLab Mirror wrote: Module: Mesa Branch: staging/19.0 Commit: a1cdab7bd4ecad7c1c518fb8430613a7559d4f9d URL:

[Mesa-dev] [PATCH] radv: do not need to force emit the TCS regs on Vega20

This chip doesn't need the fixup. This fixes a bunch of dEQP-VK.tessellation tests and avoid random GPU hangs. Cc: "19.0" Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_nir_to_llvm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/

[Mesa-dev] [PATCH v2] radv: implement a workaround for VK_EXT_conditional_rendering

: e45ba51ea45 ("radv: add support for VK_EXT_conditional_rendering") Reported-by: Philip Rebohle Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen (v1) --- src/amd/vulkan/radv_cmd_buffer.c | 47 ++-- 1 file changed, 44 insertions(+), 3 deletions(-) diff -

Re: [Mesa-dev] [PATCH v3] radv: fix set_output_usage_mask() with composite and 64-bit types

Reviewed-by: Samuel Pitoiset On 4/27/19 11:47 AM, Rhys Perry wrote: It previously used var->type instead of deref_instr->type and didn't handle 64-bit outputs. This fixes lots of transform feedback CTS tests involving transform feedback and geometry shaders (mostl

[Mesa-dev] [PATCH] radv: add missing VEGA20 chip in radv_get_device_name()

Otherwise it returns "AMD RADV unknown". Cc: 19.0 Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_device.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index b7f991fce72..8340bf52c11 100644 --- a/src/

Re: [Mesa-dev] [PATCH] ac, ac/nir: use a better sync scope for shared atomics

Thanks for your investigations Rhys. As discussed over IRC, this makes sense to me. Reviewed-by: Samuel Pitoiset On 4/26/19 3:48 PM, Rhys Perry wrote: https://reviews.llvm.org/rL356946 (present in LLVM 9 and later) changed the meaning of the "system" sync scope, making it

Re: [Mesa-dev] [PATCH] radv: implement a workaround for VK_EXT_conditional_rendering

On 4/26/19 1:58 PM, Samuel Pitoiset wrote: Per the Vulkan spec 1.1.107, the predicate is a 32-bit value. Though the AMD hardware treats it as a 64-bit value which means it might fail to discard. I don't know why this extension has been drafted like that but this definitely not fit with AMD

[Mesa-dev] [PATCH] radv: implement a workaround for VK_EXT_conditional_rendering

value for the predicate, so we need to implement a workaround. This fixes an issue when DXVK enables conditional rendering with RADV. Fixes: e45ba51ea45 ("radv: add support for VK_EXT_conditional_rendering") Reported-by: Philip Rebohle Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nie

[Mesa-dev] [PATCH] ac: tidy up ac_build_llvm8_tbuffer_{load, store}

For consistency with ac_build_llvm8_buffer_{load,store}_common helpers and that will help a bit for removing the vec3 restriction. Signed-off-by: Samuel Pitoiset --- src/amd/common/ac_llvm_build.c | 26 +- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git

Re: [Mesa-dev] [PATCH] nir: fix nir_remove_unused_varyings()

Reviewed-by: Samuel Pitoiset Thanks fo the fix Tim! On 4/25/19 3:17 AM, Timothy Arceri wrote: We were only setting the used mask for the first component of a varying. Since the linking opts split vectors into scalars this has mostly worked ok. However this causes an issue where for example

Re: [Mesa-dev] [PATCH 1/1] radv: consider MESA_VK_VERSION_OVERRIDE when setting the api version

Reviewed-by: Samuel Pitoiset On 4/24/19 2:54 PM, Bas Nieuwenhuizen wrote: Reviewed-by: Bas Nieuwenhuizen On Wed, Apr 24, 2019 at 2:40 PM Eleni Maria Stea wrote: Before setting the physical device API version, we should check if the MESA_VK_VERSION_OVERRIDE environment variable is set

Re: [Mesa-dev] [PATCH] radeonsi: use CP DMA for the null const buffer clear on CIK

looks okay? Thanks, Dylan Quoting Samuel Pitoiset (2019-04-16 08:24:01) I don't have much context for that issue, so: Acked-by: Samuel Pitoiset On 4/12/19 10:15 PM, Marek Ol\u0161 k wrote: Done locally. Marek On Fri, Apr 12, 2019 at 12:20 PM Samuel Pitoiset wrote: I

Re: [Mesa-dev] [PATCH 1/2] nir: add an option for skipping split_alu_of_phi

On 4/23/19 5:16 PM, Jason Ekstrand wrote: On Tue, Apr 23, 2019 at 7:46 AM Samuel Pitoiset mailto:samuel.pitoi...@gmail.com>> wrote: On 4/23/19 10:45 AM, Bas Nieuwenhuizen wrote: > On Tue, Apr 23, 2019 at 9:35 AM Samuel Pitoiset > mailto:samuel.pitoi...@gmail.com

Re: [Mesa-dev] [PATCH 1/2] nir: add an option for skipping split_alu_of_phi

On 4/23/19 10:45 AM, Bas Nieuwenhuizen wrote: On Tue, Apr 23, 2019 at 9:35 AM Samuel Pitoiset wrote: Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_shader.c | 2 +- src/compiler/nir/nir.h | 3 ++- src/compiler/nir/nir_opt_if.c

[Mesa-dev] [PATCH] radv: do not load vertex attributes that are not provided by the pipeline

Per the Vulkan spec this is definitely invalid but X4 Foundations does that and it ends up by hanging the GPU. Found while enabling validation layers with the game. The issue will be reported to the developers. Cc: "19.0" mesa-sta...@lists.freedesktop.org Signed-off-by: Samue

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