On 31/05/17 10:17 PM, Alex Deucher wrote:
> On Wed, May 31, 2017 at 1:15 AM, Michel Dänzer wrote:
>> On 31/05/17 07:31 AM, Li, Samuel wrote:
>>> From: Michel Dänzer [mailto:mic...@daenzer.net]
On 30/05/17 06:16 AM, Samuel Li wrote:
> +67FF, CF, 67FF:CF
On Thu, Jun 01, 2017 at 12:26:40PM +0800, Ken Wang wrote:
> Change-Id: If7dee7bd1074eac7faa6af724a7272f9ce6f3a98
> Signed-off-by: Ken Wang
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ---
> 1 file changed, 3 deletions(-)
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of Ken
Wang
Sent: Thursday, June 01, 2017 11:07
To: amd-gfx@lists.freedesktop.org
Cc: Wang, Ken
Subject:
On 2017年06月01日 13:29, Huang Rui wrote:
On Thu, Jun 01, 2017 at 12:19:19PM +0800, zhoucm1 wrote:
On 2017年06月01日 00:14, Huang Rui wrote:
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 33 +++-
On Thu, Jun 01, 2017 at 12:19:19PM +0800, zhoucm1 wrote:
>
>
> On 2017年06月01日 00:14, Huang Rui wrote:
> >Signed-off-by: Huang Rui
> >---
> > drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 33
> > +++-
> > drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 33
Change-Id: If7dee7bd1074eac7faa6af724a7272f9ce6f3a98
Signed-off-by: Ken Wang
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index
On 2017年06月01日 12:26, Ken Wang wrote:
Change-Id: If7dee7bd1074eac7faa6af724a7272f9ce6f3a98
Signed-off-by: Ken Wang
Reviewed-by: Chunming Zhou
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ---
1 file changed, 3 deletions(-)
diff --git
Change-Id: If7dee7bd1074eac7faa6af724a7272f9ce6f3a98
Signed-off-by: Ken Wang
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index
Change-Id: If7dee7bd1074eac7faa6af724a7272f9ce6f3a98
Signed-off-by: Ken Wang
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index
Change-Id: If7dee7bd1074eac7faa6af724a7272f9ce6f3a98
Signed-off-by: Ken Wang
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index
On 2017年05月31日 20:38, Christian König wrote:
From: Christian König
The fragment bits work differently for Vega10 compared to previous generations.
Increase the fragment size to 2MB for now to better handle that.
I checked the fragment bits in PTE, don't find
On Thu, Jun 01, 2017 at 01:00:16AM +0800, Zhang, Hawking wrote:
> I would suggest to use RREG32_SOC15/ WREG32_SOC15 to avoid code refactor
> again...
>
Right. Thanks to reminder. Will update it in next version.
Thanks,
Ray
___
amd-gfx mailing list
On Thu, Jun 01, 2017 at 12:58:02AM +0800, Koenig, Christian wrote:
> Am 31.05.2017 um 18:29 schrieb Deucher, Alexander:
>
> > -Original Message-
> > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> > Of Huang Rui
> > Sent: Wednesday, May 31, 2017
On Thu, Jun 01, 2017 at 01:04:52AM +0800, Koenig, Christian wrote:
> Am 31.05.2017 um 18:14 schrieb Huang Rui:
> > Signed-off-by: Huang Rui
> > ---
> > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 1 +
> > drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 27
From: Dave Airlie
This just splits out the fence depenency checking into it's
own function to make it easier to add semaphore dependencies.
Reviewed-by: Christian König
Signed-off-by: Dave Airlie
---
From: Dave Airlie
This interface allows importing the fence from a sync_file into
an existing drm sync object, or exporting the fence attached to
an existing drm sync object into a new sync file object.
This should only be used to interact with sync files where necessary.
From: Dave Airlie
Sync objects are new toplevel drm object, that contain a
pointer to a fence. This fence can be updated via command
submission ioctls via drivers.
There is also a generic wait obj API modelled on the vulkan
wait API (with code modelled on some amdgpu code).
Okay so Christian said he wanted lookup and replace split in the
amdgpu cs, this does this, and looks a bit cleaner, it required
changing some of the interfaces around on what is exported.
Dave.
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
In review, Christian would like to keep the logic
inside amdgpu_vm.c with a cost of slightly slower.
The loop is still optimized out with this patch.
v2: remove the if statement. Now it is not slower.
Signed-off-by: Alex Xie
---
On Wed, May 31, 2017 at 4:22 PM, Samuel Li wrote:
> From: Xiaojie Yuan
>
> v2: fix an off by one error and leading white spaces
> v3: use thread safe strtok_r(); initialize len before calling getline();
> change printf() to drmMsg(); add initial
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Leo Liu
> Sent: Wednesday, May 31, 2017 5:01 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Leo
> Subject: [PATCH 3/3] drm/amdgpu: add saved_bo to save vce 4.0 context
> when suspend
>
>
We are using PSP to resume firmware after suspend, and it is
resumed at where it got suspended, so we'd better save the
the context.
Signed-off-by: Leo Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h | 1 +
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 45
Create crtc/connector combinations based on actual adapter
information obtained from drmModeRes.
Also set MAX_CRTCs to 6 for AMD GPUs.
Signed-off-by: Harry Wentland
---
tests/kms_setmode.c | 52
1 file changed, 32
On 2017-05-31 09:32 AM, Harry Wentland wrote:
On 2017-05-31 05:37 AM, Daniel Vetter wrote:
On Tue, May 30, 2017 at 04:01:40PM -0400, Harry Wentland wrote:
AMD GPUs can have 6 CRTCs.
This requires us to allocate the combinations on the heap.
Signed-off-by: Harry Wentland
On 05/31/2017 03:54 PM, Deucher, Alexander wrote:
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Leo Liu
> Sent: Wednesday, May 31, 2017 3:28 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Leo
> Subject: [PATCH 3/3] drm/amdgpu: add
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Samuel Li
> Sent: Wednesday, May 31, 2017 4:02 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Li, Samuel; Yuan, Xiaojie
> Subject: [PATCH libdrm v5 1/1] amdgpu: move asic id table to a separate
From: Xiaojie Yuan
v2: fix an off by one error and leading white spaces
v3: use thread safe strtok_r(); initialize len before calling getline();
change printf() to drmMsg(); add initial amdgpu.ids
v4: integrate some recent internal changes, including format changes
v5:
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Leo Liu
> Sent: Wednesday, May 31, 2017 3:28 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Leo
> Subject: [PATCH 3/3] drm/amdgpu: add saved_bo to save vce 4.0 context
> when suspend
>
>
We are using PSP to resume firmware after suspend, and it is
resumed at where it got suspended, so we'd better save the
the context.
Signed-off-by: Leo Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h | 1 +
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 39
To simplify vce bo create
Signed-off-by: Leo Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 27 +++
1 file changed, 3 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index
Signed-off-by: Leo Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
index 0a7f18c..c93f74a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
On 2017-05-31 02:53 AM, Christian König wrote:
2. How are the priorities from processes supposed to interact with
the per context priority?
Do you mean process niceness?
There isn't any relationship between niceness and gpu priority.
Let me know if you meant something different here.
I
Hi Christian,
I have asked for code review of a new patch.
It turns out that the index operation is not needed. But there is one extra if
statement in every IB submission, which will be a slight performance hit.
Function amdgpu_vm_check_compute_bug is called in amdgpu_device_init.
Function
Hi Dave,
Just one fix for VCE3.
The following changes since commit 5ed02dbb497422bf225783f46e6eadd237d23d6b:
Linux 4.12-rc3 (2017-05-28 17:20:53 -0700)
are available in the git repository at:
git://people.freedesktop.org/~agd5f/linux drm-fixes-4.12
for you to fetch changes up to
In review, Christian would like to keep the logic
inside amdgpu_vm.c with a cost of slightly slower.
The loop is still optimized out with this patch.
Signed-off-by: Alex Xie
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++
Nothing comes to mind. It's presumably a change in the drm area so you could
limit the bisection to just drivers/gpu/drm.
From: Tom Reddish [mailto:tom.redd...@mediavuesystems.com]
Sent: Wednesday, May 31, 2017 1:48 PM
To: Deucher, Alexander
Cc: Koenig, Christian; amd-gfx@lists.freedesktop.org;
I can do that. I've looked through the changelog between the two and theres a
number of things related to drm and radeon but I'm not exactly sure what I
should be looking for. Are there any specific files that jump out to you in
your head that would be handling this part of interaction with the
I would suggest to use RREG32_SOC15/ WREG32_SOC15 to avoid code refactor
again...
Regards,
Hawking
-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of Huang
Rui
Sent: Thursday, June 01, 2017 0:15
To: amd-gfx@lists.freedesktop.org; Deucher,
LG Displays are being reported as "disconnected" when they are powered off
(currently connected through DVI to mini-displayport adapter)
Only seeing this with LG displays (have tested NEC and Samsung *limited model
types for each manufacturer*). With the LG display connected to the graphics
What do you mean by bisect?
My gut is telling me it's something that changed in the kernel. Maybe the
kernel is correctly parsing the information it is being given from the display
now and in the older kernel it was handling that information differently? With
the exact same display and no
Am 31.05.2017 um 18:14 schrieb Huang Rui:
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 27 +++
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h | 1 +
3 files changed, 17
Am 31.05.2017 um 18:14 schrieb Huang Rui:
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 33 +++-
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 33 +++-
2 files changed, 40 insertions(+), 26
Am 31.05.2017 um 18:29 schrieb Deucher, Alexander:
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Huang Rui
> Sent: Wednesday, May 31, 2017 12:15 PM
> To: amd-gfx@lists.freedesktop.org; Deucher, Alexander; Koenig, Christian
> Cc: Wang,
Use git to bisect between the current problematic kernel and the last working
kernel. Bisecting is a git feature that allows you to bisect the commits
between two points to determine what change caused the regression. Google for
"git bisect howto".
Alex
From: Tom Reddish
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 33 +++-
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 33 +++-
2 files changed, 40 insertions(+), 26 deletions(-)
diff --git
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Huang Rui
> Sent: Wednesday, May 31, 2017 12:15 PM
> To: amd-gfx@lists.freedesktop.org; Deucher, Alexander; Koenig, Christian
> Cc: Wang, Ken; Huang, Ray; Huan, Alvin
> Subject: [PATCH 00/18]
Hey Harry, hey Andrey,
Harry Wentland wrote on 31.05.2017 17:52:
> From: Andrey Grodzovsky
>
> Summury of changes:
s/Summury/Summary/
> 1: Both in check and commit Connector properties were handled as
s/in// ?
>part of for_each(crtc) loop while they shoud have
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Huang Rui
> Sent: Wednesday, May 31, 2017 12:15 PM
> To: amd-gfx@lists.freedesktop.org; Deucher, Alexander; Koenig, Christian
> Cc: Wang, Ken; Huang, Ray; Huan, Alvin
> Subject: [PATCH 02/18]
> -Original Message-
> From: Huang Rui [mailto:ray.hu...@amd.com]
> Sent: Wednesday, May 31, 2017 12:15 PM
> To: amd-gfx@lists.freedesktop.org; Deucher, Alexander; Koenig, Christian
> Cc: Wang, Ken; Huan, Alvin; Huang, Ray
> Subject: [PATCH 01/18] drm/amdgpu: abstract gart table
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 61 ++-
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 101 ++-
2 files changed, 81 insertions(+), 81 deletions(-)
diff --git
Hey Harry,
you should drop this patch and remove the addition from patch 3 AFAICT.
Cheers,
Kai
P.S.: IIRC the conclusion of the last discussion was, that this code is needed
on non-x86 hardware as well. Shouldn't there at least be some TODO added
somewhere in the DCN code or maybe now in the
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 51 ++--
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 22 ++
2 files changed, 44 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Huang Rui
> Sent: Wednesday, May 31, 2017 12:15 PM
> To: amd-gfx@lists.freedesktop.org; Deucher, Alexander; Koenig, Christian
> Cc: Wang, Ken; Huang, Ray; Huan, Alvin
> Subject: [PATCH 18/18]
Can you bisect? Sounds like the monitor does not keep the EDID powered up when
the display is off as is required by the vesa spec.
Alex
From: Tom Reddish [mailto:tom.redd...@mediavuesystems.com]
Sent: Wednesday, May 31, 2017 12:20 PM
To: Deucher, Alexander; Koenig, Christian
Cc:
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 2 ++
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 2 ++
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 2 ++
User is able to follow the ip block number to write the ip_block_mask for
selecting the one which user would like to enable.
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++
1 file changed, 3 insertions(+)
diff --git
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index c6debba..08d6908 100644
---
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 -
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c| 93 --
drivers/gpu/drm/amd/amdgpu/soc15.c | 1 -
drivers/gpu/drm/amd/include/amd_shared.h | 1 -
4 files
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 -
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 93 --
drivers/gpu/drm/amd/amdgpu/soc15.c | 1 -
drivers/gpu/drm/amd/include/amd_shared.h | 1 -
4 files
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 27 +++
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h | 1 +
3 files changed, 17 insertions(+), 12 deletions(-)
diff --git
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 26 ++
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h | 1 +
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c| 2 ++
3 files changed, 17 insertions(+), 12 deletions(-)
diff --git
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4 +++-
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 12
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h | 2 ++
3 files changed, 13 insertions(+), 5 deletions(-)
diff --git
This patch moves invalidation into gart enable function from hw_init.
Because we would like align the sequence calling between init and resume.
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 27 +++
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 55 ---
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 56 +---
2 files changed, 59 insertions(+), 52 deletions(-)
diff --git
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 37 ++--
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 36 +--
2 files changed, 41 insertions(+), 32 deletions(-)
diff --git
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 22 --
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 27 ---
2 files changed, 32 insertions(+), 17 deletions(-)
diff --git
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 72 +++---
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 88 +++-
2 files changed, 62 insertions(+), 98 deletions(-)
diff --git
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 34 +---
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 33 +--
2 files changed, 36 insertions(+), 31 deletions(-)
diff --git
Hi all,
These patches refines gfxhub/mmhub programming sequence to make them clear and
readable. And actually, gfxhub + mmhub = GMCv9 for vega10, we don't need
specific gfxhub and mmhub ip blocks, and meanwhile, they have different resume
sequence during gfxhub, mmhub, and gmc. That will make
make-kpkg doesn't seem to like it
Change-Id: Ia589318e8632de57286c4a3d63a0a92a6cb96af3
Signed-off-by: Harry Wentland
Reviewed-by: Andrey Grodzovsky
Acked-by: Harry Wentland
---
From: Shirish S
The DCE engine triggers scan as soon as the luma
address is updated, since it is updated before chroma address
the chroma data is not scanned out properly or in order.
This patch fixes this by re-ordering the same.
BUG: SWDEV-119421
TEST: (On Chromium OS for
From: Indrajit Das
Change-Id: Ib61bf88eb16da50017944556995d3789735aea0c
Signed-off-by: Indrajit Das
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
From: Hersen Wu
Change-Id: Ia19bcb874b7ae22201f2b7cfef3c42c10276c6d5
Signed-off-by: Hersen Wu
Reviewed-by: Hersen Wu
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 7
From: Jerry Zuo
Check if adding surface is failed to prevent NULL pointer deref.
Change-Id: I804585bf126e74570875f4b8508358d3bad172a0
Signed-off-by: Jerry Zuo
Reviewed-by: Harry Wentland
---
From: Shirish S
This patch updates the YUV format supported to
NV12 and NV21 and hence updates the offsets.
BUG: SWDEV-119421
TEST: (On Chromium OS for Stoney Only)
* Executed below tests to see YUV(underlay) & RGB planes on eDP
plane_test --format XR24 --size 500x100
From: Dmytro Laktyushkin
Change-Id: I7df3470eb793f91e9a3d765b476bf181a56663b3
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Dmytro Laktyushkin
Acked-by: Harry Wentland
---
From: Andrey Grodzovsky
Use drm_atomic_crtc_needs_modeset instead.
Change-Id: I296cd1c8f8a2e4239a3cb814805868c14bcd20ba
Signed-off-by: Andrey Grodzovsky
Reviewed-by: Harry Wentland
---
From: Jeff Smith
Change-Id: I7ec74c131caa7d085415d5fd15c4e442a39b966a
Signed-off-by: Jeff Smith
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 1 +
1
From: Corbin McElhanney
Passing NULL as surfaceUpdates to dc_update_surfaces_and_stream now
updates just the stream. Code that is dependent on srf_updates was moved
below the NULL check.
Change-Id: Iee54909c6c89c150b376aa85c95f0307d4fa91ab
Signed-off-by: Corbin
From: Zeyu Fan
Change-Id: I486b2be53a380956b3405874ecb92d83b62135a0
Signed-off-by: Zeyu Fan
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 2 ++
1 file
DCN bw calcs currently rely on the following gcc options:
-mhard-float -msse -mpreferred-stack-boundary=4
We probably shouldn't really try building this on architectures
other than x86.
Change-Id: I63d214b2f6fe9b3fc0d59bd00563e0543f0baa8c
CC: Alex Deucher
CC:
From: Charlene Liu
Change-Id: I09afa9c67b09ec3d9e547ce71963015d8eddd499
Signed-off-by: Charlene Liu
Reviewed-by: Charlene Liu
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
1
From: Andrey Grodzovsky
Change-Id: I65f1e3920bebeac06336add3a136b0ff452782c6
Signed-off-by: Andrey Grodzovsky
Reviewed-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 42
From: Andrey Grodzovsky
Summury of changes:
1: Both in check and commit Connector properties were handled as
part of for_each(crtc) loop while they shoud have been handled
in a dedicated for_each(connector)
loop since they are connector properties. Moved.
2:
From: Amy Zhang
Change-Id: I8beaae4b027868ed3a088d89b2396b0097611830
Signed-off-by: Amy Zhang
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 5 +
1 file
* Fix missed scaler programming
* Some cleanups in atomic_check and commit_tail
* Restrict DCN to x86
* Bunch of DCN and other fixes
Amy Zhang (1):
drm/amd/display: Disable PSR entry abort to prevent intermittent
freezes
Andrey Grodzovsky (4):
drm/amd/display: program scaler not
Change-Id: Id369865feb28818a62f8eb26ce4b2dee097a7bcb
Signed-off-by: Harry Wentland
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 11 +--
1 file changed,
From: Andrey Grodzovsky
Scaler code in case of UPDATE_TYPE_MED was not called
since new pipe context and current context are the same.
Change-Id: Ib8ce1c3497fff24ce78e20a092139a755fb1423d
Signed-off-by: Andrey Grodzovsky
Reviewed-by: Dmytro
From: Dmytro Laktyushkin
Change-Id: Ie2f36ef791ae61da6a806c1b6ad6195db52afd83
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
* Fix missed scaler programming
* Some cleanups in atomic_check and commit_tail
* Restrict DCN to x86
* Bunch of DCN and other fixes
Amy Zhang (1):
drm/amd/display: Disable PSR entry abort to prevent intermittent
freezes
Andrey Grodzovsky (4):
drm/amd/display: program scaler not
Please see comments incline,
-Original Message-
From: Michel Dänzer [mailto:mic...@daenzer.net]
Sent: Wednesday, May 31, 2017 1:15 AM
To: Li, Samuel
Cc: amd-gfx@lists.freedesktop.org; Yuan, Xiaojie
Subject: Re: [PATCH libdrm v4 1/1] amdgpu: move
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Rex Zhu
> Sent: Wednesday, May 31, 2017 8:16 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhu, Rex
> Subject: [PATCH 4/4] drm/amd/powerplay: enable CKS by default on vega10.
>
> Change-Id:
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Rex Zhu
> Sent: Wednesday, May 31, 2017 8:16 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhu, Rex
> Subject: [PATCH 3/4] drm/amd/powerplay: Align with VBIOS to support AVFS
> parameters.
>
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Rex Zhu
> Sent: Wednesday, May 31, 2017 8:16 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhu, Rex
> Subject: [PATCH 2/4] drm/amd/powerplay: Add floor DCEF for DS on boot.
>
> Change-Id:
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Rex Zhu
> Sent: Wednesday, May 31, 2017 8:16 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhu, Rex
> Subject: [PATCH 1/4] drm/amd/powerplay: hardcode temp range to 0-89 for
> vega10.
>
>
On 30.05.2017 12:54, Lukas Wunner wrote:
> On Tue, May 30, 2017 at 11:34:17AM +0200, Florian Echtler wrote:
>> On 26.05.2017 23:03, Lukas Wunner wrote:
>>> On Fri, May 26, 2017 at 02:13:29PM +0200, Florian Echtler wrote:
I'm running Ubuntu 16.04.2 on a 27" unibody iMac 10,1 from 2009.
Always use the max for the family rather than the per sku limits.
This makes sure the mask is always the max size to avoid reporting
the wrong number of CUs.
Cc: sta...@vger.kernel.org
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 71
Signed-off-by: Leo Liu
Acked-by: Christian König
---
tests/amdgpu/cs_tests.c| 2 +-
tests/amdgpu/decode_messages.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/tests/amdgpu/cs_tests.c b/tests/amdgpu/cs_tests.c
index
Signed-off-by: Leo Liu
Acked-by: Christian König
---
tests/amdgpu/decode_messages.h | 30 +
tests/amdgpu/vcn_tests.c | 139 -
2 files changed, 166 insertions(+), 3 deletions(-)
diff --git
Signed-off-by: Leo Liu
Acked-by: Christian König
---
tests/amdgpu/Makefile.am | 3 +-
tests/amdgpu/amdgpu_test.c | 6 +
tests/amdgpu/amdgpu_test.h | 15 +++
tests/amdgpu/vcn_tests.c | 277 +
4 files
1 - 100 of 122 matches
Mail list logo