Re: [PATCH 1/2] drm/amdgpu/gfx: fix MEC interrupt enablement for pipes != 0

On 2017-06-09 11:16 PM, Deucher, Alexander wrote: -Original Message- From: Andres Rodriguez [mailto:andre...@gmail.com] Sent: Friday, June 09, 2017 7:49 PM To: Alex Deucher; amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander Subject: Re: [PATCH 1/2] drm/amdgpu/gfx: fix MEC interrupt

Re: [PATCH i-g-t] tests: Rename I915_MAX_PIPES to IGT_MAX_PIPES

Reviewed-by: Harry Wentland Harry On 2017-06-09 05:13 PM, sunpeng...@amd.com wrote: > From: "Leo (Sunpeng) Li" > > Name should not be driver-specific. > > Signed-off-by: Leo (Sunpeng) Li > --- > lib/igt_kms.c |

[PATCH 1/2] drm/amdgpu: vm_update_ptes remove code duplication

Signed-off-by: Harish Kasiviswanathan --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 73 -- 1 file changed, 16 insertions(+), 57 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

[PATCH 2/2] drm/amdgpu: Fix compiler warnings

Signed-off-by: Harish Kasiviswanathan --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index c308047..9743db5

[PATCH i-g-t] tests: Rename I915_MAX_PIPES to IGT_MAX_PIPES

From: "Leo (Sunpeng) Li" Name should not be driver-specific. Signed-off-by: Leo (Sunpeng) Li --- lib/igt_kms.c | 2 +- lib/igt_kms.h | 5 +++-- tests/kms_atomic_transition.c | 12 ++-- tests/kms_busy.c

[PATCH i-g-t v3] tests: Increase value of I915_MAX_PIPES to 6

From: "Leo (Sunpeng) Li" Increasing max pipe count to 6 to support AMD GPU's. Since some tests' behavior depends on this value, small changes are made to remove this dependency: * kms_ccs: Early abort if wanted_pipe is out-of-bounds. * kms_concurrent: Check if pipe is

Re: [PATCH] drm/amdgpu/vm: fix warnings

Reviewed-by: Alex Xie On 2017-06-09 12:05 PM, Alex Deucher wrote: silence uninitialized variable warnings. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)

Re: [PATCH i-g-t v2] tests: Increase value of I915_MAX_PIPES to 6

On 2017-06-09 04:17 PM, sunpeng...@amd.com wrote: > From: "Leo (Sunpeng) Li" > > Increasing max pipe count to 6 to support AMD GPU's. > > Since some tests' behavior depends on this value, small changes are made > to remove this dependency: > > * kms_ccs: Early abort if

RE: [PATCH i-g-t v2] tests: Increase value of I915_MAX_PIPES to 6

> -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of sunpeng...@amd.com > Sent: Friday, June 09, 2017 4:18 PM > To: intel-...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org; > Wentland, Harry > Cc: Li, Sun peng > Subject: [PATCH i-g-t v2]

[PATCH 8/8] drm/amdgpu: add interface for editing a foreign process's priority v2

The AMDGPU_SCHED_OP_PROCESS_PRIORITY_GET/PUT ioctls are used to set the priority of a different process in the current system. When all requests are dropped, the foreign process's contexts will be restored to the priority specified at context creation time. An fd is used to identify the remote

[PATCH 6/8] drm/amd/sched: allow clients to edit an entity's rq v2

This is useful for changing an entity's priority at runtime. v2: don't modify the order of amd_sched_entity members Signed-off-by: Andres Rodriguez --- drivers/gpu/drm/amd/scheduler/gpu_scheduler.c | 26 +++---

[PATCH 2/8] drm/amdgpu: add framework for HW specific priority settings v9

Add an initial framework for changing the HW priorities of rings. The framework allows requesting priority changes for the lifetime of an amdgpu_job. After the job completes the priority will decay to the next lowest priority for which a request is still valid. A new ring function set_priority()

[PATCH i-g-t v2] tests: Increase value of I915_MAX_PIPES to 6

From: "Leo (Sunpeng) Li" Increasing max pipe count to 6 to support AMD GPU's. Since some tests' behavior depends on this value, small changes are made to remove this dependency: * kms_ccs: Early abort if wanted_pipe is out-of-bounds. * kms_concurrent: Check if pipe is

[PATCH 27/27] drm/amd/display: disable dcc when reset front end.

From: Yongqiang Sun Change-Id: Ief8354f612161481cd303512fa41001376504f81 Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland ---

[PATCH 21/27] drm/amd/display: No need to get property before set

Get property requires a lock but if we add it we get a deadlock on MST display detection. There's really no need to get the property before setting it. Change-Id: I67d523b856665f8b2b952c2747de56be74a136de Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng

[PATCH 15/27] drm/amd/display: Refactor to call set PSR wait loop in dce_dmcu instead of dce_clocks

From: Amy Zhang Change-Id: I61437d58382fd3bdb2b02d44f4b731148543ddc9 Signed-off-by: Amy Zhang Reviewed-by: Anthony Koo Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 52

[PATCH 13/27] drm/amd/display: disable forced stutter disable after programming watermark

From: Tony Cheng vbios will disable stutter pre-OS. driver re-enable after programming watermark Change-Id: Iefec5991ca9c776156b7c8c5f20fbd938102019b Signed-off-by: Tony Cheng Reviewed-by: Charlene Liu Acked-by: Harry Wentland

[PATCH 22/27] drm/amd/display: Temporary disable BTR FreeSync support for now

From: Anthony Koo Reduce timer tick interval for the static screen Change-Id: I4096ae0ee63a02f1923b1345f909f97c71ea961f Signed-off-by: Anthony Koo Reviewed-by: Tony Cheng Acked-by: Harry Wentland ---

[PATCH 26/27] drm/amd/display: RV stereo support

From: Vitaly Prosyak HDMI frame pack and DP frame alternate in band Change-Id: I643614508abc3b93bf841ccf5f070b9566919f23 Signed-off-by: Vitaly Prosyak Reviewed-by: Tony Cheng Acked-by: Harry Wentland

[PATCH 11/27] drm/amd/display: Add assertion for invalid surface dimensions

From: Corbin McElhanney Change-Id: Ie7e9e43fc522fcd35cc8eef11a021b1984b9c9c6 Signed-off-by: Corbin McElhanney Reviewed-by: Tony Cheng Acked-by: Harry Wentland ---

[PATCH 23/27] drm/amd/display: Use surface update inuse for pending check.

From: Yongqiang Sun Change-Id: Ib7bb454bd0dd48a71bfe78601b07384c08386cc2 Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland ---

[PATCH 14/27] drm/amd/display: fix mpc alpha programming

From: Dmytro Laktyushkin Change-Id: Idee0068c6c94980de931803cb25dcf17bf774560 Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland ---

[PATCH 12/27] drm/amd/display: remove disable_clk_gate debug flag for DCN

From: Hersen Wu Change-Id: I6143202c8b6c3c730c098fc4cabcbc89d3cf8908 Signed-off-by: Hersen Wu Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 30

[PATCH 25/27] drm/amd/display: add bw logging for dcn

From: Dmytro Laktyushkin Change-Id: I6242cae575f292728fea23069514379b87f421f5 Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland ---

[PATCH 17/27] drm/amd/display: fix single link black screen

From: Charlene Liu Don't fall back to dual link DVI mode if the connector is single Link only. Change-Id: Ifef1bc5d4e38ab163e13de33fc8494baaf3b1d6b Signed-off-by: Charlene Liu Reviewed-by: Dmytro Laktyushkin Acked-by:

[PATCH 20/27] drm/amd/display: propagate surface alpha setting from OS to DC

From: Dmytro Laktyushkin Change-Id: I74a7f87d0c70a2ad1de9797ebae61976e49972ed Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland ---

[PATCH 24/27] drm/amd/display: fix enable_optc_clock reg_wait timeouts

From: Dmytro Laktyushkin Change-Id: Ie33d1204597c75114f14403a671755632a163ab9 Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland ---

[PATCH 19/27] drm/amd/display: Call program_gamut explicitly instead of entire set_plane

From: Zeyu Fan This fixes on boot crush on Vega, Polaris with Dal3. Change-Id: Ia103a8b77879d573cdab0c98b3df563fa3677f80 Signed-off-by: Zeyu Fan Reviewed-by: Tony Cheng Acked-by: Harry Wentland ---

[PATCH 16/27] drm/amd/display: Fix DRR Enable on Desktop

From: Amy Zhang - Block PSR in Full screen apps to prevent incorrect static screen curser events - Reprogram static screen events when update freesync state - Program static ramp variable active after other values are programmed - Correct wrong assigning of the nominal and

[PATCH 01/27] drm/amd/display: allow taking split pipes during resource mapping

From: Dmytro Laktyushkin Change-Id: I77bed9c869b8edfd9dfde6855b1d27f0850df2d8 Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland ---

[PATCH 06/27] drm/amd/display: Remove redundant member from amdgpu_plane.

From: Andrey Grodzovsky Change-Id: I074023eba6cec3ae1a1c06f2b4472abc7826df61 Signed-off-by: Andrey Grodzovsky Signed-off-by: Leo (Sunpeng) Li Reviewed-by: Harry Wentland ---

[PATCH 09/27] drm/amd/display: Don't update surface if dimensions are 0

From: Corbin McElhanney Change-Id: I787bcc4f2b4b3c5a13108c2451cd9f99d67d931f Signed-off-by: Corbin McElhanney Reviewed-by: Tony Cheng Acked-by: Harry Wentland ---

[PATCH 07/27] drm/amd/display: Enable DCN clock gating

From: Hersen Wu Change-Id: I8979a9b8403115d6638dda415954596c9823f555 Signed-off-by: Hersen Wu Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 68

[PATCH 04/27] drm/amd/display: Universal cursor plane hook-up.

From: Andrey Grodzovsky Switch from legacy cursor to DRM cursor plane. Cursor is not an actual plane but more of a subplane of each pipe. Bind a DRM cursor plane instance to each CRTC. Eliminate seperate FB object allocation for cursor and clean dm_crtc_cursor_set.

[PATCH 05/27] drm/amd/display: Add function to get PSR state

From: Amy Zhang Change-Id: I7359d5d7b3e6a0569863f6bea10dbf4199be172d Signed-off-by: Amy Zhang Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 13

[PATCH 03/27] drm/amd/display: fix mpo + split pipe aquisition failure

From: Dmytro Laktyushkin Change-Id: Ic0d15333971c33102b887b8c425b6c4231d03d8b Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland ---

[PATCH 00/27] DC Linux Patches Jun 9, 2017

* Universal cursor plane * Bunch of Raven fixes * Couple of fixes for IGT Amy Zhang (3): drm/amd/display: Add function to get PSR state drm/amd/display: Refactor to call set PSR wait loop in dce_dmcu instead of dce_clocks drm/amd/display: Fix DRR Enable on Desktop Andrey Grodzovsky

[PATCH 02/27] drm/amd/display: fix surface attachment handling of pipe split

From: Dmytro Laktyushkin Change-Id: I5f81333e21658cdd1a5c9932cfc91d6e9a56ec02 Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland ---

[PATCH 08/27] drm/amd/display: Remove unsupported RGB formats

From: "Leo (Sunpeng) Li" Do not broadcast (to DRM) unsupported RGB formats. Change-Id: If6ab99f7056b518c5c2a77b1320ea9d2f0349776 Signed-off-by: Leo (Sunpeng) Li Reviewed-by: Harry Wentland ---

Re: [PATCH 7/8] drm/amdgpu: add plumbing for ctx priority changes

On 2017-06-09 07:11 AM, Christian König wrote: Am 09.06.2017 um 00:06 schrieb Andres Rodriguez: Introduce amdgpu_ctx_priority_get/put(). This a refcounted mechanism to change a context's priority. A context's priority will be set to the highest priority for which a request exists. If no

Re: [PATCH 5/8] drm/amdgpu: move priority decay logic into amd_sched_priority_ctr

On 2017-06-09 06:54 AM, Christian König wrote: Am 09.06.2017 um 00:06 schrieb Andres Rodriguez: So that it can be re-used. A priority counter can be used to track priority requests. If no active requests exists, the counter will default to ()->default_priority. The re-factored version is

[PATCH] drm/amdgpu/vm: fix warnings

silence uninitialized variable warnings. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

Re: [Intel-gfx] [PATCH i-g-t] tests: Increase value of I915_MAX_PIPES to 6

On 2017-06-09 05:49 AM, Arkadiusz Hiler wrote: On Thu, Jun 08, 2017 at 09:48:58PM +, Deucher, Alexander wrote: -Original Message- From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of sunpeng...@amd.com Sent: Thursday, June 08, 2017 3:11 PM To:

Re: [PATCH] drm/amdgpu: add contiguous flag in ucode bo create

Hi Horace, yeah that looks good to me, feel free to add my reviewed-by line and push it. Regards, Christian. Am 09.06.2017 um 15:45 schrieb Chen, Horace: Hi Christian, Sorry, it's my first time to submit code to the staging. I have done the fix. Attached the fixed review. Thank you for

Re: [PATCH 1/2] drm/amdgpu/gfx: fix MEC interrupt enablement for pipes != 0

On 09/06/17 10:23 AM, Deucher, Alexander wrote: Could use WREG32_FIELD() here to simplify these. That doesn't work if you have variable register names as we do in this case. Which is why we have WREG32_FIELD_OFFSET :-) Tom ___ amd-gfx mailing

RE: [PATCH 2/2] drm/amdgpu/gfx: spread queues across pipes again for 1 MEC parts

OK. Regards, Shirish S From: Deucher, Alexander Sent: Friday, June 9, 2017 6:23:12 PM To: S, Shirish; amd-gfx@lists.freedesktop.org; Alex Deucher Subject: RE: [PATCH 2/2] drm/amdgpu/gfx: spread queues across pipes again for 1 MEC parts Please include patch 1 of

RE: [PATCH 1/2] drm/amdgpu/gfx: fix MEC interrupt enablement for pipes != 0

> -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Tom St Denis > Sent: Friday, June 09, 2017 9:19 AM > To: amd-gfx@lists.freedesktop.org > Subject: Re: [PATCH 1/2] drm/amdgpu/gfx: fix MEC interrupt enablement for > pipes != 0 > > On

RE: [PATCH] drm/amdgpu: add contiguous flag in ucode bo create

Hi Ray, I have tried to use GTT to store firmware on VF, but the driver failed to load, so I still use VRAM in this change. Regards, Horace. -Original Message- From: Huang Rui [mailto:ray.hu...@amd.com] Sent: Friday, June 09, 2017 9:54 PM To: Chen, Horace Cc: Wang@hr-amur2; Wang,

Re: [PATCH] drm/amdgpu: add contiguous flag in ucode bo create

On Fri, Jun 09, 2017 at 09:42:32PM +0800, horchen wrote: > Under VF environment, the ucode would be settled to the visible VRAM, > As it would be pinned to the visible VRAM, it's better to add > contiguous flag,otherwise it need to move gpu address during the pin > process. This movement is not

RE: [PATCH] drm/amdgpu: add contiguous flag in ucode bo create

Hi Christian, Sorry, it's my first time to submit code to the staging. I have done the fix. Attached the fixed review. Thank you for the review. Regards, Horace. -Original Message- From: Christian König [mailto:deathsim...@vodafone.de] Sent: Friday, June 09, 2017 8:25 PM To: Chen,

[PATCH] drm/amdgpu: add contiguous flag in ucode bo create

Under VF environment, the ucode would be settled to the visible VRAM, As it would be pinned to the visible VRAM, it's better to add contiguous flag,otherwise it need to move gpu address during the pin process. This movement is not necessary. Signed-off-by: horchen ---

Re: [Intel-gfx] [PATCH i-g-t] igt/kms_properties.c: fix test case for setting immutable properties

On 2017-06-09 08:22 AM, Arkadiusz Hiler wrote: > On Thu, Jun 08, 2017 at 04:06:44PM -0400, Bhawanpreet Lakha wrote: >> Test doesn't check if the property is immutable, and fails. >> Added conditions to detect if the property is immutable. >> >> Signed-off-by: Bhawanpreet Lakha

Re: [PATCH 1/2] drm/amdgpu/gfx: fix MEC interrupt enablement for pipes != 0

On 09/06/17 08:49 AM, Alex Deucher wrote: The interrupt registers are not indexed. Fixes: 763a47b8e (drm/amdgpu: teach amdgpu how to enable interrupts for any pipe v3) Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 57

Re: [PATCH 1/2] drm/amdgpu/gfx: fix MEC interrupt enablement for pipes != 0

Am 09.06.2017 um 14:49 schrieb Alex Deucher: The interrupt registers are not indexed. Fixes: 763a47b8e (drm/amdgpu: teach amdgpu how to enable interrupts for any pipe v3) Signed-off-by: Alex Deucher . Acked-by: Christian König . ---

Re: [PATCH v5 5/6] drm/amdgpu: move hw generation check into amdgpu_doorbell_init

On Fri, Jun 9, 2017 at 11:59 AM, Christian König wrote: > From: Christian König > > This way we can savely call it on SI as well. s/savely/safely FWIW, Reviewed-by: Andy Shevchenko > Signed-off-by: Christian König

RE: [PATCH 2/2] drm/amdgpu/gfx: spread queues across pipes again for 1 MEC parts

Please include patch 1 of this series as well. From: S, Shirish Sent: Friday, June 09, 2017 8:53 AM To: amd-gfx@lists.freedesktop.org; Alex Deucher Cc: Deucher, Alexander Subject: Re: [PATCH 2/2] drm/amdgpu/gfx: spread queues across pipes again for 1 MEC parts Sure Alex. I shall update the

Re: [PATCH 2/2] drm/amdgpu/gfx: spread queues across pipes again for 1 MEC parts

Sure Alex. I shall update the result on stoney soon. Regards, Shirish S From: Alex Deucher Sent: Friday, June 9, 2017 6:19:30 PM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander; S, Shirish Subject: [PATCH 2/2] drm/amdgpu/gfx: spread

[PATCH 2/2] drm/amdgpu/gfx: spread queues across pipes again for 1 MEC parts

Now that interrupts are properly enabled for all pipes, this should be function properly. Cc: Shirish S Signed-off-by: Alex Deucher --- Shirish, Can you test this change on your Stoney setup? drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 12

[PATCH 1/2] drm/amdgpu/gfx: fix MEC interrupt enablement for pipes != 0

The interrupt registers are not indexed. Fixes: 763a47b8e (drm/amdgpu: teach amdgpu how to enable interrupts for any pipe v3) Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 57 +++--

Re: [PATCH] drm/amdgpu: add contiguous flag in ucode bo create

Am 09.06.2017 um 13:59 schrieb horchen: Under VF environment, the ucode would be settled to the visible VRAM, As it would be pinned to the visible VRAM, it's better to add contiguous flag,otherwise it need to move gpu address during the pin process. This movement is not necessary.

Re: [Intel-gfx] [PATCH i-g-t] igt/kms_properties.c: fix test case for setting immutable properties

On Thu, Jun 08, 2017 at 04:06:44PM -0400, Bhawanpreet Lakha wrote: > Test doesn't check if the property is immutable, and fails. > Added conditions to detect if the property is immutable. > > Signed-off-by: Bhawanpreet Lakha > --- > tests/kms_properties.c | 6 +- >

RE: [PATCH] drm/amdgpu: add contiguous flag in ucode bo create

Done it, thanks for the review. Regards, Horace. -Original Message- From: Christian König [mailto:deathsim...@vodafone.de] Sent: Friday, June 09, 2017 7:16 PM To: Chen, Horace; amd-gfx@lists.freedesktop.org Cc: Huang, Ray Subject: Re: [PATCH] drm/amdgpu: add contiguous flag in ucode bo

[PATCH] drm/amdgpu: add contiguous flag in ucode bo create

Under VF environment, the ucode would be settled to the visible VRAM, As it would be pinned to the visible VRAM, it's better to add contiguous flag,otherwise it need to move gpu address during the pin process. This movement is not necessary. Signed-off-by: horchen ---

RE: [PATCH 2/2] drm/amdgpu: add sysfs for current gpu voltage.

> -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Rex Zhu > Sent: Friday, June 09, 2017 4:20 AM > To: amd-gfx@lists.freedesktop.org > Cc: Zhu, Rex > Subject: [PATCH 2/2] drm/amdgpu: add sysfs for current gpu voltage. Do we want to expose

RE: [PATCH 1/2] drm/amd/powerplay: implement gpu voltage display for smu7_hwmgr.

> -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Rex Zhu > Sent: Friday, June 09, 2017 4:19 AM > To: amd-gfx@lists.freedesktop.org > Cc: Zhu, Rex > Subject: [PATCH 1/2] drm/amd/powerplay: implement gpu voltage display > for smu7_hwmgr. > >

[PATCH] drm/amdgpu:ucode bo init add contiguous flag

Under VF environment, the ucode would be settled to the visible VRAM, As it would be pinned to the visible VRAM, it's better to add contiguous flag,otherwise it need to move gpu address during the pin process. This movement is not necessary. Signed-off-by: horchen ---

Re: [PATCH] drm/amdgpu: add contiguous flag in ucode bo create

Am 09.06.2017 um 12:55 schrieb horchen: Under VF environment, the ucode would be settled to the visible VRAM, As it would be pinned to the visible VRAM, it's better to add contiguous flag,otherwise it need to move gpu address during the pin process. This movement is not necessary.

Re: [PATCH 7/8] drm/amdgpu: add plumbing for ctx priority changes

Am 09.06.2017 um 00:06 schrieb Andres Rodriguez: Introduce amdgpu_ctx_priority_get/put(). This a refcounted mechanism to change a context's priority. A context's priority will be set to the highest priority for which a request exists. If no active requests exist, the context will default to

RE: [PATCH] drm/amdgpu:ucode bo init add contiguous flag

Sorry, branch wrong, please ignore this. Regards, Horace. -Original Message- From: horchen [mailto:horace.c...@amd.com] Sent: Friday, June 09, 2017 5:19 PM To: amd-gfx@lists.freedesktop.org Cc: Huang, Ray; Chen, Horace Subject: [PATCH] drm/amdgpu:ucode bo init add contiguous flag Under

Re: [PATCH 8/8] drm/amdgpu: add interface for editing a foreign process's priority

Am 09.06.2017 um 00:06 schrieb Andres Rodriguez: The AMDGPU_SCHED_OP_PROCESS_PRIORITY_GET/PUT ioctls are used to set the priority of a different process in the current system. When all requests are dropped, the foreign process's contexts will be restored to the priority specified at context

Re: [PATCH 6/8] drm/amd/sched: allow clients to edit an entity's rq

Am 09.06.2017 um 00:06 schrieb Andres Rodriguez: This is useful for changing an entity's priority at runtime. Signed-off-by: Andres Rodriguez --- drivers/gpu/drm/amd/scheduler/gpu_scheduler.c | 26 +++--- drivers/gpu/drm/amd/scheduler/gpu_scheduler.h

[PATCH] drm/amdgpu: add contiguous flag in ucode bo create

Under VF environment, the ucode would be settled to the visible VRAM, As it would be pinned to the visible VRAM, it's better to add contiguous flag,otherwise it need to move gpu address during the pin process. This movement is not necessary. Signed-off-by: horchen ---

Re: [PATCH 5/8] drm/amdgpu: move priority decay logic into amd_sched_priority_ctr

Am 09.06.2017 um 00:06 schrieb Andres Rodriguez: So that it can be re-used. A priority counter can be used to track priority requests. If no active requests exists, the counter will default to ()->default_priority. The re-factored version is now allowed to decay below NORMAL. This allows us to

Re: [PATCH 2/8] drm/amdgpu: add framework for HW specific priority settings v8

Am 09.06.2017 um 00:06 schrieb Andres Rodriguez: Add an initial framework for changing the HW priorities of rings. The framework allows requesting priority changes for the lifetime of an amdgpu_job. After the job completes the priority will decay to the next lowest priority for which a request

Re: [Intel-gfx] [PATCH i-g-t] tests: Increase value of I915_MAX_PIPES to 6

On Thu, Jun 08, 2017 at 09:48:58PM +, Deucher, Alexander wrote: > > -Original Message- > > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > > Of sunpeng...@amd.com > > Sent: Thursday, June 08, 2017 3:11 PM > > To: intel-...@lists.freedesktop.org;

Re: [PATCH 2/2] drm/amdgpu: add sysfs for current gpu voltage.

Am 09.06.2017 um 10:19 schrieb Rex Zhu: Change-Id: I348f9307c8e03e193df481e6c9faf234039d97b5 Signed-off-by: Rex Zhu --- drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h | 4 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 50 + 2 files changed, 54

Re: [PATCH v6 5/5] drm/amdgpu: resize VRAM BAR for CPU access v2

Am 07.06.2017 um 01:10 schrieb Bjorn Helgaas: [SNIP] What if the driver did something like this: pci_disable_decoding(dev, IORESOURCE_MEM); pci_release_resource(dev, 2); pci_resize_bar(dev, bar, size); pci_assign_resources(dev); pci_enable_decoding(dev, IORESOURCE_MEM); That

[PATCH v5 2/6] PCI: add resizeable BAR infrastructure v5

From: Christian König Just the defines and helper functions to read the possible sizes of a BAR and update it's size. See https://pcisig.com/sites/default/files/specification_documents/ECN_Resizable-BAR_24Apr2008.pdf and PCIe r3.1, sec 7.22. This is useful for

Resizeable PCI BAR support V5

Hi everyone, This is the fith incarnation of this set of patches. It enables device drivers to resize and most likely also relocate the PCI BAR of devices they manage to allow the CPU to access all of the device local memory at once. This is very useful for GFX device drivers where the default

[PATCH v5 1/6] PCI: add a define for the PCI resource type mask v2

From: Christian König We use this mask multiple times in the bus setup. v2: fix some style nit picks Signed-off-by: Christian König Reviewed-by: Andy Shevchenko --- drivers/pci/pci.h | 4

[PATCH v5 6/6] drm/amdgpu: resize VRAM BAR for CPU access v3

From: Christian König Try to resize BAR0 to let CPU access all of VRAM. v2: rebased, style cleanups, disable mem decode before resize, handle gmc_v9 as well, round size up to power of two. v3: handle gmc_v6 as well, release and reassign all BARs in the driver.

[PATCH v5 3/6] PCI: add functionality for resizing resources v6

From: Christian König This allows device drivers to request resizing their BARs. The function only tries to reprogram the windows of the bridge directly above the requesting device and only the BAR of the same type (usually mem, 64bit, prefetchable). This is done to

[PATCH v5 5/6] drm/amdgpu: move hw generation check into amdgpu_doorbell_init

From: Christian König This way we can savely call it on SI as well. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 17 - 1 file changed, 12 insertions(+), 5 deletions(-) diff --git

[PATCH v5 4/6] x86/PCI: Enable a 64bit BAR on AMD Family 15h (Models 30h-3fh) Processors v4

From: Christian König Most BIOS don't enable this because of compatibility reasons. Manually enable a 64bit BAR of 64GB size so that we have enough room for PCI devices. v2: style cleanups, increase size, add resource name, set correct flags, print message that

[PATCH 2/2] drm/amdgpu: add sysfs for current gpu voltage.

Change-Id: I348f9307c8e03e193df481e6c9faf234039d97b5 Signed-off-by: Rex Zhu --- drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h | 4 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 50 + 2 files changed, 54 insertions(+) diff --git

[PATCH 1/2] drm/amd/powerplay: implement gpu voltage display for smu7_hwmgr.

Change-Id: I4fca04d24e6b11ab0b036451da61d58114534e6c Signed-off-by: Rex Zhu --- drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 24 ++ drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 31 +++