> -Original Message-
> From: Liu, Monk
> Sent: Thursday, September 21, 2017 11:37 PM
> To: Deucher, Alexander; amd-gfx@lists.freedesktop.org
> Subject: RE: [PATCH 2/4] drm/amdgpu/sriov:alloc KIQ MQD in VRAM
>
> Alex
>
> Since CPU visible VRAM resource is very limited, I'm not sure BM like
Alex
Since CPU visible VRAM resource is very limited, I'm not sure BM like it or
not,
Besides, after we unify the code we'll forget why we do this on SRIOV and in
future someone will change it back to GTT domain (some guy care bare-metal
only) and lead to SRIOV issues and that time it's hard t
[Hari, can you comment on the last paragraph below regarding the events
limit? Would it hurt the runtime much to lose 8 signals out of 4096?]
Hi Oded,
I'm looking into upstreaming some event handling enhancements. I see
that you actually worked on increasing the number of events to 4096 and
worki
When many wavefronts cause VM faults at the same time, it can
overwhelm the interrupt handler and cause IH ring overflows before
the driver can notify or kill the faulting application.
As a workaround I'm introducing limited per-VM fault credit. After
that number of VM faults have occurred, furthe
The AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE ioctls are used to set
the priority of a different process in the current system.
When a request is dropped, the process's contexts will be
restored to the priority specified at context creation time.
A request can be dropped by setting the override p
Introduce amdgpu_ctx_priority_override(). A mechanism to override a
context's priority.
An override can be terminated by setting the override to
AMD_SCHED_PRIORITY_UNSET.
v2: change refcounted interface for a direct set
Signed-off-by: Andres Rodriguez
Acked-by: Christian König
---
drivers/gpu
This is useful for changing an entity's priority at runtime.
v2: don't modify the order of amd_sched_entity members
Signed-off-by: Andres Rodriguez
Acked-by: Christian König
---
drivers/gpu/drm/amd/scheduler/gpu_scheduler.c | 24 ++--
drivers/gpu/drm/amd/scheduler/gpu_sched
Returning invalid priorities as _NORMAL is a backwards compatibility
quirk of amdgpu_ctx_ioctl(). Move this detail one layer up where it
belongs.
Signed-off-by: Andres Rodriguez
Acked-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 8 +---
drivers/gpu/drm/amd/schedul
Add an initial framework for changing the HW priorities of rings. The
framework allows requesting priority changes for the lifetime of an
amdgpu_job. After the job completes the priority will decay to the next
lowest priority for which a request is still valid.
A new ring function set_priority() c
Use _INVALID to identify bad parameters and _UNSET to represent the
lack of interest in a specific value.
Signed-off-by: Andres Rodriguez
Acked-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 2 ++
drivers/gpu/drm/amd/scheduler/gpu_scheduler.h | 3 ++-
include/uapi/drm/a
Add a new context creation parameter to express a global context priority.
The priority ranking in descending order is as follows:
* AMDGPU_CTX_PRIORITY_HIGH_HW
* AMDGPU_CTX_PRIORITY_HIGH_SW
* AMDGPU_CTX_PRIORITY_NORMAL
* AMDGPU_CTX_PRIORITY_LOW_SW
* AMDGPU_CTX_PRIORITY_LOW_HW
The driver wil
Programming CP_HQD_QUEUE_PRIORITY enables a queue to take priority over
other queues on the same pipe. Multiple queues on a pipe are timesliced
so this gives us full precedence over other queues.
Programming CP_HQD_PIPE_PRIORITY changes the SPI_ARB_PRIORITY of the
wave as follows:
0x2: CS_
Just a rebase of v2 since it went a little stale.
Series available in the wip-process-priorities-v3 branch at:
git://people.freedesktop.org/~lostgoat/linux
Gpuvis trace with normal priority running steamvr, hellovr_vulkan and ssao
demo:
https://drive.google.com/open?id=0B2ygSoZuj3IMdFJ4bTZPcmh5aH
Am 21.09.2017 um 18:30 schrieb Samuel Li:
v2: drop hdp invalidate/flush.
v3: honor pgoff during prime mmap. Add a barrier after cpu access.
v4: drop begin/end_cpu_access() for now, revisit later.
Signed-off-by: Samuel Li
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu.
Patch is Reviewed-by: Christian König .
Regards,
Christian.
Am 21.09.2017 um 16:38 schrieb Andres Rodriguez:
Hi Christian,
The reference radv patches are on the list. The basic idea is to only
set the explicit sync flag for buffers allocated for dri usage.
Regards,
Andres
On 2017-09-19 09:
v2: drop hdp invalidate/flush.
v3: honor pgoff during prime mmap. Add a barrier after cpu access.
v4: drop begin/end_cpu_access() for now, revisit later.
Signed-off-by: Samuel Li
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 +
drivers/gpu/d
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Christian König
> Sent: Thursday, September 21, 2017 4:32 AM
> To: Christian König; amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/amdgpu: simplify pinning into visible VRAM
>
> Pin
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Monk Liu
> Sent: Thursday, September 21, 2017 3:12 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk
> Subject: [PATCH 4/4] drm/amdgpu:fix firmware memoryleak
>
> this fix memory leak du
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Monk Liu
> Sent: Thursday, September 21, 2017 3:12 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk
> Subject: [PATCH 3/4] drm/amdgpu:fix uvd ring fini routine(v2)
>
> fix missing finis
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Monk Liu
> Sent: Thursday, September 21, 2017 3:12 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk
> Subject: [PATCH 2/4] drm/amdgpu/sriov:alloc KIQ MQD in VRAM
>
> this way after KIQ
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Monk Liu
> Sent: Thursday, September 21, 2017 3:12 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk
> Subject: [PATCH 1/4] drm/amdgpu/sriov:unmap KCQ in gfx hw_fini
>
> Change-Id: Ieee4
Hi Christian,
The reference radv patches are on the list. The basic idea is to only
set the explicit sync flag for buffers allocated for dri usage.
Regards,
Andres
On 2017-09-19 09:24 AM, Christian König wrote:
Am 19.09.2017 um 14:59 schrieb Andres Rodriguez:
Introduce a flag to signal that
Am 21.09.2017 um 16:31 schrieb Li, Samuel:
Please just completely drop the begin_cpu_access() and end_cpu_access()
callbacks.
Checking other drivers the only one actually implementing something special
is the i915 driver which needs to remove the BO from the GTT domain for
cache coherency I think
> Please just completely drop the begin_cpu_access() and end_cpu_access()
> callbacks.
> Checking other drivers the only one actually implementing something special
> is the i915 driver which needs to remove the BO from the GTT domain for
> cache coherency I think.
Well, as the first step, we can
Ping?
Am 13.09.2017 um 10:32 schrieb Christian König:
From: Christian König
Just set the CPU access required flag when we pin it.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 23 ---
1 file changed, 8 insertions(+), 15 deletions(-)
d
I decide to cancel this fix, because it although can avoid the SAVE_VF fail,
but the next round driver loading will fail on KIQ, unless there is a VF FLR
inserted before driver loading, so I had another w/a for it, which allocates
MQD of KIQ on VRAM domain
Already sent out for review, thanks !
Am 21.09.2017 um 09:12 schrieb Monk Liu:
this way after KIQ MQD released in drv unloading, CPC
can still let KIQ access this MQD thus RLCV SAVE_VF
will not fail
Change-Id: Iccef37a70c193c83af80961dae2c67ed859f1a13
Signed-off-by: Monk Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 2 +-
1
Am 20.09.2017 um 22:31 schrieb Li, Samuel:
The waiting done here is only for the shared fence to switch from explicitly to
implicitly synchronization for correct interaction with the Intel driver.
Actually here it is going to wait for all fences,
94 ret = reservation_object_wait_timeout_
fix missing finish uvd enc_ring.
v2:
since the adev pointer check in already in ring_fini
so drop the check outsider
Change-Id: Ib74237ca5adcb3b128c9b751fced0b7db7b09e86
Signed-off-by: Monk Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 4
1 file changed, 4 insertions(+)
diff --git a/dr
this fix memory leak due to request_firmware after driver
unloaded
Change-Id: I7b4724deea0a095189c344eea3801e456e9cced0
Signed-off-by: Monk Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 6 ++
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 20
drivers/gpu/drm/amd/amdgpu/s
Change-Id: Ieee45a0127701ba946b5f8014ff0ac0a8a94a200
Signed-off-by: Monk Liu
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 57 ++
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 58 +++
2 files changed, 115 insertions(+)
diff --git a/drivers/
this way after KIQ MQD released in drv unloading, CPC
can still let KIQ access this MQD thus RLCV SAVE_VF
will not fail
Change-Id: Iccef37a70c193c83af80961dae2c67ed859f1a13
Signed-off-by: Monk Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Xiangliang.Yu
> Sent: Wednesday, September 20, 2017 11:22 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Yu, Xiangliang
> Subject: [PATCH] drm/amdgpu: Fix driver reloading failure
>
> SRIOV doe
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Monk Liu
> Sent: Wednesday, September 20, 2017 5:49 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk
> Subject: [PATCH] drm/amdgpu:fix firmware memoryleak
>
> this fix memory leak due t
Am 19.09.2017 um 19:07 schrieb Yong Zhao:
Use it to replace the hard coded value in amdgpu_vm_bo_update_mapping().
Change-Id: I85d89d401b8dbcf01ca9c55c281e552db874fde5
Signed-off-by: Yong Zhao
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 4
drivers/gpu/
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