On Tue, Jan 22, 2019 at 10:43 PM Evan Quan wrote:
>
> For those SKUs which support this feature only.
>
> Change-Id: I74de00204d93f951e04073e5c4c4ce9c0d34f662
> Signed-off-by: Evan Quan
Is there a minimum smu version number required to support this? Is it
safe to setup the structures and enable
For those SKUs which support this feature only.
Change-Id: I74de00204d93f951e04073e5c4c4ce9c0d34f662
Signed-off-by: Evan Quan
---
.../drm/amd/powerplay/hwmgr/vega10_hwmgr.c| 1 +
.../drm/amd/powerplay/hwmgr/vega10_thermal.c | 37 +++
.../drm/amd/powerplay/hwmgr/vega10_therm
MGPU fan boost related parameter is added.
Change-Id: Iaa6c570373d81199a07028f275b083f459952254
Signed-off-by: Evan Quan
---
.../drm/amd/powerplay/hwmgr/vega10_pptable.h | 24 +
.../powerplay/hwmgr/vega10_processpptables.c | 50 ++-
drivers/gpu/drm/amd/powerplay/inc/hwm
On Tue, 22 Jan 2019 at 21:56, Alex Deucher wrote:
>
> On Tue, Jan 22, 2019 at 4:19 AM Ard Biesheuvel
> wrote:
> >
> > On Mon, 21 Jan 2019 at 20:04, Michel Dänzer wrote:
> > >
> > > On 2019-01-21 7:28 p.m., Ard Biesheuvel wrote:
> > > > On Mon, 21 Jan 2019 at 19:24, Michel Dänzer wrote:
> > > >>
From: Marek Olšák
- move all adjustments into one place
- specify GDS/GWS/OA alignment in basic units of the heaps
- it looks like GDS alignment was 1 instead of 4
Signed-off-by: Marek Olšák
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c| 7 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
On Tue, Jan 22, 2019 at 4:19 AM Ard Biesheuvel
wrote:
>
> On Mon, 21 Jan 2019 at 20:04, Michel Dänzer wrote:
> >
> > On 2019-01-21 7:28 p.m., Ard Biesheuvel wrote:
> > > On Mon, 21 Jan 2019 at 19:24, Michel Dänzer wrote:
> > >> On 2019-01-21 7:20 p.m., Ard Biesheuvel wrote:
> > >>> On Mon, 21 Ja
From: Marek Olšák
I'm not increasing the DRM version because GDS isn't totally without bugs yet.
v2: update emit_ib_size
Signed-off-by: Marek Olšák
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h | 2 ++
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 19 +++-
drivers/gpu/drm/amd/amdgpu/gfx_v8
From: Nicholas Kazlauskas
[Why]
During any modeset the CRTC stream is removed and a new stream is added.
This new stream doesn't carry over CRC capture state if it was
previously set.
[How]
Re-program the stream for CRC capture. The existing DRM callback can
be re-used here for the most part - t
From: Nicholas Kazlauskas
[Why]
In order to read CRC events when CRC capture is enabled the vblank
interrput handler needs to be running for the CRTC. The handler is
enabled while there is an active vblank reference.
When running IGT tests there will often be no active vblank reference
but the t
From: Eric Yang
[Why]
This change causes regression for S4 resume where gamma is not
programmed. The change incorrectly updates the requested dpms_off
state.
This reverts commit d2b1d6bbc56afab8ebae9d52d7ca0ea3569bd600.
Signed-off-by: Eric Yang
Reviewed-by: Yongqiang Sun
Acked-by: Leo Li
---
From: Fatemeh Darbehani
[Why]
Enhanced sync need to use vertical_interrupt1.
[How]
Add vertical_interrupt1 source to irq manger,
Implment setup vline interrupt interface.
Signed-off-by: Fatemeh Darbehani
Reviewed-by: Jun Lei
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/core/dc.c
From: hersen wu
[Why] After call bios table crtc_source_select, dal will program fmt
again. The bios table program dig_source_select and other fmt register
for bios usage which is redundancy and uncessary.
[How] Program dig_soruce_select register directly
Signed-off-by: hersen wu
Reviewed-by:
From: Martin Tsai
[Why]
On current design, driver cannot handle the interrupt for
down reply when link training is processing. The DOWN REQ
send before link training will keep in the pending DOWN REP
state in the queue.
It makes the next DOWN REQ be queued until time out.
[How]
To add a polling
From: Eric Yang
[why]
Previously we incorrectly skipped backlight control when stream is
present but dpms_off = true. This causes backlight to remain on in
the we boot up or resume into a external display only configuration
where VBIOS posted on the eDP.
[How]
Add dpms_off into the condition for
From: David Francis
[Why]
amdgpu_dm_commit_planes was performing multi-plane
flips incorrectly:
It waited for vblank once per flipped plane
It prepared flip ISR and acquired the corresponding vblank ref
once per plane, although it closed ISR and put the ref once
per crtc
It called into dc once
From: David Francis
[Why]
DC was assuming that any surface_update->scaling_info
meant the update was at least medium. However, if nothing
has changed there is no scaling to program, so there is
no problem with the update being fast
[How]
If every update flag is not set, the update is fast
Sign
From: Krunoslav Kovac
[Why] Our output TF calculation doesn't work if no user-specified gamma
correction. Normally, user provides this, but driver sohuld just assume
default (linear) gamma otherwise.
[How] Remove output TF dependency on user gamma being provided.
Signed-off-by: Krunoslav Kovac
From: Josip Pavic
[Why]
Current date based versioning doesn't tell us about feature version
and build version, and is not useful for debug.
[How]
Add versioning based on feature and build
Signed-off-by: Josip Pavic
Reviewed-by: Anthony Koo
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc
From: David Francis
[Why]
We were assuming that any commit with allow_modeset == false
was a pageflip. This was against drm intention and only
worked by sheer luck
[How]
A pageflip is the change from one framebuffer to another
Signed-off-by: David Francis
Reviewed-by: Harry Wentland
Reviewed
From: Josip Pavic
[Why]
Need method of detecting which version of the DMCU FW is loaded and
load the appropriate iRAM.
[How]
Create definition for ABM 2.2 iRAM, and load it if the DMCU FW version
number matches the ABM 2.2 version; otherwise load ABM 2.1 iRAM.
Signed-off-by: Josip Pavic
Review
From: David Francis
[Why]
Our old logic: if pageflip, update freesync and plane address.
Otherwise, update everything.
This over-updated on non-pageflip cases, and it failed to
update if pageflip and non-pageflip changes occurred on
the same commit
[How]
Update flip_addrs on pageflips.
Update sc
From: John Barberiz
[Why]
An uninitialized variable would randomly initialize to a large
value. This caused enough delay to fail DP Compliance Test 400.2.1.
[How]
Initialize the variable.
Signed-off-by: John Barberiz
Reviewed-by: Wenjing Liu
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/
From: Steven Chiu
Signed-off-by: Steven Chiu
Reviewed-by: Aric Cyr
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index f362b04..8391bc3 100
From: Josip Pavic
[Why]
Improved contrast in ABM 2.2 is desired
[How]
Increase the contrast factor for ABM levels 2, 3 and 4
Signed-off-by: Josip Pavic
Reviewed-by: Anthony Koo
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/modules/power/power_helpers.c | 6 +++---
1 file changed, 3 inser
From: Leo Li
Summary of change:
* Fixes for pageflipping logic
* Multiplane flipping support
* Make it more atomic
* Fix CRC capture on pipes with no active vblank reference
* Simplify commit for scaling and ABM changes
David Francis (5):
drm/amd/display: Simplify underscan and ABM co
From: Eryk Brol
[Why]
Change DCN10 hubbub to use hubbub as a base and allow all future DCN
hubbubs to do the same instead of using DCN10_hubbub. This increases
readability and doesn't require future hubbubs to inherit anything
other than the base hubbub struct.
[How]
Create separate DCN10_hubbub
From: David Francis
[Why]
Underscan and ABM are connector properties but require updates
to DC stream state. Previously, on updates to these properties
the affected stream and all its planes were committed.
This is unnecessary; only a few fields on the stream need
to be changed.
[How]
If scalin
From: Eryk Brol
Virtual memory allows display to support flipping to surfaces which
are not allocated contiguously in memory with physical addresses,
instead a 1-4 level page table is used.
This is beneficial because it allows the scattering of large surfaces
to improve memory efficiency and sec
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Alex Deucher (1):
amdgpu: update to latest marketing names from 18.50
Andrey Grodzovsky (3):
amdgpu/test: Add illegal register and memory access test v2
amdgpu/test: Disable deadlock tests for all non gfx8/9 ASICs.
amdgpu/te
Hi,
[This is an automated email]
This commit has been processed because it contains a -stable tag.
The stable tag indicates that it's relevant for the following trees: all
The bot has tested the following trees: v4.20.3, v4.19.16, v4.14.94, v4.9.151,
v4.4.171, v3.18.132.
v4.20.3: Build OK!
v4.
On Mon, 21 Jan 2019 at 20:04, Michel Dänzer wrote:
>
> On 2019-01-21 7:28 p.m., Ard Biesheuvel wrote:
> > On Mon, 21 Jan 2019 at 19:24, Michel Dänzer wrote:
> >> On 2019-01-21 7:20 p.m., Ard Biesheuvel wrote:
> >>> On Mon, 21 Jan 2019 at 19:04, Michel Dänzer wrote:
> On 2019-01-21 6:59 p.m.
since vm_size enlarged to 0x4 GB,
sriov need to put csa below AMDGPU_GMC_HOLE.
or amdgpu_vm_alloc_pts would receive saddr among AMDGPU_GMC_HOLE,
and result in a range fault interrupt IIRC.
Change-Id: I405a25a01d949f3130889b346f71bedad8ebcae7
Signed-off-by: Wenta Lou
---
drivers/gpu/drm/amd/a
Am 22.01.19 um 00:46 schrieb Marek Olšák:
From: Marek Olšák
I'm not increasing the DRM version because GDS isn't totally without bugs yet.
Looks mostly good on first glance.
But one things that is certainly wrong is when you add any
amdgpu_ring_write() call to the emit_ibs callback you also
On Mon, Jan 21, 2019 at 11:13 PM Sam Ravnborg wrote:
>
> Hi Daniel et al.
>
> > >
> > > Yeah the drm_crtc_helper.h header is a bit the miniature drmP.h for legacy
> > > kms drivers. Just removing it from all the atomic drivers caused lots of
> > > fallout, I expect even more if you entirely remove
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